L10C23 L10C23 DEVICES INCORPORATED 64-bit Digital Correlator 64-bit Digital Correlator DEVICES INCORPORATED FEATURES DESCRIPTION ❑ High Speed (50 MHz), Low Power (125 mW), CMOS 64-bit Digital Correlator ❑ Replaces Fairchild TDC1023/TMC2023 ❑ Bit Can be Selectively Masked ❑ Three-State Outputs ❑ 24-pin PDIP The L10C23 is a high speed CMOS 64-bit digital correlator. It is pin-forpin equivalent to the Fairchild TDC1023/TMC2023. The L10C23 operates over the full military ambient temperature range using advanced CMOS technology. The L10C23 produces the 7-bit correlation score of two input words of up to 64 bits, denoted A and B. The A and B inputs are serially shifted into two independently clocked 64-bit registers. The A register is clocked on L10C23 BLOCK DIAGRAM BOUT AOUT AIN CLK A A1 A2 A64 C LATCH B64 B2 B1 BIN CLK B C64 C2 C1 LCL MOUT M64 M2 M1 MIN CLK M 7 THRESHOLD REG CLK S 3-STAGE PIPELINED CLK S REGISTER DIGITAL REGISTER SUMMER REGISTER 7 INV COMPARATOR CLK S 7 OE R6-0 The outputs of the B register drive a 64-bit transparent latch, denoted the C latch. The C latch is controlled by the LCL (Load C Latch) input. A HIGH level on the LCL input causes the C latch to be transparent, allowing the contents of the B register to be applied directly to the correlator array. When the LCL input is LOW, the data in the C latch is held, so that the B input may be loaded with a new correlation reference without affecting the current reference value stored in C. Each bit in the A register is exclusive NOR’ed with the corresponding bit in the C latch, implementing a single bit multiplication at each bit position. The mask register, denoted by M, is a third 64-bit register, which is serially loaded from the M input on the rising edge of CLK M. Bit positions in the M register which are set to zero mask the corresponding bits in the A and C registers from participating in the correlation score. This can be used to reduce the effective length of the correlation, or to correlate against only one channel of a bit-multiplexed datastream without deinterleaving the data. The output of the masking process is a 64bit vector which contains ones in the locations in which A and B data match, and which are unmasked (M register contains a ‘1’). This 64-bit vector is applied to a pipelined digital summer which calculates the total number of ones in the vector (the correlation score). The summer network contains three pipeline stages, which are clocked on the rising edge of CLK S. Calculation of a 7 D Q CLK C the rising edge of CLK A, and the B register is clocked on the rising edge of CLK B. CFL Special Arithmetic Functions 1 08/16/2000–LDS.23-K L10C23 DEVICES INCORPORATED correlation score therefore requires three clock cycles, but a new result can be obtained on each cycle once the pipeline is filled. Because a portion of the summer logic is located between the input registers and the first pipeline register, some timing restrictions exist between CLK S and CLK A, CLK B, or CLK M. CLK S may be tied to an input clock (usually CLK A) to obtain a continuously updated correlation score, delayed by three cycles from the data. Under this condition, CLK S may be skewed later than CLK A by no more than tSK to assure that the A register outputs have not changed before the S clock occurs. Alternatively, CLK S may be asyncronous to the input clocks, as long as data is stable at the pipeline register inputs prior to the CLK S rising edge. This condition can be met by assuring that CLK S occurs at least tPS after the input clock. The summer output represents a count of the number of matching positions in the input data streams. This 7-bit result can be inverted (one’s complemented) by loading a ‘1’ into the INV register. 64-bit Digital Correlator Correlation values which exceed a predetermined threshold can be detected via the Threshold register and Comparator. The Threshold register is loaded with a 7-bit value via the R 6-0 pins at the rising edge of CLK C and while OE is HIGH. To achieve synchronization with the digital summer, the Threshold register contents are fed into pipeline registers clocked by CLK S. The compare flag output (CFL) goes HIGH when the summer output is equal to or greater than the contents of the Threshold register. Cascading the L10C23 devices for longer correlation lengths and more bits of reference or data precision is easily accomplished. The A, B, and M registers have serial outputs to directly drive the corresponding inputs of succeeding devices. The correlation scores of multiple devices in such a system should be added together to obtain the overall correlation score. Correlation on data exceeding one bit of precision can be accomplished by first calculating single-bit correlation scores at each bit position, then adding the results after weighting them appropriately. Thus, one L10C23 would be used for each bit of precision in the data. LOGIC Devices’ L4C381 16-bit ALU can be used to assist in adding the outputs of several L10C23 correlators. When adding several 7-bit correlation scores, advantage can be taken of the fact that the sum of two 7-bit numbers will not exceed 8 bits. Thus the L4C381 can simultaneously perform two 7-bit additions. The first two operands are applied to A6 -0 and B 6 -0, with the result appearing on F 7 -0. The second pair of operands are applied to A14 -8 and B14 -8, with the result appearing in F15 -8. The unused inputs are tied to ground. If it can be guaranteed that at least one of the input scores will not reach its maximum value of 64, then this technique can also be applied in the second tier of adders. In this case, while the inputs have 8 bits of precision, the maximum value that their sum can assume is 255, which is expressable in 8 bits. Alternatively, when performing long correlations on relatively slow datastreams, one L4C381 can be configured using its feedback mode to accumulate the correlation scores of a number of L10C23s. To accomplish this, the outputs of all the correlators are tied together on a three-state bus. Each one is sequentially enabled and clocked into the L4C381, which accumulates the total resulting score. Special Arithmetic Functions 2 08/16/2000–LDS.23-K L10C23 DEVICES INCORPORATED 64-bit Digital Correlator MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Active Operation, Commercial Active Operation, Military Supply Voltage 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –2.0 mA VOL Output Low Voltage VCC = Min., IOL = 4.0 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current IOZ Typ Max 3.5 Unit V 0.5 V 2.0 VCC V 0.0 0.8 V Ground ≤ VIN ≤ VCC (Note 12) ±20 µA Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 100 mA ICC2 VCC Current, Quiescent (Note 7) 0.5 mA 25 Special Arithmetic Functions 3 08/16/2000–LDS.23-K L10C23 DEVICES INCORPORATED 64-bit Digital Correlator SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) Symbol Parameter tPABM A, B, M Clock Period tPW A, B, M, S, C Clock Pulse Width tS Input Setup Time tH Input Hold Time tBLCL B Clock to LCL Hold tCS C Clock to S Clock tDABM A, B, M Clock to A, B, M Out tPS S Clock Period, A, B, M Clock to S Clock Delay tSK A, B, M Clock to S Clock Skew (Note 8) tDR S Clock to R6-0 tDC S Clock to CFL tENA Output Enable Time (Note 11) tDIS Output Disable Time (Note 11) L10C23– 1234567890123456 1234567890123456 1234567890123456 * 50 30 20 1234567890123456 1234567890123456 1234567890123456 Min Max Min Max Min Max 1234567890123456 1234567890123456 50 28 20 1234567890123456 1234567890123456 1234567890123456 1234567890123456 20 12 8 1234567890123456 1234567890123456 1234567890123456 20 10 10 1234567890123456 1234567890123456 1234567890123456 0 0 0 1234567890123456 1234567890123456 1234567890123456 20 12 8 1234567890123456 1234567890123456 1234567890123456 50 28 20 1234567890123456 1234567890123456 1234567890123456 1234567890123456 25 20 18 1234567890123456 1234567890123456 1234567890123456 50 28 20 1234567890123456 1234567890123456 1234567890123456 3 3 3 1234567890123456 1234567890123456 1234567890123456 35 30 22 1234567890123456 1234567890123456 1234567890123456 1234567890123456 25 20 18 1234567890123456 1234567890123456 1234567890123456 30 18 16 1234567890123456 1234567890123456 1234567890123456 35 16 14 1234567890123456 123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE 123456789012345678901234 SWITCHING WAVEFORMS tPS tS tPW tH A, B, M DATA tPW tPW CLK A, B, M tDABM A, B, M OUT tBLCL LCL tPS tSK tPW tPW CLK S tCS CLK C tPW OE tDR tDIS R6-0 OUT tS tH IN tENA OUT tDC CFL Special Arithmetic Functions 4 08/16/2000–LDS.23-K L10C23 DEVICES INCORPORATED 64-bit Digital Correlator SWITCHING CHARACTERISTICS MILITARY OPERATING RANGE (-55°C to +125°C) Notes 9, 10 (ns) Symbol Parameter tPABM A, B, M Clock Period tPW A, B, M, S, C Clock Pulse Width tS Input Setup Time tH Input Hold Time tBLCL B Clock to LCL Hold tCS C Clock to S Clock tDABM A, B, M Clock to A, B, M Out tPS S Clock Period, A, B, M Clock to S Clock Delay tSK A, B, M Clock to S Clock Skew (Note 8) tDR S Clock to R6-0 tDC S Clock to CFL tENA Output Enable Time (Note 11) tDIS Output Disable Time (Note 11) L10C23– 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 * 60 35* 20* 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 Min Max Min Max Min Max 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 58 33 20 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 20 14 8 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 22 12 12 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 0 0 0 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 20 14 8 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 58 33 20 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 30 23 20 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 58 33 20 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 3 3 3 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 40 35 27 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 30 23 18 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 35 20 18 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 40 18 16 1234567890123456789012345678901212345678901234 123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE 123456789012345678901234 SWITCHING WAVEFORMS tPS tS tPW tH A, B, M DATA tPW tPW CLK A, B, M tDABM A, B, M OUT tBLCL LCL tPS tSK tPW tPW CLK S tCS CLK C tPW OE tDR tDIS R6-0 OUT tS tH IN tENA OUT tDC CFL Special Arithmetic Functions 5 08/16/2000–LDS.23-K L10C23 DEVICES INCORPORATED 64-bit Digital Correlator NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minN = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT S1 DUT IOL VTH CL IOH FIGURE B. THRESHOLD LEVELS tENA OE Z tDIS 1.5 V 1.5 V 3.5V Vth 0 1.5 V 1.5 V Z 1 VOL* 0.2 V VOH* 0.2 V 0 Z 1 Z 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. Special Arithmetic Functions 6 08/16/2000–LDS.23-K L10C23 DEVICES INCORPORATED 64-bit Digital Correlator ORDERING INFORMATION 24-pin — 0.3" wide VCC MIN AIN BIN CLK C CLK S INV OE R6 R5 R4 R3 Speed 24-pin — 0.6" wide 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK B CLK M CLK A LCL MOUT AOUT BOUT CFL GND R0 R1 R2 VCC MIN AIN BIN CLK C CLK S INV OE R6 R5 R4 R3 Plastic DIP (P1) Plastic DIP (P2) 0°C to +70°C — COMMERCIAL SCREENING 30 ns 20 ns L10C23PC30 L10C23PC20 L10C23NC30 L10C23NC20 –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK B CLK M CLK A LCL MOUT AOUT BOUT CFL GND R0 R1 R2 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 Ceramic DIP 1234567890123456789012345 1234567890123456789012345 (C4) 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 Discontinued Package 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 1234567890123456789012345 Special Arithmetic Functions 7 08/16/2000–LDS.23-K