19-6261; Rev 0; 4/12 EVALUATION KIT AVAILABLE MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter General Description The MAX5986A/MAX5987A provide a complete powersupply solution as IEEE® 802.3af-compliant Class 1 Powered Devices (PDs) in a Power-over-Ethernet (PoE) system. The MAX5986A/MAX5987A integrate the PD interface with an efficient DC-DC converter, offering a low external part count PD solution. The MAX5987A includes a low-dropout regulator and the MAX5986A includes sleep and ultra-low power modes. The PD interface provides a detection signature and a Class 1 classification signature with a single external resistor. The PD interface also provides an isolation power MOSFET, a 60mA (max) inrush current limit, and a 201mA (typ) operating current limit. The integrated step-down DC-DC converter uses a peak current-mode control scheme and provides an easy-toimplement architecture with a fast transient response. The step-down converter operates in a wide input voltage range from 8.7V to 60V and supports up to 3.84W of input power at 1.15A load. The DC-DC converter operates at a fixed 275kHz switching frequency, with an efficiency-boosting frequency foldback that reduces the switching frequency by half at light loads. The devices feature an input undervoltage-lockout (UVLO) with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure glitch-free transition during power-on/-off conditions. The devices also feature overtemperature shutdown, short-circuit protection, output overvoltage protection, and hiccup current limit for enhanced performance and reliability. Benefits and Features S IEEE 802.3af Compliant S PoE Class 1 Classification S Simplified Wall Adapter Interface S Efficient, Integrated DC-DC Converter (with Integrated Switches) S 8.7V to 60V Wide Input Voltage Range S 3.0V to 5.6V Programmable Output Voltage Range S Internal Compensation S Fixed 275kHz Switching Frequency S Frequency Foldback for High-Efficiency LightLoad Operation S Built-In Output-Voltage Monitoring S Open-Drain RESET Output (MAX5987A) S Protects Against Overload, Output Short Circuit, Output Overvoltage, and Overtemperature S Hiccup-Mode Runaway Current Limit S Back-Bias Capability to Optimize the Efficiency S Integrated TVS Diode Withstands Cable Discharge Event (CDE) S Internal LDO Regulator with Up to 100mA Load (MAX5987A) S Fixed 3.3V or Adjustable Output Voltage Through an External Resistive Divider S 49mA (typ) Inrush Current Limit S Pass 2kV, 200m CAT-6 Cable Discharge Event The MAX5986A/MAX5987A are available in a 16-pin, 5mm x 5mm, TQFN power package and operate over the -40°C to +85°C temperature range. Applications IEEE 802.3af-Powered Devices IP Phones Wireless Access Nodes IP Security Cameras Ordering Information appears at end of data sheet. WiMAX® Base Stations IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc. WiMAX is a registered certification mark and registered service mark of WiMAX Forum. For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX5986A/MAX5987A.related. ����������������������������������������������������������������� Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND, unless otherwise noted.) VDD to GND............................................................-0.3V to +70V (100V, 100ms, RTEST = 3.3kω) (Note 1) VCC, WAD, RREF to GND......................... -0.3V to (VDD + 0.3V) AUX, LDO_IN, LED to GND..................................... -0.3V to 16V LDO_OUT to GND............................... -0.3V to (LDO_IN + 0.3V) LDO_FB to GND.......................................................-0.3V to +6V LX to GND................................................. -0.3V to (VCC + 0.3V) LDO_OUT, VDRV, FB, RESET, WK, SL, ULP, to GND...............................................................-0.3V to +6V VDRV to VDD............................................. -0.3V to (VDD + 0.3V) PGND to GND.......................................................-0.3V to +0.3V LX Total RMS Current............................................................1.6A Continuous Power Dissipation (TA = + 70NC) TQFN (derate 28.6mW/NC above +70NC)...............2285.7mW Operating Temperature Range........................... -40NC to +85NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Note 1: See Figure 1, Test Circuit. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 2) Junction-to-Ambient Thermal Resistance (qJA)...............35°C/W Junction-to-Case Thermal Resistance (qJC)...................2.7°C/W Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND, C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected. All voltages are referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 FA 25.5 kI POWER DEVICE (PD) INTERFACE DETECTION MODE Input Offset Current Effective Differential Input Resistance IOFFSET dR VVDD = 1.4V to 10.1V (Note 4) VVDD = 1.4V to 10.1V with 1V step, (Note 5) 23.95 CLASSIFICATION MODE Classification Enable Threshold VTH,CLS,EN VDD rising 10.2 11.42 12.5 V Classification Disable Threshold VTH,CLS,DIS VDD rising 22 23 23.8 V Classification Stability Time Classification Current 2 ICLASS VDD = 12.6V to 20V 9.12 ms 11.88 mA POWER MODE VDD Supply Voltage Range VDD VDD Supply Current IDD VDD = 60V VDD Turn-On Voltage VON VDD rising VDD Turn-Off Voltage VOFF VDD falling MAX5986A 34.3 MAX5987A 60 V 3.6 4.5 mA 35.7 37.6 38.7 30 31.4 V V ����������������������������������������������������������������� Maxim Integrated Products 2 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter ELECTRICAL CHARACTERISTICS (continued) (VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND, C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected. All voltages are referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER VDD Turn-On/Off Hysteresis VDD Deglitch Time Inrush to Operating Mode Delay Isolation Power MOSFET On-Resistance SYMBOL VHYST_UVLO tOFF_DLY tDELAY CONDITIONS MAX5986A (Note 6) MIN TYP 3.4 4.2 MAX5987A 100 75 90 UNITS V 7.2 VDD falling from 40V to 20V (Note 5) tDELAY = time from a (VDD - VCC) 1.5V to 0V step to DC-DC converter turn-on MAX Fs 110 ms TJ = +25NC 1.2 TJ = +85NC 1.5 2.2 39 49 60 mA 175 201 226 mA 8.8 V RON_ISO IVCC = 100mA IINRUSH During initial turn-on period, VDD - VCC = 4V, measured at VCC After inrush completed, VCC = VDD - 1.5V, measured at VCC I CURRENT LIMIT Inrush Current Limit Current Limit During Normal Operation ILIM WAD Detection Rising Threshold VWAD_RISE WAD Detection Falling Threshold VWAD_FALL 5.8 WAD Detection Hysteresis WAD Input Current IWAD VWAD = 24V V 0.6 V 125 FA INTERNAL REGULATOR WITH BACK BIAS VAUX Input Voltage Range VAUX Inferred from VAUX input current 4.75 14 V VAUX from 4.75V to 14V 0.65 3.1 mA 4.2 5.5 V VWK falling and VULP rising and falling 1.6 2.9 V SL Logic Threshold Falling 0.55 SL Current V SL = 0V VAUX Input Current VDRV Output Voltage SLEEP MODE (MAX5986A) WK and ULP Logic Threshold LED Current Amplitude VTH ILED 0.8 62.5 R SL = 60.4kI, VLED = 6.5V 9.2 10.6 12 R SL = 30.2kI, VLED = 6.5V R SL = 30.2kI, VLED = 3.5V 19.2 21.2 23.5 mA 20 mA 31.4 mA LED Current Programmable Range 21.2 10 LED Current with Grounded SL V FA V SL = 0V 20.6 26.4 LED Current Frequency fILED Sleep and ultra-low power modes 250 Hz LED Current Duty Cycle DILED Sleep and ultra-low power modes 25 % ����������������������������������������������������������������� Maxim Integrated Products 3 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter ELECTRICAL CHARACTERISTICS (continued) (VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND, C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected. All voltages are referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL VDD Current Amplitude IVDD Internal Current Duty Cycle DIVDD MIN TYP MAX UNITS Sleep mode, VLED = 6.5V Sleep and ultra-low power modes CONDITIONS 10 12 14.5 mA 75 % Internal Current Enable Time tMPS Ultra-low power mode 76 87 98 ms Internal Current Disable Time tMPDO Ultra-low power mode 205 235 265 ms THERMAL SHUTDOWN Thermal Shutdown Threshold TSD Thermal Shutdown Hysteresis TSD,HYS TJ rising 143 NC 16 NC LDO (MAX5987A) Input Voltage Range Inferred from line regulation Output Voltage LDO_FB = VDRV Max Output Voltage Setting With external divider to LDO_FB 4.5 14 3.3 V 5.5 LDO FB Regulation Voltage LDO FB Leakage Current V V 1.224 V ±1 FA Dropout VLDO_IN = 5V, VLDO_FB = VDRV, ILOAD = 80mA 500 mV Load Regulation ILOAD from 1mA to 80mA 0.4 mV/mA Line Regulation VLDO_IN from 4.5V to 14V 3 mV/V 100 mA LDO_FB Rising Threshold 2 V LDO_FB Hysteresis 1 V Overcurrent Protection Threshold IOVC DC-DC CONVERTER INPUT SUPPLY VDD Voltage Range WAD Detection Rising Threshold WAD Detection Falling Threshold WAD Detection Hysteresis VDD,RISING VCC = VDD = VWAD + 0.3V, rising 8.7 60 VDD,FALLING 7.6 60 VWAD,RISE VCC = VDD = VWAD + 0.3V, falling (Note 9) VWAD,FALL (Note 9) 5.8 8.8 V V V 0.6 V POWER MOSFETs High-Side pMOS On-Resistance RDSON-H ILX = 0.5A (sourcing) 0.65 1.01 I Low-Side nMOS On-Resistance RDSON-L ILX = 0.5A (sinking) 0.16 0.33 I LX Leakage Current ILX-LKG VDD = VCC = 28V, VLX = (VPGND + 1V) to (VCC - 1V) +5 FA -5 SOFT-START (SS) Soft-Start Time tSS-TH 7.45 ms ����������������������������������������������������������������� Maxim Integrated Products 4 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter ELECTRICAL CHARACTERISTICS (continued) (VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND, C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected. All voltages are referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.203 1.225 1.252 V 10 200 nA 5.6 V FEEDBACK (FB) FB Regulation Voltage VFB-RG FB Input Bias Current IFB VFB = 1.224V OUTPUT VOLTAGE Output Voltage Range Cycle by Cycle Overvoltage Protection VOUT VOUT-OV 3.0 Rising (Note 7) 101.5 105 107.8 Falling (Note 7) 98.2 101.1 104 % INTERNAL COMPENSATION NETWORK Compensation Network ZeroResistance RZERO 200 kI Compensation Network ZeroCapacitance CZERO 150 pF CURRENT LIMIT Peak Current-Limit Threshold IPEAK-LIMIT Runaway Current-Limit Threshold IRUNAWAY- Valley Current-Limit Threshold ZX Threshold 1.45 LIMIT IVALLEYLIMIT IZX A 1.9 A 1.5 A 25 mA TIMINGS Switching Frequency fSW 245 275 305 kHz Frequency Foldback fSW-FOLD 122.5 137.5 152.5 kHz Consecutive ZX Events for Entering Foldback 8 Events Consecutive ZX Events for Exiting Foldback 8 Events VOUT Undervoltage Trip Level to Cause HICCUP VOUT-HICF After soft-start completed (Note 7) HICCUP Timeout 55 60 65 120 Minimum On-Time tON-MIN 97 LX Dead Time % ms 126 ns 14 ns RESET (MAX5987A) VFB Threshold for RESET Assertion VFB-OKF VFB falling (Note 7) 90 % VFB Threshold for RESET Deassertion VFB-OKR VFB rising (Note 7) 95 % ����������������������������������������������������������������� Maxim Integrated Products 5 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter ELECTRICAL CHARACTERISTICS (continued) (VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND, C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected. All voltages are referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER VLDO_FB Threshold for RESET Assertion SYMBOL VLDO_FB-OKF CONDITIONS MIN TYP VLDO_FB falling, LDO_FB = VDRV (Note 8) RESET Deassertion Delay After FB Reaches 95% Regulation RESET Output Voltage Low ISINK = 1mA RESET Leakage Current MAX UNITS 90 % 3.72 ms 0.1 V ±10 FA 3: All devices are 100% production tested at TA = +25°C. Limits over temperature are guaranteed by design. 4: The input offset current is illustrated in Figure 2. 5: Effective differential input resistance is defined as the differential resistance between VDD and GND, see Figure 2. 6: A 20V glitch on input voltage, which takes VDD below VON shorter than or equal to tOFF_DLY does not cause the device to exit power-on mode. Note 7 Referred to feedback regulation voltage. Note 8: Referred to LDO feedback regulation voltage. Note 9: The WAD Detection Rising and Falling Thresholds control the isolation power MOS transistor. To turn the DC-DC on in WAD mode, the WAD must be detected and the VDD must be within the VDD voltage range. Note Note Note Note IIN RTEST dRi = 1V (VINi + 1 - VINi) = (IINi + 1 - IINi) (IINi + 1 - IINi) IOFFSET = IINi 1ms/10ms/100ms 100V MAX5986A IINi + 1 EVALUATION BOARD IINi VINi dRi dRi IOFFSET VINi Figure 1. MAX5986A/MAX5987A Internal TVS Test Setup 1V VINi + 1 VIN Figure 2. Effective Differential Resistance and Offset Current ����������������������������������������������������������������� Maxim Integrated Products 6 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Device with Integrated DC-DC Converter Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) QUIESCENT CURRENT vs. SUPPLY VOLTAGE (ULTRA-LOW POWER MODE) 0.30 0.25 0.20 0.15 0.10 DIFFERENTIAL RESISTANCE (kI) 3.75 0.35 28 MAX5986A toc02 0.40 QUIESCENT CURRENT (mA) 0.45 3.50 3.25 3.00 2.75 0.05 0 2.9 4.4 5.9 7.4 8.9 2.50 10.1 27 26 25 24 23 22 35 40 INPUT VOLTAGE (V) 45 50 55 60 1.4 2.9 4.4 SUPPLY VOLTAGE (V) 5.9 7.4 8.9 10.1 SUPPLY VOLTAGE (V) INPUT OFFSET CURRENT vs. INPUT VOLTAGE CLASSIFICATION CURRENT vs. INPUT VOLTAGE 1 0 -1 -2 MAX5986A toc05 2 10.60 10.58 CLASSIFICATION CURRENT (mA) 3 MAX5986A toc04 10.56 10.54 10.52 10.50 10.48 10.46 10.44 10.42 -3 10.40 2.9 4.4 5.9 7.4 8.9 10.1 14.1 12.6 SUPPLY VOLTAGE (V) 15.6 17.1 18.6 20.0 INPUT VOLTAGE (V) INRUSH CURRENT LIMIT vs. VCC VOLTAGE CLASSIFICATION SETTLING TIME 60 MAX5986A toc06 MAX5986A toc07 1.4 56 VDD 10V/div GND IDD 10mA/div 0mA INRUSH CURRENT (mA) 1.4 OFFSET CURRENT (µA) DETECTION CURRENT (mA) 4.00 MAX5986A toc01 0.50 SIGNATURE RESISTANCE vs. SUPPLY VOLTAGE MAX5986A toc03 DETECTION CURRENT vs. INPUT VOLTAGE 52 48 44 40 400µs/div 0 6 12 18 24 30 36 42 48 VCC (V) ����������������������������������������������������������������� Maxim Integrated Products 7 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Device with Integrated DC-DC Converter Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) 24 RSL = 30.2kI 18 15 RSL = 60.4kI 90 VWAD = 12V 85 80 75 VDD = 57V 70 65 10 12 VDD = 48V 95 EFFICIENCY (%) LED CURRENT (mA) 20 20 100 MAX5986A toc09 25 MAX5986A toc08 28 LED CURRENT (mA) EFFICIENCY vs. LOAD CURRENT (VOUT = 5V) LED CURRENT vs. LED VOLTAGE 60 55 8 10 20 30 40 50 60 70 AUX CONNECTED TO VOUT 50 5 80 0 RSL (kI) 1.75 3.50 5.25 7.00 0 100 200 300 400 500 600 700 800 LOAD CURRENT (mA) LED VOLTAGE (V) 5V LOAD TRANSIENT (0% TO 50%) 5V LOAD TRANSIENT (50% TO 100%) MAX5986A toc11 MAX5986A toc12 VOUT AC-COUPLED 50mV/div VOUT AC-COUPLED 50mV/div IOUT 500mA /div 0A IOUT 500mA/div 0A 100µs/div 100µs/div DC-DC CONVERTER STARTUP IOUT = 0A DC-DC CONVERTER STARTUP ROUT = 6.67I MAX5986A toc13 2ms/div MAX5986A toc10 LED CURRENT vs. R SL MAX5986A toc14 VOUT 1V/div VOUT 1V/div VGND VGND 2ms/div ����������������������������������������������������������������� Maxim Integrated Products 8 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter GND GND ULP WAD RESET GND GND 12 11 10 9 12 11 10 9 VDD 13 VCC 14 MAX5986A PGND 15 *EP VDD 13 7 VDRV VCC 14 RREF 16 *EP + 1 2 3 4 1 2 3 LDO_IN FB LX 5 AUX PGND 15 WK GND LED 6 MAX5987A LX + SL AUX RREF 16 8 TQFN 8 LDO_FB 7 VDRV 6 GND 5 FB 4 LDO_OUT TOP VIEW WAD Pin Configurations TQFN *EXPOSED PAD, CONNECT TO GND *EXPOSED PAD, CONNECT TO GND Pin Description PIN NAME FUNCTION MAX5986A MAX5987A 1 1 AUX 2 2 LX 3 — LED LED Driver Output. In sleep mode, LED sources a periodic current (ILED) at 250Hz with 25% duty cycle. 4 — WK Wake Mode Enable Input. WK has an internal 50kI pullup resistor to the internal 5V bias rail. A falling edge on WK brings the device out of sleep mode and into the normal operating mode (wake mode). — 3 LDO_IN LDO Input Voltage. Connect LDO_IN to output when used, otherwise connect to GND. Connect a minimum 1FF bypass capacitor between LDO_IN and GND. — 4 LDO_OUT Auxiliary Voltage Input. Auxiliary input to the internal regulator VDRV. Connect AUX to output of buck converter if the output voltage greater than 4.75V to back bias the internal circuitry and increase efficiency. Connect to a clean ground when not used. Inductor Connection. Inductor connection for the internal DC-DC converter. LDO Output Voltage. Connect a minimum 1FF output capacitor between LDO_OUT and GND. ����������������������������������������������������������������� Maxim Integrated Products 9 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter Pin Description (continued) PIN NAME FUNCTION MAX5986A MAX5987A 5 5 FB 6, 10, 11 6, 9, 10 GND Ground. Reference Rail for the Device. It is also the “quiet” ground for all voltage reference (e.g. FB is referenced to this GND). 7 7 VDRV Internal 5V Regulator Voltage Output. The internal voltage regulator provides 5V to the MOSFET driver and other internal circuits. VDRV is referenced to GND. Do not use VDRV to drive external circuits. Connect a 1Ff bypass capacitor between VDRV and GND. 8 — SL Sleep Mode Enable Input. A falling edge on SL brings the device into sleep mode. An external resistor (RSL) connected between SL and GND sets the LED current (ILED). ULP Ultra-Low Power-Mode Enable Input. ULP has an internal 50kI pullup resistor to the internal 5V bias rail. A falling edge on SL while ULP is asserted low enables ultra-low power mode. When ultra-low power mode is enabled, the power consumption of the device is reduced even lower than sleep mode to comply with ultra-low power sleep power requirements while still supporting MPS. 9 — Feedback. Feedback input for the DC-DC buck converter. Connect FB to a resistive divider from the output to GND to adjust the output voltage. 12 12 WAD Wall Power Adapter Detector Input. Wall adapter detection is enabled when the voltage from WAD to GND is greater than 8.8V. When a wall power adapter is present, the isolation p-channel power MOSFET turns off. Connect WAD directly to GND when the wall power adapter or other auxiliary power source is not used. 13 13 VDD Positive Supply Input. Connect a 68nF (min) bypass capacitor between VDD and PGND. 14 14 VCC DC-DC Converter Power Input. VDD is connected to VCC by an isolation p-channel MOSFET. Connect a 10FF capacitor in parallel with a 1FF ceramic capacitor between VCC and PGND. 15 15 PGND Power Ground. Power ground of the DC-DC converter power stage. Connect PGND to GND with a star connection. Do not use PGND as reference for sensitive feedback circuit. 16 16 RREF Signature Resistor Connection. Connect a 24.9kI resistor (RSIG) to GND. — 8 LDO_FB LDO Regulator Feedback Input. Connect to VDRV to get the preset LDO output voltage of 3.3V, or connect to a resistive divider from the LDO_OUT to GND for an adjustable LDO output voltage. — 11 RESET Open-Drain RESET Output. The RESET output is driven low if either LDO_OUT or FB drops below 90% of its set value. RESET goes high 100Fs after both LDO_OUT and FB rise above 95% of their set values. Leave unconnected when not used. — — EP Exposed Pad. Connect the exposed pad to ground. ���������������������������������������������������������������� Maxim Integrated Products 10 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter Detailed Description PD Interface The MAX5986A/MAX5987A include complete interface functions for a PD to comply with the IEEE 802.3af standard as a Class 1 PD. The devices provide the detection and classification signatures using a single external signature resistor. An integrated MOSFET provides isolation from the buck converter when the PSE has not applied power. The MAX5986A/MAX5987A guarantee a leakage current offset of less than 10µA during the detection phase. The devices feature power-mode undervoltagelockout (UVLO) with wide hysteresis and long deglitch time to compensate for twisted-pair-cable resistive drop and to ensure glitch-free transitions between detection, classification, and power-on/-off modes. Operating Modes The MAX5986A/MAX5987A operate in three different modes depending on VDD. The three modes are detection mode, classification mode, and power mode. The device is in detection mode when VDD is between 1.4V and 10.1V, classification mode when VDD is between 12.6V and 20V, and power mode when the input voltage exceeds VON. Detection Mode (1.4V < VDD < 10.1V) In detection mode, the MAX5986A/MAX5987A provide a signature differential resistance to VDD. During detection, the power-sourcing equipment (PSE) applies two voltages to VDD, both between 1.4V and 10.1V with a minimum 1V increment. The PSE computes the differential resistance to ensure the presence of the 24.9kω signature resistor. Connect the 24.9kω signature resistor (RSIG) from RREF to GND for proper signature detection. The device applies VDD to RREF when in detection mode, and the VDD offset current due to the device is less than 10µA. The DC offset due to protection diodes does not significantly affect the signature resistance measurement. Classification Mode (12.6V < VDD < 20V) In classification mode, the MAX5986A/MAX5987A sink a Class 1 classification current. The PSE applies a classification voltage between 12.6V and 20V, and measures the classification current. The MAX5986A/MAX5987A use the external 24.9kω resistor (RSIG) to set the classifica- tion current at 10.5mA. The PSE uses this to determine the maximum power to deliver. The classification current includes current drawn by the supply current of the device so the total current drawn by the PD is within the IEEE 802.3af standard. The classification current is turned off when the device leaves classification mode. Power Mode (VDD > VON) In power mode, the MAX5986A/MAX5987A have the isolation MOSFET between VDD and VCC fully on. The MAX5987A has the buck regulator enabled and the LDO enabled. The MAX5986A can be in either wake mode, sleep mode, or ultra-low power mode. The buck regulator is enabled when the MAX5986A is in wake mode. The devices enter power mode when VDD rises above the undervoltage lockout threshold (VON). When VDD rises above VON, the device turns on the internal p-channel isolation MOSFET to connect VCC to VDD with inrush current limit internally set to 49mA (typ). The isolation MOSFET is fully turned on when VCC is near VDD and the inrush current is below the inrush limit. Once the isolation MOSFET is fully turned on, the device changes the current limit to 201mA (typ). The buck converter turns on 100ms after the isolation MOSFET turns on fully. Undervoltage Lockout The MAX5986A/MAX5987A operate with up to a 60V supply voltage with a turn-on UVLO threshold (VON) at 35.4V/38.7V (typ), and a turn-off UVLO threshold (VOFF) at 31.4V (typ). When the input voltage is above VON, the device enters power mode and the internal isolation MOSFET is turned on. When the input voltage is below VOFF for more than tOFF_DLY, the MOSFET and the buck converter are off. LED Driver (MAX5986A) The MAX5986A drives an LED, or multiple LEDs in series, with a maximum LED voltage of 6.5V. In sleep mode and ultra-low power mode, the LED current is pulse width modulated with a duty cycle of 25% and the amplitude is set by R SL. The LED driver current amplitude is programmable from 10mA to 20mA using R SL according to the formula: ILED = 646/R SL (mA) where R SL is in kω. ���������������������������������������������������������������� Maxim Integrated Products 11 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter Sleep and Ultra-Low Power Modes (MAX5986A) The MAX5986A features a sleep mode and an ultra-low power mode in which the internal p-channel isolation MOSFET is kept on and the buck regulator is off. In sleep mode, the LED driver output (LED) pulse width modulates the LED current with a 25% duty cycle. The peak LED current (ILED) is set by an external resistor R SL. To enable sleep mode, apply a falling edge to SL with ULP disconnected or high impedance. Sleep mode can only be entered from wake mode. Ultra-low power mode allows the MAX5986A to reduce power consumption lower than sleep mode, while maintaining the power signature of the IEEE standard. The ultra-low power-mode enable input ULP is internally held high with a 50kω pullup resistor to the internal 5V bias of the device. To enable ultra-low power mode, apply a falling edge to SL with ULP = LOW. Ultra-low power mode can only be entered from wake mode. To exit from sleep mode or ultra-low power mode and resume normal operation, apply a falling edge on the wake-mode enable input (WK). Thermal-Shutdown Protection If the MAX5986A/MAX5987A die temperature reaches 143°C, an overtemperature fault is generated and the device shuts down. The die temperature must cool down below +127°C to remove the overtemperature fault condition. After a thermal shutdown condition clears, the device is reset. WAD Description For applications where an auxiliary power source such as a wall power adapter is used to power the PD, the MAX5986A/MAX5987A feature wall power adapter detection. The wall power adapter is connected from WAD to PGND. The MAX5986A/MAX5987A detect the wall power adapter when the voltage from WAD to PGND is greater than 8.8V. When a wall power adapter is detected, the internal isolation MOSFET is turned off, classification current is disabled. Connect the auxiliar power source to WAD, connect a diode from WAD to VDD, and connect a diode from WAD to VCC. See the typical application circuit in Figure 2. The application circuit must ensure that the auxiliary power source can provide power to VDD and VCC by means of external diodes. The voltage on VDD must be within the VDD voltage range to allow the DC-DC to operate. To allow operation of the DC-DC converter, the VDD and VCC voltage must be greater than 8.7V, on the rising edge, while on the falling edge the VDD and VCC may fall down to 7.3V keeping the DC-DC converter on. Note: When operating solely with a wall power adapter, the WAD voltage must be able to meet the condition VDD > 8.7V, that likely results in WAD > 9.4V. Internal Linear Regulator and Back Bias An internal voltage regulator provides VDRV to internal circuitry. The VDRV output is filtered by a 1µF capacitor connected from VDRV to GND. The regulator is for internal use only and cannot be used to provide power to external circuits. VDRV can be powered by either VDD or VAUX, depending on VAUX. The internal regulator is used for both PD and buck converter operations. VOUT can be used to back bias the VDRV voltage regulator if VOUT is greater than 4.75V. Back biasing VDRV increases device efficiency by drawing current from VOUT instead of VDD. If VOUT is used as back bias, connect AUX directly to VOUT. In this configuration, the VDRV source switches from VDD to VAUX after the buck converter’s output has reached its regulation voltage. Cable Discharge Event Protection (CDE) A 70V voltage clamp is integrated to protect the internal circuits from a cable discharge event. DC-DC Buck Converter The DC-DC buck converter uses a PWM, peak currentmode, fixed-frequency control scheme providing an easy-to-implement architecture without sacrificing a fast transient response. The buck converter operates in a wide input voltage range from 8.7V to 60V and supports up to 3.84W of output power at 1.15A load. The devices provide a wide array of protection features including UVLO, overtemperature shutdown, short-circuit protection with hiccup runaway current limit, cycle-by-cycle peak current protection, and cycle-by-cycle output overvoltage protection, for enhanced performance and reliability. A frequency foldback scheme is implemented to reduce the switching frequency to half at light loads to increase the efficiency. ���������������������������������������������������������������� Maxim Integrated Products 12 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter Frequency Foldback Protection for High-Efficiency Light-Load Operation The MAX5986A/MAX5987A enter frequency foldback mode when eight consecutive inductor current zerocrossings occur. The switching frequency is 275kHz under loads large enough that the inductor current does not cross zero. In frequency foldback mode, the switching frequency is reduced to 137.5kHz to increase power conversion efficiency. The device returns to normal mode when the inductor current does not cross zero for eight consecutive switching periods. Frequency foldback mode is forced during startup until 50% of the soft-start is completed. Hiccup Mode The MAX5986A/MAX5987A include a hiccup protection feature. When hiccup protection is triggered, the devices turn off the high-side and turn on the low-side MOSFET until the inductor current reaches the valley current limit. The control logic waits 120ms until attempting a new softstart sequence. Hiccup mode is triggered if the current in the high-side MOSFET exceeds the runaway currentlimit threshold, both during soft-start and during normal operating mode. Hiccup mode can also be triggered in normal operating mode in the case of an output undervoltage event. This happens if the regulated feedback voltage drops below 60% (typ). RESET Output (MAX5987A) The MAX5987A features an open-drain RESET output that indicates if either the LDO or the switching regulator drop out of regulation. The RESET output goes low if either regulator drops below 92% of its regulated feedback value. RESET goes high impedance 100µs after both regulators are above 95% of their value. Applications Information Operation with Wall Adapter For applications where an auxiliary power source such as a wall power adapter is used to power the PD, the MAX5986A features wall power adapter detection. The device gives priority to the WAD supply over VDD supply, and smoothly switches the power supply to WAD when it is detected. The wall power adapter is connected from WAD to PGND. The MAX5986A detects the wall power adapter when the voltage from WAD to PGND is greater than 8.8V. When a wall power adapter is detected, the internal isolation MOSFET is turned off, classification current is disabled and the device draws power from the auxiliary power source through VCC. Connect the auxiliary power source to WAD, connect a diode from WAD to VCC. See the typical application circuit in Figure 2. Adjusting LDO Output Voltage (MAX5987A) An uncommitted LDO regulator is available to provide a supply voltage to external circuits. A preset voltage of 3.3V is set by connecting LDO_FB directly to VDRV. For different output voltages connect a resistor divider from LDO_OUT and LDO_FB to GND. The total feedback resistance should be in the range of 100kω. The maximum output current is 85mA and thermal considerations must be taken to prevent triggering thermal shutdown. The LDO regulator can be powered by VOUT, a different power supply, or grounded when not used. The LDO is enabled once the buck converter has reached the regulation voltage. The LDO is disabled when the buck converter is turned off or not regulating. Adjusting Buck Converter Output Voltage The buck converter output voltage is set by changing the feedback resistor-divider ratio. The output voltage can be set from 3.0V to 5.6V. The FB voltage is regulated to 1.225V. Keep the trace from the FB pin to the center of the resistive divider short, and keep the total feedback resistance around 100kω. Inductor Selection Choose an inductor with the following equation: where LIR is the ratio of the inductor ripple current to full load current at the minimum duty cycle. Choose LIR between 20% to 40% for best performance and stability. Use an inductor with the lowest possible DC resistance that fits in the allotted dimensions. Powdered iron ferrite core types are often the best choice for performance. With any core material, the core must be large enough not to saturate at the current limit of the MAX5986A. VCC Input Capacitor Selection The input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the IC. The total input capacitance must be equal or greater than the value given by the following equation to keep the input-ripple voltage within specification and minimize the high-frequency ripple current being fed back to the input source: ���������������������������������������������������������������� Maxim Integrated Products 13 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter where VIN-RIPPLE is the maximum allowed input ripple voltage across the input capacitors and is recommended to be less than 2% of the minimum input voltage. D is the duty cycle (VOUT/VIN) and TS is the switching period (1/ fS). The impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source, but are instead shunted through the input capacitor. The input capacitor must meet the ripple current requirement imposed by the switching currents. The RMS input ripple current is given by: where IRIPPLE is the input RMS ripple current. Output Capacitor Selection The key selection parameters for the output capacitor are capacitance, ESR, ESL, and voltage-rating requirements. These affect the overall stability, output ripple voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitor’s ESR, and the voltage drop due to the capacitor’s ESL. Estimate the output-voltage ripple due to the output capacitance, ESR, and ESL: VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) +VRIPPLE(ESL) where the output ripple due to output capacitance, ESR, and ESL is: or whichever is larger. The peak-to-peak inductor current (IP-P) Use these equations for initial output capacitor selection. Determine final values by testing a prototype or an evaluation circuit. A smaller ripple current results in less output-voltage ripple. Since the inductor ripple current is a factor of the inductor value, the output-voltage ripple decreases with larger inductance. Use ceramic capacitors for low ESR and low ESL at the switching frequency of the converter. The ripple voltage due to ESL is negligible when using ceramic capacitors. Load-transient response depends on the selected output capacitance. During a load transient, the output instantly changes by ESR x ILOAD. Before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. After a short time, the controller responds by regulating the output voltage back to its predetermined value. The controller response time depends on the closed-loop bandwidth. A higher bandwidth yields a faster response time, preventing the output from deviating further from its regulating value. ���������������������������������������������������������������� Maxim Integrated Products 14 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter PCB Layout Careful PCB layout is critical to achieve clean and stable operation. It is highly recommended to duplicate the MAX5986A EV kit layout for optimum performance. If deviation is necessary, follow these guidelines for good PCB layout: 1)Connect input and output capacitors to the power ground plane; connect all other capacitors to the signal ground plane. 2) Place capacitors on VDD, VCC, AUX, VDRV as close as possible to the IC and its corresponding pin using direct traces. Keep power ground plane (connected to PGND) and signal ground plane (connected to GND) separate. 4) Connect VDD, VCC, and PGND separately to a large copper area to help cool the IC to further improve efficiency and long-term reliability. 5) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close as possible to the IC. 6) Route high-speed switching nodes, such as LX, away from sensitive analog areas (FB). 7) Place enough vias in the pad for the EP of the MAX5986A/MAX5987A so that heat generated inside can be effectively dissipated by the PCB copper. The recommended spacing for the vias is 1mm to 1.2mm pitch. The thermal vias should be plated (1oz copper) and have a small barrel diameter (0.3mm to 0.33mm). 3) Keep the high-current paths as short and wide as possible. Keep the path of switching current short and minimize the loop area formed by LX, the output capacitors, and the input capacitors. ���������������������������������������������������������������� Maxim Integrated Products 15 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter Typical Application Circuits RJ-45 AND BRIDGE RECTIFIER C1 68nF 1µF C2 10µF VDD VCC WAD AUX C3 1µF VDRV L0 47µH LX WK TO µP OPEN-DRAIN OUTPUTS OR PULLDOWN SWITCHES R1 75kI MAX5986A ULP 5V OUTPUT C4 47µF FB SL R2 24.9kI RSL 60.4kI LED RREF RSIG 24.9kI GND PGND 0I Figure 3. MAX5986A 5V Output with Back Bias ���������������������������������������������������������������� Maxim Integrated Products 16 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter Typical Application Circuits (continued) RJ-45 AND BRIDGE RECTIFIER C1 68nF 1µF LDO_FB C2 10µF VDD VCC WAD AUX VDRV L0 47µH C3 1µF LX LDO_IN TO 5V OUTPUT C5 1µF R1 75kI MAX5987A LDO_OUT 5V OUTPUT C4 47µF FB C6 1µF R2 24.9kI LED RREF RSIG 24.9kI GND PGND 0I Figure 4. MAX5987A 5V Buck Regulator Output and 3.3V LDO Output ���������������������������������������������������������������� Maxim Integrated Products 17 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter Functional Diagram VCC VDD 5V TVS HOT-SWAP CONTROLLER DETECTION CLASSIFICATION GND 5V RREF WAD PD VOLTAGE MONITOR AUX 5V 5V 1.5V 5V REGULATOR VDRV 1 5V 0 CLK LX CONTROL DRIVER VREF LDO_IN VREF LDO_OUT LDO PGND FB LDO_FB (MAX5987A ONLY) OPEN DRAIN VDD RESET 5V MAX5986A MAX5987A 50kI 5V VREF BANDGAP 50kI WK LOGIC SL ULP LED (MAX5986A ONLY) ���������������������������������������������������������������� Maxim Integrated Products 18 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter Package Information Chip Information PROCESS: BiCMOS For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 16 TQFN-EP T1655-4 21-0140 90-0121 Ordering Information PIN-PACKAGE SLEEP/ULP MODE LDO UVLO (V) RESET MAX5986AETE+ 16 TQFN-EP* YES NO 35.7 NO MAX5987AETE+** 16 TQFN-EP* NO YES 38.7 YES PART +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. **Future product—contact factory for availability. ���������������������������������������������������������������� Maxim Integrated Products 19 MAX5986A/MAX5987A IEEE 802.3af-Compliant, High-Efficiency, Class 1, Powered Devices with Integrated DC-DC Converter Revision History REVISION NUMBER REVISION DATE 0 4/12 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2012 Maxim Integrated Products 20 Maxim is a registered trademark of Maxim Integrated Products, Inc.