MC33560 Power Management and Interface IC for Smartcard Readers and Couplers The MC33560 is an interface IC for smartcard reader/writer applications. It enables the management of any type of smart or memory card through a simple and flexible microcontroller interface. Moreover, several couplers can be coupled in parallel, thanks to the chip select input pin (pin #5). The MC33560 is particularly suited to low power and portable applications because of its power saving features and the minimum of external parts required. Battery life is extended by the wide operating range and the low quiescent current in stand by mode. A highly sophisticated protection system guarantees timely and controlled shutdown upon error conditions. • 100% Compatible with ISO 7816–3 Standard • Wide Battery Supply Voltage Range: 1.8V < VBAT < 6.6V • Programmable VCC Supply for 3V or 5V Card Operation • Power Management for Very Low Quiescent Current in Stand By Mode (30µA max) • Microprocessor Wake–up Signal Generated Upon Card Insertion • Self Contained DC/DC Converter to Generate VCC using a Minimum of Passive Components • Controlled Power Up/Down Sequence for High Signal Integrity on the Card I/O and Signal Lines • Programmable Card Clock Generator • Chip Select Capability for Parallel Coupler Operation • High ESD Protection on Card Pins (4kV, Human Body Model) • Fault Monitoring VBATlow, VCClow and ICClim • All Card Outputs Current Limited and Short Circuit Protected • Tested Operating Temperature Range: –25°C to +85°C Figure 1. Simplified Functional Block Diagram VBAT L1 ILIM PGND DC/DC CONVERTER http://onsemi.com SO–24L DW SUFFIX CASE 751E 24 1 TSSOP–24 DTB SUFFIX CASE 948H 24 1 PIN CONNECTIONS PGND 1 24 ILIM PWRON 2 23 VBAT INT 3 22 L1 RDYMOD 4 21 C4 CS 5 20 C8 RESET 6 19 CRDC8 18 CRDCON IO 7 INVOUT 8 17 CRDDET ASYCLKIN 9 16 CRDC4 SYNCLK 10 15 CRDCLK CRDIO 11 14 CRDRST CRDGND 12 13 CRDVCC (Top View) PWRON INT RDYMOD CS POWER MANAGER AND PROGRAMMING SYNCLK ASYCLKIN INVOUT CLOCK GENERATOR CARD DETECTOR DELAY ORDERING INFORMATION VBAT IO RESET C4 C8 Semiconductor Components Industries, LLC, 1999 October, 1999 – Rev. 0 CRDDET CRDCON CRDVCC CRDIO CRDRST CRDC4 CRDC8 CRDCLK CRDGND LEVEL TRANSLATOR 1 Device Package Shipping SO–24WB 30 Units/Rail MC33560DWR2 SO–24WB 1000 Tape & Reel MC33560DTB TSSOP–24 62 Units/Rail MC33560DW MC33560DTBR2 TSSOP–24 2500 Tape & Reel Publication Order Number: MC33560/D MC33560 MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit Battery Supply Voltage VBAT 7 V Battery Supply Current IBAT ± 200 mA Power Supply Voltage VCC 6 V Power Supply Current ICC ± 150 mA Digital Input Pins (2, 4, 5, 6, 7, 9, 10, 17, 18, 20, 21) VIN IIN – 0.5 to VBAT + 0.5 but < 7 ±5 V mA Digital Output Pins (3, 4, 8) VOUT IOUT – 0.5 to VBAT + 0.5 but < 7 ±10 V mA Card Interface Pins (11, 13, 14, 15, 16, 19) VCard ICard – 0.5 to VCC + 0.5 ± 25 V mA IL ± 200 ± 100 mA 2 kV 4 kV Coil Driver Pin (22), ILIM (pin 24) Power Ground (pin 1) ESD Capability: (Note 2) Standard Pins (2, 3, 4, 5, 6, 7, 8, 9, 10, 17, 18, 20, 21, 22, 23, 24) Card Interface Pins (11, 13, 14, 15, 16, 19) VESD SO–24WB Package: Power Dissipation @ TA = 85 °C Thermal Resistance Junction to Air PDs RθJAs 285 140 mW °C/W TSSOP–24 Package: Power Dissipation @ TA = 85 °C Thermal Resistance Junction to Air PDt RθJAt 220 180 mW °C/W TA – 40 to + 85 °C TJ – 40 to + 125 °C TJmax 150 °C Operating Ambient Temperature Range Operating Junction Temperature Range Max. Junction Temperature (Note 3) Storage Temperature Range Tstg – 65 to + 150 °C Note 1: Maximum electrical ratings are those values beyond which damage to the device may. TA = 25°C Note 2: Human body model, R = 1500W, C = 100pF Note 3: Maximum thermal rating beyond which damage to the device may occur This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, input and output voltages should be constrained to the ranges indicated in the recommended operating conditions. ELECTRICAL CHARACTERISTICS These specifications are written in the same style as common for standard integrated circuits. The convention considers current flowing into the pin (sink current) as positive and current flowing out of the pin (source current) as negative. (Conditions: VBAT = 4V, VCC = 5V nom, PWRON = VBAT , operating mode, –ICC = 10mA, –25°C ≤ TA ≤ 85°C, L1 =47µH, RLIM =0W, CRDVCC capacitor=10µF, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Supply Voltage Range normal operating range extended operating range (Note 4) VBAT 2.2 1.8 6.0 6.6 V MC33560 Stand By Quiescent Current PWRON = GND, CRDCON = GND, ASYCLKIN = GND, VBAT = 6V, all other logic inputs and outputs open IoBAT 30 ms DC Operating Current –ICC = 10mA ; VCC =5V,VBAT = 6V IBATop 12.5 mA BATTERY POWER SUPPLY SECTION VBAT undervoltage detection: Upper Threshold Lower Threshold Hysteresis V 1.6 1.4 0.2 Note 4: See figures 2 and 3. http://onsemi.com 2 MC33560 VCC = 5V NOMINAL POWER SUPPLY SECTION Characteristic Test Conditions Output Voltage 2.2V 1mA 3.0V 1mA Symbol v V v 6V v –IBAT CC v 25mA v VBAT v 6V v –ICC v 60mA (RDYMOD output) (see table 4) Peak Output Current VCC = 4V, internally limited (RDYMOD = L) Current limit time–out VCC = 4V VCC = 2V; 0°C to +85°C –40°C to 0°C Low Side Switch Saturation Voltage Rectifier on Saturation Voltage Converter Switching Frequency Shut Down Current (Card access deactivated) Min Typ Max 4.75 5.0 5.25 4.60 5.0 5.40 4.2 120 4.5 180 VCC Card VCC Undervoltage Detection: Upper Threshold Lower Threshold Switching Hysteresis Start–up Current VT5H VT5L VHYS5 –ICClim td –ICCst V VCC–0.14 Card VCC Undervoltage Detection: Upper Threshold Lower Threshold Switching Hysteresis Start–up Current Shut Down Current (Card access deactivated) mA 160 ms 80 50 mA IL = 50mA, pin 22 IL = 50mA, pin 22 to pin 13 Vsat22 VFsat22 100 160 400 520 TA = 25 °C PWRON = GND, VCC = 2V fsw ISD 120 2.2V 1mA 2.5V 1mA v V BAT v 6V v –ICC v 10mA v V v 6V v –IBAT CC v 50mA V mV 80 mV mV kHz 80 VCC = 3V NOMINAL POWER SUPPLY SECTION (VBAT = 2.5V, –ICC = 5mA) Test Conditions Symbol Characteristic Output Voltage Unit Guaranteed Limits mA Unit Guaranteed Limits Min Typ Max 2.75 3.0 3.25 V 2.60 3.0 3.40 V VCC (RDYMOD output) (see table 4) V VT3H VT3L VHYS3 –ICCst ISD VCC = 2V PWRON = GND, VCC = 2V VCC–0.1 2.4 80 mV 2.7 110 50 50 mA APPLICATION INTERFACE DC SECTION (VBAT = 5V) Test Conditions Characteristic Symbol Unit Guaranteed Limits Min Typ Max Input High Threshold Voltage (increasing) pins 2, 4, 5, 6, 10, 17 VIH 0.55*VBAT 0.65*VBAT V Input Low Threshold Voltage (decreasing) pins 2, 5, 6, 10 pin 17 pin 4 VIL pins 2, 4, 5, 6, 10, 17 0.45*VBAT 0.40*VBAT 0.5*VBAT 0.3*VBAT V Switching Hysteresis 0.3*VBAT 0.2*VBAT 0.3*VBAT 0.06*VBAT Threshold Voltage pin 9 pin18 0.5*VBAT 0.4*VBAT 0.6*VBAT 0.6*VBAT V Pull–down resistance VIN = VBAT –1V, pin 2, 6, 7, 10 VIN = 0.5V, pin 3, 4, 5 Pull–up resistance VHYST VTH Output High Voltage IOH = –2.5µA, pin 3, pin 4 for CS = H IOH = –50µA, pins 7, 20,21 IOH = –0.2mA, pin 8 pin 4 ( in output mode) Output Low Voltage IOL = 1.0 mA, pins 7, 20, 21 IOL = 0.2mA, pins 3, 4, 8 Input Leakage Current VIN = 2.5V, CS = H, pins 9, 17, 18, 20, 21 Rdown 120 240 500 Rup VOH 120 240 500 VBAT –1 kW kW V VOL 0.4 V +/–Ileak 2.0 mA http://onsemi.com 3 V MC33560 CARD INTERFACE DC SECTION (VBAT = 5V) Characteristic Test Conditions Symbol Min Output High Voltage IOH = –20µA, pin 11, 16, 19 IOL = 0.2mA, pins 14, 15 VOH Output Low Voltage IOL = 1mA, pins 11, 16, 19 IOL = 0.2mA, pins 14, 15 VOL I/O Pull–up resistance, operating mode, CS =L, PWRON =H VOL = 0.5V, pin 11, 16, 19 Card pins security voltage (Card access deactivated) PWRON = GND, lin=10mA, pin 11, 14, 15, 16, 19 Unit Guaranteed Limits Typ Max VCC –0.9 V 0.4 kW 18 Vsecurity V 2.0 V Max Unit Note 5: the transistors T1 on lines IO, C4 and C8 (see figure 24) have a max Rdson of 250W. DIGITAL DYNAMIC SECTION (VBAT = 5V, normal operating mode, Note 6) Guaranteed Limits Characteristic Test Conditions Symbol Min Typ Input Clock Frequency pin 9, duty cycle = 50% fasyclk 20 MHz Card Clock Frequency pin 15 fcrdclk 20 MHz Card Clock Duty Cycle (Note 7) pin 15, 50% to 50% VCC , fio = 16MHz 55 % Card Clock Rise and Fall Time pin15, 10% ↔ 90% VCC I/O Data Transfer Frequency pin [7, 11], [21, 16], [20, 19] (Note 8) fio I/O Duty Cycle pin [7, 11], [21, 16], [20, 19] (Note 8) 50% to 50% VCC rio I/O Rise and Fall Time pin [7, 11], [21, 16], [20, 19] (Note 8) 10% ↔ 90% VCC I/O Transfer Time pin [7, 11], [21, 16], [20, 19] (Note 8) 50% to 50% VCC , L H, H L Card Signal Sequence Interval pin 11, 14, 15, 16, 19, VCC power up/down rclk 45 trclk, tfclk 10 1.0 45 ns MHz 55 % trio, tfio 150 ns ttr 100 ns 1.0 ms tdseq Card Detection Filter Time: Card insertion Card extraction tfltin tfltout Internal Reset Delay RES, VCC power up/down tdres Ready Delay Time pin 4 tdrdy PWRON low Pulse Width CS = L, pin 2 twon 0.2 50 50 150 150 20 2.0 2.0 ms ms ms ms ms Note 6: Pin loading=30pF, except INVOUT=15pF Note 7: As the clock buffer is optimized for low power consumption and hence not symmetrical, clock signal duty cycle is guaranteed for divide by 2 and divide by 4 ratio. Note 8: In either direction DIGITAL DYNAMIC SECTION (VBAT = 5V, programming mode, Note 6) Guaranteed Limits Characteristic Test Conditions Symbol Min Data Setup Time RDYMOD, PWRON, RESET, IO pin 2, 4, 6, 7 tsmod 1.0 Data Hold Time RDYMOD, PWRON, RESET, IO pin 2, 4, 6, 7 thmod 1.0 CS low Pulse Width pin 5 twcs 2.0 http://onsemi.com 4 Typ Max Unit ms ms ms MC33560 Figure 3. Maximum Battery and Card Supply Current vs. VBAT (VCC=3V) Figure 2. Maximum Battery and Card Supply Current vs. VBAT (VCC=5V) 200 200 IBATop MAX 180 180 140 120 ICC MAX I (mA) I (mA) 140 100 120 ICC MAX 100 80 80 Mode Sync SYNCLK=4MHz L1=47µH Rlim=0 60 40 20 0 1.5 2.5 3.5 4.5 5.5 20 0 1.5 7.5 6.5 Mode Sync SYNCLK=4MHz L1=47µH Rlim=0 60 40 2.5 4.5 3.5 5.5 7.5 VBAT (V) Figure 4. Battery Current vs. Input Clock Frequency (ICC=0, VBAT=4V) Figure 5. Battery Current vs. Input Clock Frequency (ICC =0, VBAT=2.5V) 14 14 VBAT=4V L1=47µH Rlim=0 ICC=0 Async VBAT=2.5V L1=47µH Rlim=0 ICC=0 12 10 IBATop (mA) 10 Sync 8 6 Async/2 4 8 Async 6 Sync 4 Async/4 Async/2 2 0 2 0 2.0 4.0 6.0 8.0 10 12 14 0 16 Async/4 2.0 0 6.0 8.0 10 12 14 Frequency (MHz) Figure 6. Maximum Battery Current vs. RLIM (VCC=5V, VBAT=4V) Figure 7. Maximum Battery Current vs. RLIM (VCC=3V, VBAT=2.5V) 16 250 Mode Sync SYNCLK=4MHz VBAT=4V L1=100µH 150 200 IBATop Max (mA) 200 L1=47µH 100 50 Mode Sync SYNCLK=4MHz VBAT=2.5V L1=100µH 150 L1=47µH 100 50 L1=22µH 0 4.0 Frequency (MHz) 250 IBATop Max (mA) 6.5 VBAT (V) 12 IBATop (mA) IBATop MAX 160 160 0 L1=22µH 1 2 3 4 0 5 0 Rlim (ohms) 1 2 Rlim (ohms) http://onsemi.com 5 3 4 5 MC33560 Figure 9. Maximum Card Supply Current vs. RLIM (VCC =3V, VBAT =2.5V) Figure 8. Maximum Card Supply Current vs. RLIM (VCC =5V, VBAT =4V) 120 120 80 L1=47µH 60 40 L1=47µH 60 20 L1=22µH 1 0 2 3 0 5 4 L1=22µH 1 0 3 4 Rlim (ohms) Figure 10. Low Side Switch Saturation Voltage (IL =50mA) vs. Temperature Figure 11. Rectifier On Saturation Voltage (IL =50mA) vs. Temperature Rectifier On Saturation Voltage (V) 0.06 0.05 0.04 0.03 0.02 0.01 –5 15 35 55 75 0.30 0.25 0.20 0.15 0.10 0.05 0.00 –25 95 –5 TA, Ambient Temperature (°C) 110 110 105 105 tfltout, Filter Time (µs) 115 100 95 90 85 95 90 85 75 75 55 75 95 80 35 55 100 80 15 35 Figure 13. Card Detection (extraction) filter time vs. Temperature 115 –5 15 TA, Ambient Temperature (°C) Figure 12. Card Detection (insertion) filter time vs. Temperature 70 –25 5 0.35 0.07 0.00 –25 tfltin, Filter Time (µs) 2 Rlim (ohms) 0.08 Low Side Switch Saturation Voltage (V) L1=100µH 80 40 20 0 Mode Sync SYNCLK=4MHz VBAT=2.5V 100 ICC Max (mA) ICC Max (mA) Mode Sync SYNCLK=4MHz VBAT=4V L1=100µH 100 75 70 –25 95 TA, Ambient Temperature (°C) –5 15 35 55 TA, Ambient Temperature (°C) http://onsemi.com 6 75 95 MC33560 Figure 14. Pull Down Resistance vs. Temperature Pull Down Resistance (k W) 350 330 310 290 270 250 230 210 190 170 150 –25 –5 15 35 55 75 95 TA, Ambient Temperature (°C) Figure 15. Transition from 5V to 3V Card Supply Figure 16. Transition from 3V to 5V Card Supply Figure 17. Overcurrent Shutoff (td =160ms) Figure 18. Undervoltage Shutoff (VT5L=4.6 V) http://onsemi.com 7 MC33560 Figure 19. Functional Block Diagram VBAT VBAT VBATOK VBAT 240 k CS CS CRDCON PWRON PWRON CRDDET 240 k VBAT t 240 k INT FAULT LOGIC S Q VBAT CARD R CS DELAY 50 mS CRDVCC 240 k RDYMOD POWER MANAGEMENT LOGIC AND PROGRAMMING VBATOK CARD PINS SEQUENCER FAULT VBAT SEQ1 SEQ2 SEQ3 CRDIO CRDVCC VBAT BIDIRECTIONAL I/O CARDENABLE VBATOK CRDC4 CRDVCC VBAT SEQ3 C8 CRDVCC CRDVCC BIDIRECTIONAL I/O CARDENABLE VBATOK SEQ3 C4 ILIM L1 CRDVCC ON/OFF 3V/5V SEQ4 SEQ1 240 k CARDENABLE DC/DC CONVERTER VBAT IO PROGRAM BIDIRECTIONAL I/O CARDENABLE VBATOK CRDC8 VBAT CRDVCC DATA LATCH RESET 240 k CARDENABLE LEVEL SHIFT SEQ4 SYNCLK CLOCK GENERATOR AND PROGRAMMING 240 k ASYCLKIN CRDRST VBAT CRDVCC LEVEL SHIFT SEQ2 PROGRAM INVOUT http://onsemi.com 8 CRDCLK MC33560 Table 1: PIN FUNCTION DESCRIPTION Pin Symbol Type Name/Function CONTROLLER INTERFACE 2 PWRON INPUT pull down This pin is used to start operation of the internal DC/DC converter. In programming mode, this pin is used to set the ”Output Voltage” switch. (see table 2). 3 INT OUTPUT pull up This open collector pin indicates a change in the card presence circuit status. When a card is inserted or extracted, the pin goes to logic level ”0”. The signal is reset to logic level ”1” upon the rising edge of CS or upon the rising edge of PWRON. In the case of a multislot application, two or more INT outputs are connected together and the microcontroller has to poll all the MC33560s to identify which slot was detected. 4 RDYMOD I/O & pull up This bidirectional pin has tri–state output and schmitt trigger input. * When RDYMOD is forced to 0, the MC33560 can be set to programming mode by a negative transition on CS. * When RDYMOD is connected to a high impedance, the MC33560 is in normal operating mode, and RDYMOD is in output mode (see tables 2 and 4): – With CS=L and PWRON=H, RDYMOD indicates the status of the DC/DC converter. – With CS=L and PWRON=L, RDYMOD indicates the status of the card detector. 5 CS INPUT pull up This is the MC33560 chip select signal. Pins 2, 6, 7, 10, 20, 21 are disabled when CS=H. When RDYMOD=L, the MC33560 enters programming mode upon the falling edge of CS (see figure 20) 6 RESET INPUT pull down The signal present at this input pin is translated to pin 14 (the card reset signal) when CS=L. The signal on this pin is latched when CS=H. This pin is also used in programming mode (see table 2). 7 IO I/O This pin connects to the Serial I/O port of a microcontroller. A bi–directional level translator adapts the serial I/O signal between the smartcard and the microcontroller. The level translator is enabled when CS=L. The signal on thispin is latched when CS=H. This pin is also used in programming mode. (see table 2) 8 INVOUT CLK OUTPUT The ASYCLKIN (pin 9) signal is buffered and inverted to generate the output signal INVOUT. This output is used for multislot applications, where the ASYCLKIN inputs and INVOUT outputs are daisy–chained (see the multislot application example in figure 33). 9 ASYCLKIN CLK INPUT high impedance This pin can be connected to the microcontroller master clock or any clock signal for asynchronous cards. The signal is fed to the internal clock selector circuit, and is translated to CRDCLK at the same frequency, or divided by 2 or 4, depending on programming (see table 3). 10 SYNCLK CLK INPUT pull down This function is used for communication with synchronous cards, and the pin is generally connected to the controller serial interface clock signal. The signal is fed to the internal clock selector circuit, and is translated to CRDCLK upon appropriate programming of the MC33560 (see table 3). When selected at programming, the signal on this pin is latched when CS=H. 20 C8 I/O General purpose input/output. It has the same behavior as I/O, except for programming. It can be connected to abidirectional port of the microcontroller. The level translator is en abled when CS=L, and the signal is latched whenCS=H. (compare with pin 19) 21 C4 I/O General purpose input/output. It has the same behaviour as I/O, except for programming. It can be connected to a bidirectional port of the microcontroller. The level translator is enabled when CS=L, and the signal is latched when CS=H. (compare with pin 16) CARD INTERFACE 11 CRDIO I/O This pin connects to the serial I/O pin of the card connector. A bidirectional level translator adapts the serial I/O signal between the card and the microcontroller (compare with pin 7) 14 CRDRST OUTPUT This pin connects to the RESET pin of the card connector. A level translator adapts the RESET signal driven by the microcontroller (compare with pin 6). 15 CRDCLK OUTPUT This pin connects to the CLK pin of the card connector. The CRDCLK signal is the output of the clock selector circuit.The clock selection is programmed using pins 2, 6 and 7 with RDYMOD forced to ”0”. 16 CRDC4 I/O General purpose input/output. It has the same behavior as CRDIO. It can be connected to the C4 pin of the card connector. 17 CRDDET INPUT high impedance This pin connects to the card detection switch of the card connector. Card detection phase is determined with pin 18. This pin needs an external pull–up or pull–down resistor to operate properly. http://onsemi.com 9 MC33560 Pin Symbol Type Name/Function CARD INTERFACE 18 CRDCON INPUT high impedance This pin connects to PGND or VBAT, or possibly to an output port of the microcontroller. With this pin set to a logic “0”, the presence of a card is signalled with a logic ”1” on pin 17. With this pin set to a logic ”1”, the presence of a card is signalled with a logic ”0” on pin 17. 19 CRDC8 I/O General purpose input/output. It has the same behavior as CRDIO. It can be connected to the C8 pin of the card connector ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CURRENT LIMIT AND THERMAL PROTECTION 1 PGND POWER This pin is the return path for the current flowing into pin 22 (L1). It must be connected to CRDGND using appropriate grounding techniques. 12 CRDGND POWER This pin is the signal ground. It must be connected to the ground pin of the card connector. It is the reference level for all analog and digital signals. 13 CRDVCC POWER This pin connects to the VCC pin of the card connector. It is the reference level for a logic ”1” of pins 11, 14, 15, 16 and 19. 22 L1 POWER This pin connects to an external inductance for the DC/DC converter. Please refer to the description of the DC/DC converter functional block. 23 VBAT POWER This pin is connected to the supply voltage. Logic level ”1” of pins 2 to 10, 17, 18, 20 and 21 is referenced to VBAT. Operation of the MC33560 is inhibited when VBAT is lower than the minimum value. 24 ILIM POWER This pin can be connected to the PGND pin, or to a resistor connected to PGND, or left open, depending on the peak coil current needed to supply the card. PROGRAMMING AND STATUS FUNCTIONS The MC33560 features a programming interface and a status interface. Figure 20 shows how to enter and exit programming mode; table 2 shows which pins are used to access the various functions. Figure 20. MC33560 Programming Sequence RDYMOD (in) CS PWRON PROGRAM DATA VALUE RESET PROGRAM DATA VALUE IO PROGRAM DATA VALUE ENTER PROGRAMMING MODE LATCH EXIT PROGRAM PROGRAMMING VALUE MODE Table 2: PIN USE FOR PROGRAMMING AND STATUS FUNCTIONS Programs CRDVCC TO 3V/5V Select VCC ON/OFF Select Clock Input Program ASYCLKIN Divide Ratio Poll Card Status Poll CRDVCC Status RDYMOD (in/out) Force to 0 READ Force to 0 Force to 0 READ READ CS (in) rising edge 0 rising edge rising edge 0 0 PWRON 0/1 0/1 Programs CRDVCC Programs CRDVCC 0 or Hi–z 1 RESET (in) Programs CLK input/divide ratio NOT USED 0/1 0/1 NOT USED NOT USED IO (in) Programs CLK input/divide ratio NOT USED 0/1 0/1 NOT USED NOT USED http://onsemi.com 10 MC33560 CARD VCC AND CARD CLOCK PROGRAMMING The CRDVCC and ASYCLK programming options allow the system clock frequency to be matched to the card clock frequency and to select 3V or 5V CRDVCC supply. Table 3 shows the values of PWRON, RESET and IO for the possible options. The default power reset condition is state 4 (synchronous clock and CRDVCC =5V). All states are latched for each output variable in programming mode at the positive transition of CS (see figure 20). Table 3 : CARD VCC AND CARD CLOCK TRUTH TABLE STATE# PWRON RESET IO CRDVCC CRDCLK 0 L L L 3V SYNCLK 1 L L H 3V ASYCLKIN/4 2 L H H 3V ASYCLKIN/2 3 L H L 3V ASYCLKIN 4 H L L 5V SYNCLK 5 H L H 5V ASYCLKIN/4 6 H H H 5V ASYCLKIN/2 7 H H L 5V ASYCLKIN Note : Card clock integrity is maintained during all frequency commutations (no spikes). State 4 is the default state at power on. DC/DC CONVERTER AND CARD DETECTOR STATUS The MC33560 status can be polled when CS=L. Please consult table 2 for a description of input and output signals.The significance of the status message is described in table 4. Table 4 : RDYMOD STATUS MESSAGES PWRON (input) RDYMOD (output) Message LOW LOW No card LOW HIGH Card present HIGH LOW DC/DC converter overload HIGH HIGH DC/DC converter OK http://onsemi.com 11 MC33560 DETAILED OPERATING DESCRIPTION INTRODUCTION generator. The power management unit enables the DC/DC converter for card power supply, supervises the power up/down sequence of the card’s I/O and signal lines, and keeps the power consumption very low in stand by mode. All card interface pins have adequate ESD protection, and fault monitoring (VBATlow, VCClow, ICClim) guarantees hazard–free card reader operation. Several MC33560s can be operated in parallel, using the same control and data bus, through the use of the chip select signal CS. The MC33560 smartcard interface IC has been designed to provide all necessary functions for safe data transfers between a microcontroller and a smartcard or memory card. A card detector scans for the presence of a card and generates a debounced wake–up signal to the microcontroller. Communication and control signal levels are translated between the digital interface and the card interface by the voltage level translator, and the card clock is matched to the system clock frequency by the programmable card clock Figure 21. MC33560 Operating Modes CS: FALLING EDGE STAND BY MODE CS = H PWRON = L ERROR CONDITION ACTIVE MODE CS = L PWRON = L CS: RISING EDGE RDYMOD: 0 AND CS: FALLING EDGE CS: 1 AND RDYMOD: RISING EDGE ISO STOP SEQUENCE CS: 0 AND PWRON: RISING EDGE PWRON: FALLING EDGE OR ERROR CONDITION ISO START SEQUENCE PROGRAMMING MODE CS = L RDYMOD = L TRANSACTION MODE CS = L PWRON = H OPERATING MODES IDLE MODE CS = H PWRON = H CS: 1 AND RDYMOD: RISING EDGE RDYMOD: 0 AND CS: FALLING EDGE PROGRAMMING MODE CS = L RDYMOD = L The microcontroller polls the MC33560 by asserting CS=L and reading the RDYMOD pin. If a card is present, the microcontroller starts the DC/DC converter by asserting PWRON=H. This starts the automatic power on sequence: when CRDVcc reaches the undervoltage level (VT5H or VT3H, depending on programming), the card sequencer validates CRDIO, CRDRST, CRDCLK, CRDC4, CRDC8 pins according to the ISO7816–3 sequence (see figure 26). The MC33560 is now in transaction mode, and the system is ready for data exchange via the three I/O lines and the RESET line. The MC33560 has five operating modes: ⋅ stand by ⋅ programming ⋅ active ⋅ transaction ⋅ idle The transitions between these different states are shown in figure 21 above. STAND BY MODE Stand by mode allows the MC33560 to detect card insertion and monitor the power supply while keeping the power consumption at a minimum. It is obtained with CS=H and PWRON=L. When the MC33560 detects a card, INT is asserted low to wake up the Microcontroller. TRANSACTION MODE In transaction mode, the MC33560 maintains power and the selected clock signal applied to the card, and the levels of the IO, RESET, C4 and C8 signals between the microcontroller and the card are translated depending on the supply voltages VBAT and VCC. The DC/DC converter status can be monitored on the RDYMOD pin. PROGRAMMING MODE The programming mode allows the user to configure the card Vcc and the card clock signal for his specific application. The card supply, CRDVcc, can be programmed to 3V or 5V, and the card clock signal can be defined to be either synchronous, or asynchronous divided by 1, 2 or 4. Programming mode is obtained with RDYMOD=L followed by a negative transition on CS. The programming options are shown in table 3. Programmed values are latched on a positive transition of CS with RDYMOD=L. IDLE MODE Idle mode is used when maintaining a card powered up without communicating with it. When an asynchronous clock is used, the selected clock signal is applied to the card POWER DOWN OPERATION Power–down can be initiated by the controlling microprocessor, by stopping the DC/DC converter with PWRON=L while CS=L, or by the MC33560 itself when an error condition has been detected (CRDVcc undervoltage, overcurrent longer than 160ms typ., overtemperature, “hot” ACTIVE MODE In active mode, the MC33560 is selected, the RDYMOD pin becomes an output, and the MC33560 status can be polled. Power is not applied to the card. http://onsemi.com 12 MC33560 In stand by mode (PWRON=L) the power manager keeps only the ”card present” detector alive. All card interface pins are forced to ground potential. In the event of a power–up request from the microcontroller (PWRON L to H transition, CS=L) the power manager starts the DC/DC converter. As soon as the CRDVCC supply reaches the operating voltage range, the circuit activates the card signals in the following sequence: CRDVCC, CRDIO, CRDCLK, CRDC4/C8, CRDRST At the end of the transaction (PWRON reset to L, CS=L) or forced card extraction, the CRDVCC supply powers down and the card signal deactivation sequence takes place: CRDRST, CRDC4/C8, CRDCLK, CRDIO, CRDVCC When CS=L, the bi–directional signal lines (IO, C4 and C8) are put into high impedance state to avoid signal collision with the microcontroller in transmission mode. card extraction). The communication session is terminated in a given sequence defined in ISO7816–3. The MC33560 then goes into active mode, in which its status can be polled. Stand by mode is reached by deselecting the MC33560 (CS=H). FUNCTIONAL BLOCKS CARD DETECTOR This block monitors the card contact CRDDET (during insertion and extraction), filters the incoming waveform and generates an interrupt signal INT after each change. In order to identify which coupler activated the INT line (multicoupler application) the microcontroller scans both circuits via CS and reads the RDYMOD pin. The programming input CRDCON tells the level detector which type of mechanical contact is implemented (normally open or normally closed). Special care is taken to hold the current consumption very low on this part of the circuit which is continuously powered by the VBAT supply. The CRDDET pin has high impedance input, and an external resistor must be connected to pull–up or pull– down, depending on CRDCON. This resistor is chosen according to the maximum leakage current of the card connector and the PCB. The card detector has an internal 50µs debouncing delay. The micro controller has to insert an additional delay (in the ms range) to allow the card contacts to stabilize in the card connector before setting PWRON=H. When the card detector circuit detects a card extraction, it activates the power–down sequence and stops the converter, regardless of the PWRON signal. The 50µs delay of the debouncer is enough to ensure that all card signals have reached a safe value before communication with the card takes place. BATTERY UNDERVOLTAGE DETECTOR The task of this block is to monitor the supply voltage, and to allow operation of the DC/DC converter only with valid voltage (typically 1.5 V). The comparator has been designed to have stability better than 20mV in the temperature range. DC/DC CONVERTER Upon request from the power manager, the DC/DC converter generates the CRDVCC supply for the smartcard. The output voltage is programmable for 3V or 5V (see table 3) to guarantee full cross compatibility of the reader for 5V and 3V smartcards. The wide voltage supply range, 1.8V < VBAT < 6.6V, accommodates a broad range of coupler applications with different battery configurations (single cell or multiple cells, serial or parallel connections). CRDVCC is current–limited and The short–circuit–proof.To avoid excessive battery loading during a card short–circuit, a current integration function forces the power–down sequence (see figure 28). To retry the session, the microprocessor works through the power on sequence as defined in the power manager section. CARD STATUS The controlling microprocessor is informed of the MC33560 status by interrupt and by polling. When a card is extracted or inserted, the INT line is asserted low. The interrupt is cleared upon the rising edge of CS or upon the rising edge of PWRON (INT line set to high state). The microprocessor can poll the status at any time by reading the RDYMOD pin with proper PWRON setting (see tables 2 and 4 ). Since INT and RDYMOD have a high value pull–up resistor (240kW typ.), their rise time can be as long as 10µs if parasitic capacitance is high and no other pull–up circuitry is connected. DC/DC Converter operating principles The DC/DC converter architecture used in the MC33560 allows step–up and step–down voltage conversion to be done. The unique regulation architecture permits an automatic transition from step–up to step–down, and from zero to full load, without affecting the output characteristics. DC/DC Converter Description: The converter architecture is very similar to the boost architecture, with an active rectifier in place of the diode. The switching transistor is connected to ground through a resistor network in order to adjust the maximum peak current (see figure 22). A transistor connected to the converter output (CRDVCC) forces this pin to a low voltage when the converter is not operating. This prevents erratic voltage supply to the smartcard when not in use. POWER MANAGER The task of the power manager is to activate only those circuit functions which are needed for a determined operating mode in order to minimize power consumption (see figure 19). http://onsemi.com 13 MC33560 Fault Detection: The DC/DC converter has several features that help to avoid electrical overstress of the MC33560 and of the smartcard, and help to ensure that data transmission with the smartcard occurs only when its supply voltage is within predetermined limits. These functions are: ⋅ overtemperature detection, ⋅ current limitation, and ⋅ card supply undervoltage detection. The level at which current will be limited is defined by the maximum card supply current programmed with the external components L1 and RLIM. The undervoltage detection levels for 3V and 5V card supply are preset internally to the MC33560. The MC33560 has a built in oscillator; the DC/DC converter requires only one inductor and the output filtering capacitor to operate. Step–Up Operation: When the card supply voltage is lower than the battery voltage, the converter operates like a boost converter; the active rectifier behavior is similar to that of a diode. Step–Down Operation: When the card supply voltage is higher than the battery voltage, the rectifier control circuit puts the power rectifying transistor in conduction when the L1 voltage reaches VBAT+VFSAT22. The voltage across the rectifying transistor is higher than in step–up operation. The efficiency is lower, and similar to a linear regulator. Figure 22. DC/DC Converter Functional Block VBAT Rectifier Switch CRDVCC L1 Active pull–down switch PWN FEED BACK CLOCK OFF RECTIFIER CONTROL Low Side Switch STOP ON /OFF ILIMCOMP 120 mV 2W PGND 0.5 W Internal resistors ILIM RLIM (external) – LOGIC AND COUNTER OVER TEMP DETECTION ON /OFF CRDGND – + ON /OFF DIGITAL FILTER ON /OFF + 3V/5V UNDER VOLTAGE DETECTOR VBATOK CONVERTER FAULT + CRDGND VREF ERROR AMP. – The overcurrent and undervoltage protection features are complementary, and will shut the circuit off either if the overcurrent is high enough to bring the CRDVCC output below the preset threshold, either after 160ms (typ.) In addition, the DC/DC converter will be allowed to start only if the battery supply voltage is high enough to allow normal operation (1.8V). The undervoltage comparator has a hysteresis and a delay of typically 20ms to ensure stable operation. The current detector is a comparator associated with two resistors: one 2W attached to PGND and usually connected to analog ground, and a 0.5W attached to ILIM, usually connected to ground through an external resistor to adjust the maximum peak current. The voltage developed across this resistor network is then compared to a 120mV (typical) reference voltage, and the comparator output performs a cycle–by–cycle peak current limitation by switching off the low side transistor when the voltage exceeds 120 mV. The internal ILIMCOMP signal is monitored to stop the converter if current limitation is continuously detected during 160ms (typical). This allows normal operation with high filtering capacitance and low peak current, even at converter start–up. As a result, a short circuit to ground on the card connector or a continuous overcurrent is reported by RDYMOD 160ms (typical) after power up. Unexpected card extraction: The MC33560 detects card extraction and runs a power down sequence if card power is still on when extraction occurs. An active pull–down switch clamps CRDVCC to GND within 150µs (max) after extraction is detected. The external capacitors will then be discharged. With typical capacitor values of 10µF and 47nF as indicated in the application schematic, the time needed to discharge CRDVCC to a voltage below 0.4V can be estimated to less than 750µs. The total time aftercard extraction detection until CRDVCC reaches 0.4V is then estimated to 900µs (max). All smartcard connector contacts will be deactivated before CRDVCC deactivation. This ensures that no electrical damage will be caused to the smartcard under abnormal extraction conditions. http://onsemi.com 14 MC33560 3V/5V programming: It is possible to set the card supply voltage to 3V or 5V at any time, before DC/DC converter start, or during converter operation. When switching from 3V to 5V, a 160ms (typical) delay blanks the undervoltage fault detection to allow filter capacitor charging. PWM: The free–running integrated oscillator has two working modes: ⋅ variable on–state and fixed frequency (typically 120KHz) for average to heavy loads. ⋅ variable on–state and variable frequency for light loads. The frequency can be as low as a few kHz if no load is connected to CRDVCC. The charging current of the timing capacitor is related to the VBAT supply voltage, to allow better line regulation, and to increase stability. Filtering Capacitor: A high value allows efficient filtering of card current spikes. Low values allow low start–up charging current. Care must be taken not to combine low capacitor value with high current limiting, as this can generate high ripple. Usual values range from 4.7µF to 47µF, depending on current limiting. Selecting the external components L1 and RLIM: The choice of inductor L1 and resistor R4 is made by using figure 8 (5V card) and/or figure 9 (3V card) on page 8: First, determine the maximum current that the application requires to supply to the card (ICCmax, on the y–axis) Then, select one curve that crosses the selected ICCmax level. The curve is associated with an inductance value (22µH, 47µH, or 100µH). Finally, use the intersection of the curve and the ICCmax level to find the Rlim value on the x–axis. Good starting values are : L1 =47µH; Rlim =0.5W Note also that, for a high inductance value (100µH), the filtering capacitor is generally charged before inductance current reaches current limitation, while for alow inductance value, the current limitation is activated after a few converter cycles. Battery requirements: Having determined the L1 and Rlim values, the maximum current drawn from the battery supply is shown by the curves in figures 6 and 7. When the application is powered by a single 3V battery, special care has to be taken to extend its lifetime. When lithium batteries approach the end–of–life, their internal resistance increases, while voltage decreases. This phenomenon can prevent the start–up of the DC/DC converter if the current limiting is set too high, because of the filtering capacitor charging current. used to configure the two output variables CRDVCC and CRDCLK as described in table 3. This circuit setup is latched during the positive transition of CS. Furthermore, in asynchronous mode the system clock frequency ASYCLKIN can be divided by a factor of 1, 2 or 4. The circuit controls the frequency commutation to guarantee that the card clock signal remains free from spikes and glitches. In addition, this circuit ensures that CRDCLK signal pulses will not be shorter than the shortest and/or longer than the longest of the clock signals present before and after programming changes . The INVOUT output is provided to drive other circuits without additional load to the microprocessor quartz oscillator. It can also be used to build a local RC oscillator. This driver has been optimized for low consumption; it has no hysteresis, and input levels are not symmetrical. If the ASYCLKIN pin is connected to a sine wave, the duty cycle will not always be 50% at INVOUT. Clock generator operating principles Synchronous Clock: This clock is used mainly for memory cards. It can also be used for asynchronous (microprocessor) cards, allowing the use of two different clock sources. The status of SYNCLK is latched at CRDCLK when CS goes high, so that data (the IO pin) and clock are always consistent at the card connector, whatever the CS status is. When using the synchronous clock, the clock output becomes active only when the MC33560 is selected with CS. Asynchronous Clock: This clock is used mainly for microprocessor cards. When applied, the clock output remains active even when the MC33560 is not selected with CS, in order to keep the microprocessor running and avoid an unwanted reset. The ASYCLKIN signal is buffered at the INVOUT pin, so that several MC33560 systems can use the same clock with one load only. Depending on programming, the frequency is fed directly, or divided by 2 or by 4 to the CRDCLK pin. If the duty cycle of the applied clock signal is not exactly symmetrical, it is recommended that the clock signal be divided by two or four to guarantee 50% duty cycle. Clock Signal Synchronization and Consistency (see figure 29). The clock divider includes synchronization logic that controls the switch from synchronous clock to asynchronous (and vice–versa), from any division ratio to any other ratio, during CS changes and at power up. The synchronization logic guarantees that each clock cycle on the CRDCLK pin is finished before changing clock selection (and has always the adequate duration), regardless of the moment the programming is changed. At power–up, when ASYCLKIN is selected, the clock signal at the CRDCLK pin has an entire length, according to the selected divide ratio, whatever the ASYCLKIN signal is versus the internal sequencer timing. CLOCK GENERATOR The primary purpose of the clock generator module is to match the smartcard operating frequency to the system frequency. The source frequency can be provided to ASYCLKIN by the microcontroller itself or from an external oscillator circuit. In programming mode (RDYMOD=L and CS asserted low) the three input variables PWRON, IO and RESET are http://onsemi.com 15 MC33560 CARDENABLE ASYCLKIN B2 INVOUT B2 SELECTOR LATCH SYNCLK SYNCHRONISATION LOGIC Figure 23. Clock Generator Functional Block CRDVCC SYNCHRO LATCH CRDCLK SEQ3 RESET SELECTOR LATCH IO PROGRAM BIDIRECTIONAL LEVEL TRANSLATOR This module (used on IO/CRDIO, C4/CRDC4, C8/CRDC8, see figure 24) adapts the signal voltage levels of the I/O and control lines between the micro controller (supplied by VBAT) and the smartcard (supplied by CRDVCC) When CS is low, with CRDVCC on, and start sequencing completed, this module is transparent for the data, and acts as if the card was directly connected to the reader microcontroller. The core of the level shifter circuit defined for the bidirectional CRDIO, CRDC4 and CRDC8 lines consists of a NMOS switch which can be driven to the logic low state from either side (microcontroller or card). If both sides work in transmission mode with opposite phase, then signal collision on the line is not avoidable. In this case, the peak current is limited to a safe value for the integrated circuit and the smartcard. During high–to–low transitions, the NMOS transistor impedance (T1=250W max.) is low enough to charge parasitic capacitance, and have a high enough dv/dt. On low to high transition, the NMOS transistor is not active above a certain voltage, and an acceleration circuit is activated to ensure a high dv/dt. When the chip is disabled (CS=H) with the voltage supply CRDVCC still active, the IO, C4 and C8 lines keep their last logic state. When the converter is off, a transistor forces the CRDIO, CRDC4 and CRDC8 lines to a low state, thus preventing any unwanted voltage level to be applied to the data lines when the card is not in use. SECURITY FEATURES The MC33560 has a number of unique security functions to guarantee that no electrical damage will be caused to the smartcard: ⋅ Battery supply minimum voltage threshold ⋅ Card supply undervoltage and overcurrent detection with automatic shutdown ⋅ Card pin overvoltage clamp to CRDVCC ⋅ Card presence detector for ”clean” and fast shut–down ⋅ Consistent card signal sequencing at start–up and power–down, according to ISO7816, even on error conditions ⋅ Consistent clock signal, even when division ratio or synchronization clock signal are changed ”on the fly” during a card session (see figure 29) ⋅ Active pull–down on all card pins, including CRDVCC, when not in normal operating mode. A current limiting function and an overtemperature detector are limiting power dissipation. ESD PROTECTION Due to the nature of smartcards, the card interface pins must absorb high ESD (Electro Static Discharge) energy during card insertion. In addition, the control circuits attached to these pins must safely withstand short circuits and voltage transients during forced card extraction. Therefore, the MC33560 features enhanced ESD protection, current limitation and short circuit protection on all smartcard interface pins, including C4 and C8. PARALLEL OPERATION For applications where two or more MC33560 are used, the digital control and data bus lines are common to all MC33560. Only the chip select signal, CS, requires a separate line for each interface. While deselected, all communication pins except CRDCLK will keep their logical state on the card side, and will go to high impedance mode on the microprocessor side. Figure 33 shows a typical application of a dual card reader. This arrangement was chosen only to illustrate the parallel operation of two card interfaces in the same module. The discrete capacitor components are necessary to provide low Figure 24. Bidirectional Translator Functional Block VBAT CRDVCC 18 K IO (C4) (C8) CRDIO (CRDC4) (CRDC8) T1 CONTROL LOGIC SEQ1 (SEQ3) T2 CRDGND CARDENABLE http://onsemi.com 16 MC33560 impedance on the supply lines VBAT and CRDVCC and to suppress the high frequency noise due to the DC/DC converter. The load resistors are external in order to adapt the sense current of the ”cardpresent” switches. In order to maintain stand by current at a minimum value, all pins with pull–up resistance (CS, INT, RDYMOD) have to be kept in the high state or left open, and pins with pull–down resistance (RESET, SYNCLK, PWRON) have to be kept in the low state or left open. ASYCLKIN should not be connected to an active clock signal during stand by to avoid dynamic currents. This is valid also for SYNCLK, except that it can be left open. MINIMUM POWER CONSUMPTION CONSIDERATIONS All analog blocks except the VBAT comparator and the card presence detector are disabled in stand by mode (CS=H: DC/DC converter stopped). Figure 25. Example of single sided PCB layout for MC33560 C8 C4 CRDC8 CRDDET CRDC4 CRDCLK CRDRST L1 CRDVCC VBAT ILIM PGND C10 R4 C6 C7 CRDGND CRDIO PWRON SYNCLK INT ASYCLKIN RDYMOD INVOUT CS IO RESET http://onsemi.com 17 MC33560 Figure 26. Card Signal Sequence During VCC Power Up/Down POWER UP NORMAL OPERATION POWER DOWN VTxH CRDVCC CS RDYMOD (out) twon PWRON IO CLK C4. C8 RESET CRDIO CRDCLK CRDC4, CRDC8 ttr CRDRST SEQ4 to SEQ1 SEQ1 to SEQ4 Figure 27. Interrupt Servicing and Polling tfltin tfltout CRDDET INT CS RDYMOD (out) CS to INT 15 mS typ. INTERRUPT SERVICING tdrdy POLLING http://onsemi.com 18 INTERRUPT SERVICING POLLING MC33560 Figure 28. Card Signal Sequence During VCC Overload and Unexpected Card Extraction MCU deactivates PWRON after card extraction poll with PWRON = L –> RDYMOD = H: card still present CS = L, PWRON = H CRDVCC undervoltage –> RDYMOD = L overload time smaller than tdres (glitch not to scale) card inserted tfltin tfltout VTxH VTxL CRDVCC CRDDET INT CS RDYMOD PWRON tdrdy poll with PWRON = L –> RDYMOD = H: card present tdres tdres 35 ns typ MCU polls RDYMOD = H overload time greater than tdres –> converter stop and CRDVCC pull down http://onsemi.com 19 card extraction poll with PWRON = H –> RDYMOD = L: DC/DC converter overload MC33560 RDYMOD CS RESET IO SYNCLK ASYCLK CRDCLK RDYMOD CS RESET IO SYNCLK ASYCLK CRDCLK Figure 29. ”On–the–fly” Card Clock Selection Examples http://onsemi.com 20 M1 7805 47k + C1 Connector 10 uF DB9 U3 C1+ VCC C2– C1– VSS RX1 VDD DO1 TX1 RX2 DI 1 DO2 TX2 DI 2 RX3 TX3 DO3 DI 3 C4 + 10 uF C2 mC reset 10 uF MC145407 Q1: XTAL 4MHz D1: General Purpose diode R1: 47 kOhm C1, C2, C4,C5: 10 uF R2: 1 MOhm C3: 220 nF L1: MURATA LQH3C 47 uH R3: 1 MOhm C6: 200 nF C7: 10 uF C8, C9: 22 pF M1: 7805 regulator R4: Value depending on max. card current Z1: General Purpose 40 V zener diode U4: Card connector R1 RESET VDD IRQ 0SC1 C3 VPP OSC2 220 nF NC TCAP PA7 PD7 PA6 NC PA5 TCMP PA4 SS PA3 SCLK PA2 MOSI PA1 MISO PA0 RDI PB0 TDO PB1 PC0 PB2 PC1 PB3 PC2 NC PC3 PB4 PC4 PB5 PC5 PB6 PC6 PB7 PC7 VSS NC MC68HC705C9 U1 Z1 Q1 4 MHz C8 22 pF R3 1M C10 0.1 uF C9 22 pF R4* U2 MC33560 1 – PGND 2 – PWRON 3 – INT 4 – RDYMOD 5 – CS 6 – RESET 7 – IO 8 – INVOUT 9 – ASYCLKIN 10 – SYNCLK 11 – CRDIO 12 – CRDGND L1 47 uH ILIM – 24 VBAT – 23 L1 – 22 C4 – 21 C8 – 20 CRDC8 – 19 CRDCON – 18 CRDDET – 17 CRDC4 – 16 CRDCLK – 15 CRDRST – 14 CRDVCC – 13 Card Detect R2 1M C8 C4 CLK RST VCC GND I/O C7 C6 10 uF 200 nF U4 Card Slot MC33560 21 http://onsemi.com C2+ GND 8..40 VDC Figure 30. Card Reader/Writer Application C5 10 uF + D1 VBAT mC reset http://onsemi.com 22 MC68HC705 RESET VDD IRQ 0SC1 VPP OSC2 NC TCAP PA7 PD7 PA6 NC PA5 TCMP PA4 SS SCLK PA3 MOSI PA2 MISO PA1 RDI PA0 TDO PB0 PC0 PB1 PC1 PB2 PC2 PB3 PC3 NC PC4 PB4 PC5 PB5 PC6 PB6 PC7 PB7 NC VSS 1 – PGND 2 – PWRON 3 – INT 4 – RDYMOD 5 – CS 6 – RESET 7 – IO 8 – INVOUT 9 – ASYCLKIN 10 – SYNCLK 11 – CRDIO 12 – CRDGND MC33560 1 – PGND 2 – PWRON 3 – INT 4 – RDYMOD 5 – CS 6 – RESET 7 – IO 8 – INVOUT 9 – ASYCLKIN 10 – SYNCLK 11 – CRDIO 12 – CRDGND MC33560 ILIM – 24 VBAT – 23 L1 – 22 C4 – 21 C8 – 20 CRDC8 – 19 CRDCON – 18 CRDDET – 17 CRDC4 – 16 CRDCLK – 15 CRDRST – 14 CRDVCC – 13 ILIM – 24 VBAT – 23 L1 – 22 C4 – 21 C8 – 20 CRDC8 – 19 CRDCON – 18 CRDDET – 17 CRDC4 – 16 CRDCLK – 15 CRDRST – 14 CRDVCC – 13 VBAT VBAT GND I/O C4 CLK RST VCC C8 Card Detect GND I/O C4 CLK RST VCC C8 Card Detect MC33560 Figure 31. Multi Slot Card Reader/Writer Application MC33560 PACKAGE DIMENSIONS (TSSOP–24) DTB SUFFIX PLASTIC PACKAGE CASE 948H–01 ISSUE O 24X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S 2X 24 L/2 13 B –U– L PIN 1 IDENT. 12 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. S A –V– DIM A B C D F G H J J1 K K1 L M C 0.10 (0.004) –T– SEATING PLANE G D H –W– DETAIL E N 0.25 (0.010) K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J1 M N F SECTION N–N DETAIL E J http://onsemi.com 23 MILLIMETERS MIN MAX 7.70 7.90 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.303 0.311 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC33560 PACKAGE DIMENSIONS (SO–24L) DW SUFFIX PLASTIC PACKAGE CASE 751E–04 ISSUE E –A– 24 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 13 –B– 12X P 0.010 (0.25) 1 M B M 12 24X D J 0.010 (0.25) M T A S B S F R C –T– SEATING PLANE M 22X G K X 45 _ DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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