MOTOROLA MTP15N06V

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SEMICONDUCTOR TECHNICAL DATA
 Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
15 AMPERES
60 VOLTS
RDS(on) = 0.12 OHM
TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
TM
D
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E–FET Predecessors
G
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and
TMOS E–FET
S
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
60
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDSS
VDGR
60
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Single Pulse (tp ≤ 50 µs)
VGS
VGSM
± 20
± 25
Vdc
Vpk
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
15
8.7
45
Adc
Total Power Dissipation @ 25°C
Derate above 25°C
PD
55
0.5
Watts
W/°C
TJ, Tstg
EAS
– 55 to 175
°C
113
mJ
RθJC
RθJA
2.73
62.5
°C/W
TL
260
°C
Rating
Drain–Source Voltage
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Apk
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
TMOS
 Motorola
Motorola, Inc.
1996
Power MOSFET Transistor Device Data
1
MTP15N06V
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
60
—
—
67
—
—
Vdc
mV/°C
—
—
—
—
10
100
—
—
100
nAdc
2.0
—
2.7
5.0
4.0
—
Vdc
mV/°C
—
0.08
0.12
Ohm
—
—
2.0
—
2.2
1.9
gFS
4.0
6.2
—
mhos
Ciss
—
469
660
pF
Coss
—
148
200
Crss
—
35
60
td(on)
—
7.6
20
tr
—
51
100
td(off)
—
18
40
tf
—
33
70
QT
—
14.4
20
Q1
—
2.8
—
Q2
—
6.4
—
Q3
—
6.1
—
—
—
1.05
1.5
1.6
—
trr
—
59.3
—
ta
—
46
—
tb
—
13.3
—
QRR
—
0.165
—
µC
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
—
4.5
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
—
7.5
—
nH
Characteristic
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
µAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 7.5 Adc)
RDS(on)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 15 Adc)
(ID = 7.5 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 30 Vdc, ID = 15 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
Fall Time
Gate Charge
(See Figure 8)
(VDS = 48 Vdc, ID = 15 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 15 Adc, VGS = 0 Vdc)
(IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(See Figure 14)
(IS = 15 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
VSD
Vdc
ns
INTERNAL PACKAGE INDUCTANCE
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
MTP15N06V
TYPICAL ELECTRICAL CHARACTERISTICS
30
I D , DRAIN CURRENT (AMPS)
7V
20
15
6V
10
5V
1
2
3
4
6
5
25°C
15
10
2
4
6
8
10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
VGS = 10 V
TJ = 100°C
0.14
25°C
0.08
– 55°C
0
5
25
10
15
20
ID, DRAIN CURRENT (AMPS)
30
0.13
TJ = 25°C
0.11
VGS = 10 V
0.09
15 V
0.07
0.05
0
Figure 3. On–Resistance versus Drain Current
and Temperature
5
10
15
20
ID, DRAIN CURRENT (AMPS)
25
30
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
100
2
VGS = 0 V
VGS = 10 V
ID = 7.5 A
1.6
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
– 55°C
20
0
7
R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0
0.20
0.02
25
5
5
0
TJ = 100°C
VDS ≥ 10 V
9V
25
I D , DRAIN CURRENT (AMPS)
30
8V
VGS = 10 V
TJ = 25°C
1.2
0.8
0.4
– 50
– 25
0
25
50
75
100
125
150
175
TJ = 125°C
10
TJ, JUNCTION TEMPERATURE (°C)
30
10
20
40
50
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
0
60
3
MTP15N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1500
VDS = 0 V
VGS = 0 V
TJ = 25°C
C, CAPACITANCE (pF)
1200
Ciss
900
600
Ciss
Crss
300
Coss
Crss
0
10
5
5
0
VGS
10
15
20
25
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
60
QT
50
10
VGS
8
40
Q2
Q1
6
30
4
20
ID = 15 A
TJ = 25°C
2
0
0
Q3
3
VDS
6
9
12
10
0
15
1000
VDD = 30 V
ID = 15 A
VGS = 10 V
TJ = 25°C
t, TIME (ns)
12
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
MTP15N06V
100
tr
tf
td(off)
10
td(on)
1
1
10
QT, TOTAL CHARGE (nC)
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
100
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
15
I S , SOURCE CURRENT (AMPS)
VGS = 0 V
TJ = 25°C
12
9
6
3
0
0.5
0.7
0.9
1.1
1.3
1.5
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
Motorola TMOS Power MOSFET Transistor Device Data
able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
5
MTP15N06V
SAFE OPERATING AREA
120
VGS = 10 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
10 µs
10
100 µs
1 ms
10 ms
1.0
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
10
1.0
0.1
ID = 15 A
100
80
60
40
20
0
25
100
50
75
100
125
150
175
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.0
D = 0.5
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
SINGLE PULSE
t1
t2
DUTY CYCLE, D = t1/t2
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
1.0E–01
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
1.0E+00
1.0E+01
t, TIME (s)
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
MTP15N06V
PACKAGE DIMENSIONS
–T–
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
SEATING
PLANE
C
F
T
S
4
A
Q
1 2 3
STYLE 5:
PIN 1.
2.
3.
4.
U
H
K
Z
L
R
V
J
G
D
N
GATE
DRAIN
SOURCE
DRAIN
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
–––
–––
0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
–––
–––
2.04
CASE 221A–06
ISSUE Y
Motorola TMOS Power MOSFET Transistor Device Data
7
MTP15N06V
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8
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*MTP15N06V/D*
Motorola TMOS Power MOSFET Transistor
Device Data
MTP15N06V/D