PYRAMID P4C164

P4C164
ULTRA HIGH SPEED 8K x 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
Common Data I/O
High Speed (Equal Access and Cycle Times)
– 8/10/12/15/20/25/35/70/100 ns (Commercial)
– 10/12/15/20/25/35/70/100 ns(Industrial)
– 12/15/20/25/35/45/70/100 ns (Military)
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil Plastic DIP, SOJ
– 28-Pin 600 mil Plastic DIP (70 & 100ns)
– 28-Pin 300 mil SOP (70 & 100ns)
– 28-Pin 300 mil Ceramic DIP
– 28-Pin 600 mil Ceramic DIP
– 28-Pin 350 x 550 mil LCC
– 32-Pin 450 x 550 mil LCC
– 28-Pin CERPACK
Low Power Operation
Output Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C164L Military)
DESCRIPTION
The P4C164 is a 65,536-bit ultra high-speed static RAM
organized as 8K x 8. The CMOS memory requires no
clocks or refreshing and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply. With
battery backup, data integrity is maintained with supply
voltages down to 2.0V. Current drain is typically 10 µA
from a 2.0V supply.
Access times as fast as 8 nanoseconds are available,
permitting greatly enhanced system operating speeds.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
The P4C164 is available in 28-pin 300 mil DIP and SOJ, 28pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil
LCC, 32-pin 450 x 550 mil LCC, and 28-pin CERPACK.
The 70ns and 100ns P4C164s are available in the 600 mil
plastic DIP.
DIP (P5, P6, C5, C5-1, D5-1, D5-2),
SOJ (J5), CERPACK (F4), SOP(S6)
1519B
SEE PAGE 7 FOR LCC PIN CONFIGURATIONS
Document # SRAM115 REV F
Revised June 2007
1
P4C164
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
VTERM
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
V
TA
Operating Temperature
–55 to +125
°C
Symbol
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Military
Industrial
Commercial
Ambient
Temperature
GND
VCC
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
0V
0V
0V
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
Symbol
Parameter
Conditions Typ. Unit
CIN
Input Capacitance
COUT
Output Capacitance VOUT = 0V
VIN = 0V
5
pF
7
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
Symbol
Parameter
P4C164
Min
Max
2.2
VCC +0.5
Test Conditions
VIH
Input High Voltage
VIL
Input Low Voltage
V HC
VLC
CMOS Input High Voltage
V CD
Input Clamp Diode Voltage VCC = Min., IIN = –18 mA
Output Low Voltage
IOL = +8 mA, VCC = Min.
(TTL Load)
Output High Voltage
IOH = –4 mA, VCC = Min.
(TTL Load)
VCC = Max.
Mil.
Input Leakage Current
VIN = GND to VCC
Ind./Com’l.
VOL
VOH
ILI
ILO
ISB
ISB1
–0.5(3)
0.8
P4C164L
Unit
Min
Max
2.2
VCC +0.5 V
–0.5(3)
0.8
VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5
CMOS Input Low Voltage
(3)
–0.5
0.2
–0.5
(3)
V
V
0.2
V
–1.2
–1.2
V
0.4
0.4
V
V
2.4
2.4
–10
–5
+10
+5
–5
n/a
+5
n/a
µA
–10
–5
+10
+5
–5
n/a
+5
n/a
µA
___
___
40
___
___
40
n/a
mA
Standby Power Supply
Current (TTL Input Levels)
CE1 ≥ VIH or
Mil.
CE2 ≤VIL,
Ind./Com’l.
VCC= Max,
f = Max., Outputs Open
___
___
25
___
___
1
n/a
mA
Standby Power Supply
Current
(CMOS Input Levels)
CE1 ≥ VHC or
Mil.
CE2 ≤VLC,
Ind./Com’l.
VCC= Max,
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
Output Leakage Current
VCC = Max., CE = VIH,
VOUT = GND to VCC
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
Document # SRAM115 REV F
Mil.
Ind./Com’l.
30
15
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Page 2 of 16
P4C164
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
ICC
Dynamic Operating Current* Industrial
Military
-8
-10
-12
-15
-20
-25
-35
45
-70 -100
Unit
200 180 170 160 155 150 145 N/A 130 125
mA
N/A 190 180 170 160 155 150 N/A 145 140
mA
N/A N/A 180 170 160 155 150 145 145 145
mA
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH
DATA RETENTION CHARACTERISTICS (P4C164L, Military Temperature Only)
Symbol
Parameter
Test Condition
V DR
VCC for Data Retention
ICCDR
Data Retention Current
t CDR
Chip Deselect to
CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V
Data Retention Time
or VIN ≤ 0.2V
tR
†
Min
Typ.*
VCC =
2.0V
3.0V
Max
VCC =
2.0V
3.0V
2.0
Operation Recovery Time
V
10
CE1 ≥ VCC – 0.2V or
Unit
15
200
300
µA
0
ns
tRC§
ns
*TA = +25°C
§
tRC = Read Cycle Time
†
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM115 REV F
Page 3 of 16
P4C164
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Symbol
Parameter
-8
-10
-12
-15
-20
-25
-35
-45
-70
-100
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
tRC
Read Cycle
Time
tAA
Address
Access Time
8
10
12
15
20
25
35
45
70
100
ns
tAC
Chip Enable
Access Time
8
10
12
15
20
25
35
45
70
100
ns
tOH
Output Hold
from Address
Change
3
3
3
3
3
3
3
3
3
3
ns
tLZ
Chip Enable to
Output in Low Z
2
2
2
2
2
2
2
2
2
2
ns
tHZ
Chip Disable
to Output in
High Z
5
6
7
8
8
10
15
20
35
45
ns
tOE
Output Enable
Low to Data
Valid
5
6
7
9
10
13
18
20
35
45
ns
tOLZ
Output Enable
Low to Low Z
tOHZ
Output Enable
High to High Z
tPU
Chip Enable to
Power Up
Time
tPD
Chip Disable
to Power Down
Time
8
10
2
12
2
5
0
2
6
0
8
15
2
7
0
10
20
2
9
0
12
25
2
9
0
15
35
2
12
0
20
45
2
15
0
20
70
2
20
0
20
100
2
35
0
25
ns
ns
45
0
35
ns
ns
45
ns
OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE
Notes:
5. WE is HIGH for READ cycle.
6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE1 transition
LOW and CE2 transition HIGH.
Document # SRAM115 REV F
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
Page 4 of 16
P4C164
TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
CE1, CE2 CONTROLLED)(5,7,10)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE
Notes:
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether CE1 or CE2 causes them.
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-8
-10
-12
-15
-20
-25
-35
-45
-70
-100
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Symbol
Parameter
tWC
Write Cycle Time
8
10
12
15
20
25
35
45
70
100
ns
tCW
Chip Enable
Time to End of
Write
6
7
8
12
15
18
25
33
50
70
ns
tAW
Address Valid to
End of Write
7
8
10
12
15
18
25
33
50
70
ns
0
0
0
0
0
0
0
0
0
0
ns
7
8
9
12
15
18
20
25
40
50
ns
0
0
0
0
0
0
0
0
0
0
ns
6
7
8
9
11
13
15
20
30
40
ns
0
0
0
0
0
0
0
0
0
0
ns
tAS
tWP
tAH
tDW
Address Set-up
Time
Write Pulse
Width
Address Hold
Time
Data Valid to
End of Write
tDH
Date Hold Time
tWZ
Write Enable to
Output in High Z
tOW
Output Active
from End of
Write
6
3
Document # SRAM115 REV F
7
3
7
3
7
3
8
3
10
3
14
3
18
3
30
3
40
3
ns
ns
Page 5 of 16
P4C164
WE CONTROLLED)(11)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE
CE CONTROLLED)(11)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
Notes:
11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle.
12. OE is LOW for this WRITE cycle to show tWZ and tOW.
13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH,
the output remains in a high impedance state.
Document # SRAM115 REV F
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Page 6 of 16
P4C164
AC TEST CONDITIONS
TRUTH TABLE
Input Pulse Levels
GND to 3.0V
Mode
CE1
CE2
OE
WE
I/O
Power
Input Rise and Fall Times
3ns
Standby
H
X
X
X
High Z
Standby
Input Timing Reference Level
1.5V
Standby
X
L
X
X
High Z
Standby
Output Timing Reference Level
1.5V
DOUT
Disabled
L
H
H
H
High Z
Active
Read
L
H
L
H
DOUT
Active
Write
L
H
X
L
High Z
Active
Output Load
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the high speed of the P4C164/L, care must be taken when
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
LCC PIN CONFIGURATIONS
LCC (L5)
"L" - STANDARD PIN-OUT
Document # SRAM115 REV F
LCC (L5)
"LS" - SPECIAL PIN-OUT
LCC (L6)
Page 7 of 16
P4C164
ORDERING INFORMATION
SELECTION GUIDE
The P4C164 is available in the following temperature, speed and package options. The P4C164L is available only over
the military temperature range.
Spe e d (ns)
Te m pe ra ture
Ra nge
Commercial
Industrial
Pa cka ge
Plastic DIP (300 mil)
8
10
12
15
20
25
35
45
70
100
-8PC
-10PC
-12PC
-15PC
-20PC
-25PC
-35PC
N/A
N/A
N/A
-100P6C
Plastic DIP (600 mil)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-70P6C
Plastic SOJ
-8JC
-10JC
-12JC
-15JC
-20JC
-25JC
-35JC
N/A
N/A
N/A
Plastic SOP
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-70SNC
-100SNC
Plastic DIP (300 mil)
N/A
-10PI
-12PI
-15PI
-20PI
-25PI
-35PI
N/A
N/A
N/A
Plastic DIP (600 mil)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-70P6I
-100P6I
Plastic SOJ
N/A
-10JI
-12JI
-15JI
-20JI
-25JI
-35JI
N/A
N/A
N/A
Plastic SOP
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-70SNI
-100SNI
N/A = Not available
Document # SRAM115 REV F
Page 8 of 16
P4C164
SELECTION GUIDE (continued)
Temperature
Range
Military
Temperature
Military
Processed *
Package
Side Brazed DIP
Speed (ns)
8
10
12
15
20
25
35
45
70
100
N/A
N/A
-12CM
-15CM
-20CM
-25CM
-35CM
-45CM
-70CM
-100CM
CERDIP (300 mil)
N/A
N/A
-12DM
-15DM
-20DM
-25DM
-35DM
-45DM
-70DM
-100DM
CERDIP (600 mil)
N/A
N/A
-12DWM
-15DWM
-20DWM
-25DWM
-35DWM
-45DWM
-70DWM
-100DWM
CERPACK
N/A
N/A
-12FM
-15FM
-20FM
-25FM
-35FM
-45FM
-70FM
-100FM
28-Pin LCC
N/A
N/A
-12LM
-15LM
-20LM
-25LM
-35LM
-45LM
-70LM
-100LM
28-Pin LCC **
32-Pin LCC
N/A
N/A
-12LSM
-15LSM
-20LSM
-25LSM
-35LSM
-45LSM
-70LSM
-100LSM
N/A
N/A
-12L32M
-15L32M
-20L32M
-25L32M
-35L32M
-45L32M
-70L32M
-100L32M
Side Brazed DIP
N/A
N/A
-12CMB
-15CMB
-20CMB
-25CMB
-35CMB
-45CMB
-70CMB
-100CMB
CERDIP (300 mil)
N/A
N/A
-12DMB
-15DMB
-20DMB
-25DMB
-35DMB
-45DMB
-70DMB
-100DMB
CERDIP (600 mil)
N/A
N/A
-12DWMB
-15DWMB
-20DWMB
-25DWMB
-35DWMB
-45DWMB
CERPACK
N/A
N/A
-12FMB
-15FMB
-20FMB
-25FMB
-35FMB
-45FMB
-70FMB
-100FMB
28-Pin LCC
N/A
N/A
-12LMB
-15LMB
-20LMB
-25LMB
-35LMB
-45LMB
-70LMB
-100LMB
28-Pin LCC **
32-Pin LCC
N/A
N/A
N/A
N/A
-12LSMB
-12L32MB
-15LSMB
-15L32MB
-20LSMB
-20L32MB
-25LSMB
-25L32MB
-35LSMB
-35L32MB
-45LSMB
-45L32MB
-70DWMB -100DWMB
-70LSMB -100LSMB
-70L32MB -100L32MB
* Military temperature range with MIL-STD-883, Class B processing.
** SPECIAL PINOUT
N/A = Not available
Document # SRAM115 REV F
Page 9 of 16
P4C164
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
C5
SIDE BRAZED DUAL IN-LINE PACKAGE (300 mils)
28 (300 mil)
Min
Max
0.225
0.014
0.026
0.045
0.065
0.008
0.018
1.485
0.240
0.310
0.300 BSC
0.100 BSC
0.125
0.200
0.015
0.070
0.005
0.005
-
C5-1
SIDE BRAZED DUAL IN-LINE PACKAGE (600 mils)
28 (600 mil)
Min
Max
0.232
0.014
0.026
0.045
0.065
0.008
0.018
1.490
0.500
0.610
0.600 BSC
0.100 BSC
0.125
0.200
0.015
0.060
0.005
0.005
-
Document # SRAM115 REV F
Page 10 of 16
P4C164
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
α
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
α
D5-1
CERDIP DUAL IN-LINE PACKAGE
28 (600 mil)
Min
Max
0.232
0.014
0.026
0.045
0.065
0.008
0.018
1.490
0.500
0.610
0.600 BSC
0.100 BSC
0.125
0.200
0.015
0.060
0.005
0°
15°
D5-2
CERDIP DUAL IN-LINE PACKAGE
28 (300 mil)
Min
Max
0.225
0.014
0.026
0.045
0.065
0.008
0.018
1.485
0.240
0.310
0.300 BSC
0.100 BSC
0.125
0.200
0.015
0.060
0.005
0°
15°
Document # SRAM115 REV F
Page 11 of 16
P4C164
Pkg #
# Pins
Symbol
A
b
c
D
E
e
k
L
Q
S
S1
Pkg #
# Pins
Symbol
A
A1
b
C
D
e
E
E1
E2
Q
F4
CERPACK CERAMIC FLAT PACKAGE
28
Min
Max
0.060
0.090
0.015
0.022
0.004
0.009
0.730
0.330
0.380
0.050 BSC
0.005
0.018
0.250
0.370
0.026
0.045
0.085
0.005
-
J5
SOJ SMALL OUTLINE IC PACKAGE
28 (300 mil)
Min
Max
0.120
0.148
0.078
0.014
0.020
0.007
0.011
0.700
0.730
0.050 BSC
0.335 BSC
0.292
0.300
0.267 BSC
0.025
-
Document # SRAM115 REV F
Page 12 of 16
P4C164
Pkg #
# Pins
Symbol
A
A1
B1
D
D1
D2
D3
E
E1
E2
E3
e
h
j
L
L1
L2
ND
NE
Pkg #
# Pins
Symbol
A
A1
B1
D
D1
D2
D3
E
E1
E2
E3
e
h
j
L
L1
L2
ND
NE
L5
RECTANGULAR LEADLESS CHIP CARRIER
28
Min
Max
0.060
0.075
0.050
0.065
0.022
0.028
0.342
0.358
0.200 BSC
0.100 BSC
0.358
0.540
0.560
0.400 BSC
0.200 BSC
0.558
0.050 BSC
0.040 REF
0.020 REF
0.045
0.055
0.045
0.055
0.075
0.095
5
9
L6
RECTANGULAR LEADLESS CHIP CARRIER
32
Min
Max
0.060
0.075
0.050
0.065
0.022
0.028
0.442
0.458
0.300 BSC
0.150 BSC
0.458
0.540
0.560
0.400 BSC
0.200 BSC
0.558
0.050 BSC
0.040 REF
0.020 REF
0.045
0.055
0.045
0.055
0.075
0.095
7
9
Document # SRAM115 REV F
Page 13 of 16
P4C164
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
α
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
α
P5
PLASTIC DUAL IN-LINE PACKAGE (300 mils)
28 (300 mil)
Min
Max
0.210
0.014
0.023
0.045
0.070
0.008
0.014
1.345
1.400
0.270
0.300
0.300
0.380
0.100 BSC
0.430
0.115
0.150
0°
15°
P6
PLASTIC DUAL IN-LINE PACKAGE (600 mils)
28 (600 mil)
Min
Max
0.090
0.200
0.000
0.070
0.014
0.020
0.015
0.065
0.008
0.012
1.380
1.480
0.485
0.550
0.600
0.625
0.100 BSC
0.600 TYP
0.100
0.200
0°
15°
Document # SRAM115 REV F
Page 14 of 16
P4C164
Pkg #
# Pins
Symbol
A
A1
B
C
D
e
E
H
L
α
S6
SOIC/SOP SMALL OUTLINE IC PACKAGE (SN)
28 (300 mil)
Min
Max
0.090
0.110
0.003
0.010
0.012
0.020
0.004
0.012
0.700
0.716
0.050 BSC
0.290
0.300
0.465
0.485
0.016
0.050
0°
9°
Document # SRAM115 REV F
Page 15 of 16
P4C164
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM115
P4C164 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
1997
DAB
New Data Sheet
A
Oct-05
JDB
Change logo to Pyramid
B
Jun-06
JDB
Added 28-pin ceramic DIP
C
Aug-06
JDB
Added Lead Free Designation
D
Aug-06
JDB
Added "LS" - SPECIAL PIN-OUT
E
Aug-06
JDB
Updated SOJ package information
F
Jun-07
JDB
Corrected SOP package details
Document # SRAM115 REV F
DESCRIPTION OF CHANGE
Page 16 of 16