PYRAMID P4C188-35LI

P4C188/P4C188L
ULTRA HIGH SPEED 16K x 4
STATIC CMOS RAMS
FEATURES
Single 5V±10% Power Supply
Data Retention with 2.0V Supply
(P4C188L Military)
Three-State Outputs
TTL/CMOS Compatible Outputs
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290 x 490 mil LCC
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power (Commercial/Military)
– 715 mW Active – 12/15
– 550/660 mW Active – 20/25/35/45
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C188
– 15 mW Standby (CMOS Input)
(P4C188L Military)
DESCRIPTION
The P4C188 and P4C188L are 65,536-bit ultra high speed
static RAMs organized as 16K x 4. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. Inputs and outputs are fully TTL-compatible.
The RAMs operate from a single 5V±10% tolerance power
supply. With battery backup, data integrity is maintained for
supply voltages down to 2.0V. Current drain is typically 10
µA from a 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption to a low 715mW
active, 193mW standby and only 5mW in the P4C188L
version.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
The P4C188 and P4C188L are available in 22-pin 300 mil
DIP, 24-pin 300 mil SOJ and 22-pin LCC packages providing excellent board level densities.
DIP (P3, D3, C3)
LCC (L3)
For SOJ pin configuration, please see end of datasheet.
Document # SRAM112 REV A
1
Revised October 2005
P4C188/188L
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
VTERM
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
V
TA
Operating Temperature
–55 to +125
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Ambient
Temperature
GND
VCC
0V
0V
0V
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
Military
–55°C to +125°C
–40°C to +85°C
Industrial
0°C to +70°C
Commercial
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions Typ. Unit
VIN = 0V
5
pF
VOUT = 0V
7
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
VHC
CMOS Input High Voltage
VLC
CMOS Input Low Voltage
VCD
Input Clamp Diode Voltage VCC = Min., IIN = 18 mA
VOL
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
VOH
ILI
–0.5(3)
Output Leakage Current
0.8
P4C188L
Unit
Min
Max
2.2
VCC +0.5 V
–0.5(3)
0.8
VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5
–0.5
(3)
IOL = +8 mA, VCC = Min.
IOH = –4 mA, VCC = Min.
VCC = Max.
VIN = GND to VCC
ILO
P4C188
Min
Max
2.2
VCC +0.5
Test Conditions
VCC = Max., CE = VIH,
VOUT = GND to VCC
0.2
Mil.
Com’l.
Mil.
Com’l.
V
0.2
V
–1.2
–1.2
V
0.4
0.4
V
2.4
–0.5(3)
V
2.4
V
–10
–5
+10
+5
–5
n/a
+5
n/a
µA
–10
–5
+10
+5
–5
n/a
+5
n/a
µA
ISB
Standby Power Supply
CE ≥ VIH
Mil.
Current (TTL Input Levels) VCC = Max .,
Ind./Com’l.
f = Max., Outputs Open
___
___
40
35
___
___
40
n/a
mA
ISB1
Standby Power Supply
Current
(CMOS Input Levels)
CE ≥ VHC
Mil.
VCC = Max.,
Ind./Com’l.
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
___
___
20
15
___
___
2.7
n/a
mA
n/a = Not Applicable
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
Document # SRAM112 REV A
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Page 2 of 12
P4C188/188L
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
ICC
Temperature
Range
Parameter
Dynamic Operating Current*
Unit
–10
–12
–15
–20
–25
–35
–45
Commercial
180
170
160
155
150
N/A
N/A
mA
Industrial
N/A
180
170
160
155
150
N/A
mA
Military
N/A
N/A
170
160
155
150
145
mA
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL
DATA RETENTION CHARACTERISTICS (P4C188L Military Temperature Only)
Symbol
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to
Data Retention Time
tR†
Operation Recovery Time
Test Conditions
Min
Typ.*
VCC =
2.0V
3.0V
Max
VCC =
2.0V 3.0V
V
2.0
CE ≥ VCC –0.2V,
VIN ≥ VCC –0.2V or
VIN ≤ 0.2V
Unit
10
15
600
900
µA
0
ns
tRC§
ns
*TA = +125°C
tRC = Read Cycle Time
§
†
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM112 REV A
Page 3 of 12
P4C188/188L
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
Parameter
-10
-12
-15
-20
-25
-35
-45
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Unit
tRC
Read Cycle Time 10
tAA
Address Access
Time
10
12
15
20
25
35
45
ns
tAC
Chip Enable
Access Time
10
12
15
20
25
35
45
ns
tOH
Output Hold from
Address Change
2
2
2
2
2
2
2
ns
tLZ
Chip Enable to
Output in Low Z
2
2
2
3
3
3
3
ns
tHZ
Chip Disable to
Output in High Z
tPU
Chip Enable to
Power Up Time
tPD
Chip Disable to
Power Down
Time
12
5
0
15
6
0
10
20
6
0
12
25
8
0
15
35
10
0
20
45
20
25
0
0
25
ns
35
ns
ns
45
ns
TIMING WAVEFORM OF READ CYCLE NO. 1(5)
TIMING WAVEFORM OF READ CYCLE NO. 2(6)
Notes:
5. CE is LOW and WE is HIGH for READ cycle.
6. WE is HIGH, and address must be valid prior to or coincident with CE
transition LOW.
Document # SRAM112 REV A
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Page 4 of 12
P4C188/188L
AC CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
Parameter
-12
-10
-15
-20
-25
-35
-45
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Unit
tWC
Write Cycle Time
10
12
13
20
25
35
45
ns
tCW
Chip Enable
Time to
End of Write
7
8
10
13
15
25
35
ns
tAW
Address Valid
to End of Write
7
8
10
15
20
25
35
ns
tAS
Address
Set-up Time
0
0
0
0
0
0
0
ns
tWP
Write Pulse
Width
8
9
10
13
15
25
35
ns
tAH
Address Hold
Time from
End of Write
0
0
0
0
0
0
0
ns
tDW
Data Valid to
End of Write
5
6
7
8
10
15
20
ns
tDH
Data Hold
Time
0
0
0
0
0
0
5
ns
tWZ
Write Enable
to Output in
High Z
tDW
Output Active
from End
of Write
2
6
6
5
2
2
10
8
2
2
20
15
3
3
ns
ns
WE CONTROLLED) (9)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE
Notes:
9. CE and WE must be LOW for WRITE cycle.
10. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
Document # SRAM112 REV A
12. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is
sampled and not 100% tested.
Page 5 of 12
P4C188/188L
CE CONTROLLED)(9)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
AC TEST CONDITIONS
Input Pulse Levels
TRUTH TABLE
GND to 3.0V
Mode
CE
WE
Output
Power
Standby
Input Rise and Fall Times
3ns
Standby
H
X
High Z
Input Timing Reference Level
1.5V
Read
L
H
DOUT
Active
Output Timing Reference Level
1.5V
Write
L
L
DIN
Active
Output Load
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C188/L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
Document # SRAM112 REV A
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
Page 6 of 12
P4C188/188L
ORDERING INFORMATION
1513 10
SELECTION GUIDE
The P4C188/L is available in the following temperature, speed and package options. The P4C188L is only available
over the Military Temperature range.
Temperature
Range
Commercial
Industrial
Military
Temperature
Military
Processed*
Package
Speed (ns)
10
12
15
20
25
35
45
Plastic DIP
-10PC
-12PC
-15PC
-20PC
-25PC
-35PC
45PC
Plastic SOJ
-10JC
-12JC
-15JC
-20JC
-25JC
-35JC
-45JC
Plastic DIP
N/A
-12PI
-15PI
-20PI
-25PI
-35PI
-45PI
Plastic SOJ
N/A
-12JI
-15JI
-20JI
-25JI
-35JI
-45JI
Side Brazed DIP
N/A
N/A
-15CM
-20CM
-25CM
-35CM
-45CM
CERDIP
N/A
N/A
-15DM
-20DM
-25DM
-35DM
-45DM
LCC
N/A
N/A
-15LM
-20LM
-25LM
-35LM
-45LM
Side Brazed DIP
N/A
N/A
-15CMB
-20CMB
-25CMB
-35CMB
-45CMB
CERDIP
N/A
N/A
-15DMB
-20DMB
-25DMB
-35DMB
-45DMB
LCC
N/A
N/A
-15LMB
-20LMB
-25LMB
-35LMB
-45LMB
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not Available
Document # SRAM112 REV A
Page 7 of 12
P4C188/188L
SOJ PIN CONFIGURATION
SOJ (J4)
Document # SRAM112 REV A
Page 8 of 12
P4C188/188L
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
α
C3
SIDE BRAZED DUAL IN-LINE PACKAGE
22 (300 mil)
Min
Max
0.100
0.200
0.014
0.023
0.030
0.060
0.008
0.015
1.050
1.260
0.260
0.310
0.300 BSC
0.100 BSC
0.125
0.200
0.015
0.070
0.005
0.005
-
D3
CERDIP DUAL IN-LINE PACKAGE
22 (300 mil)
Min
Max
0.225
0.015
0.020
0.045
0.065
0.009
0.012
1.060
1.110
0.290
0.320
0.300 BSC
0.100 BSC
0.125
0.200
0.015
0.060
0.005
0°
15°
Document # SRAM112 REV A
Page 9 of 12
P4C188/188L
Pkg #
# Pins
Symbol
A
A1
b
C
D
e
E
E1
E2
Q
Pkg #
# Pins
Symbol
A
A1
B1
D
D1
D2
D3
E
E1
E2
E3
e
h
j
L
L1
L2
ND
NE
J4
SOJ SMALL OUTLINE IC PACKAGE
24 (300 mil)
Min
Max
0.128
0.148
0.082
0.016
0.020
0.007
0.010
0.620
0.630
0.050 BSC
0.335 BSC
0.292
0.300
0.267 BSC
0.025
-
L3
RECTANGULAR LEADLESS CHIP CARRIER
22
Min
Max
0.060
0.080
0.050
0.068
0.022
0.028
0.284
0.296
0.150 BSC
0.075 BSC
0.296
0.484
0.496
0.300 BSC
0.150 BSC
0.496
0.050 BSC
R = .012
R = .012
0.039
0.051
0.039
0.051
0.058
0.072
4
7
Document # SRAM112 REV A
Page 10 of 12
P4C188/188L
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
α
P3
PLASTIC DUAL IN-LINE PACKAGE
22 (300 Mil)
Min
Max
0.210
0.015
0.014
0.022
0.045
0.070
0.008
0.014
1.145
1.165
0.240
0.280
0.300
0.325
0.100 BSC
0.430
0.115
0.150
0°
15°
Document # SRAM112 REV A
Page 11 of 12
P4C188/188L
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM112
P4C188 / P4C188L ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
1997
DAB
New Data Sheet
A
Oct-05
JDB
Change logo to Pyramid
Document # SRAM112 REV A
DESCRIPTION OF CHANGE
Page 12 of 12