INTEGRATED CIRCUITS DATA SHEET PCF8812 65 × 102 pixels matrix LCD driver Product specification File under Integrated Circuits, IC12 2000 Nov 22 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 CONTENTS 10 INSTRUCTIONS 10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.4 10.4.1 10.5 10.6 10.7 10.8 10.9 10.10 Initialization Reset function Function set PD V H Display control D and E Set Y address of RAM Set X address of RAM Set HV-generator stages Bias system Temperature control Set VOP value 11 LIMITING VALUES 12 HANDLING 13 DC CHARACTERISTICS 14 AC CHARACTERISTICS 15 SERIAL INTERFACE 16 RESET 17 APPLICATION INFORMATION 18 CHIP INFORMATION 19 PAD INFORMATION 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 PIN FUNCTIONS 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 7.1.14 Pin functions ROW 0 to ROW 64 row driver outputs COL 0 to COL 101 column driver outputs VSS1 and VSS2: negative power supply rails VDD1 to VDD3: positive power supply rails VLCDIN: LCD power supply VLCDOUT: LCD power supply VLCDSENSE: voltage multiplier regulation input (VLCD) T1 to T5: test pads SDIN: serial data line SCLK: serial clock line D/C: mode select SCE: chip enable OSC: oscillator RES: reset 8 FUNCTIONAL DESCRIPTION 20 BONDING PAD LOCATION 8.1 8.2 8.3 8.4 8.5 8.6 Oscillator Address Counter (AC) Display Data RAM (DDRAM) Timing generator Display address counter LCD row and column drivers 21 DEVICE PROTECTION DIAGRAM 22 TRAY INFORMATION 23 DATA SHEET STATUS 24 DEFINITIONS 25 DISCLAIMERS 9 ADDRESSING 9.1 Data structure 2000 Nov 22 2 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 1 PCF8812 2 FEATURES APPLICATIONS • Telecom equipment. • 65 row and 102 column outputs • Display data RAM 65 × 102 bits • On-chip: 3 – Configurable 5 (4, 3 and 2) voltage multiplier generating VLCD (external VLCD also possible) GENERAL DESCRIPTION The PCF8812 is a low power CMOS LCD controller driver, designed to drive a graphic display of 65 rows and 102 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The PCF8812 interfaces to microcontrollers via a serial bus interface. – Generation of intermediate LCD bias voltages – Oscillator requires no external components (external clock also possible). • External reset input pin • Serial interface maximum 4.0 Mbit/s • CMOS compatible inputs • Mux rate: 1 : 65 • Logic supply voltage range VDD1 to VSS: – 2.5 to 5.5 V. • High voltage generator supply voltage range VDD2 to VSS and VDD3 to VSS – 2.5 to 4.5 V. • Display supply voltage range VLCD to VSS: – 4.5 to 9.0 V. • Low power consumption, suitable for battery operated systems • Temperature compensation of VLCD • Temperature range: Tamb = −40 to +85 °C • Slim chip layout, suited for Chip-On-Glass (COG) applications. 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8812U/2 2000 Nov 22 Tray DESCRIPTION VERSION − chip with bumps in tray 3 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 5 PCF8812 BLOCK DIAGRAM VDD1 handbook, full pagewidth VDD2 VDD3 ROW0 to ROW64 COL0 to COL101 65 102 ROW DRIVERS COLUMN DRIVERS VLCDIN BIAS VOLTAGE GENERATOR SHIFT REGISTER DATA LATCHES VLCDSENSE VLCDOUT HIGH VOLTAGE GENERATOR 4 stages DISPLAY DATA RAM (DDRAM) 65 × 102 bits VSS1 VSS2 OSCILLATOR OSC ADDRESS COUNTER T2 DISPLAY ADDRESS COUNTER T3 T5 RES TIMING GENERATOR T1 T4 RESET DATA REGISTER PCF8812 I/O BUFFER MGT636 SDIN SCLK D/C Fig.1 Block diagram. 2000 Nov 22 4 SCE Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 6 PCF8812 PINNING SYMBOL RES 7 PAD 1 PIN FUNCTIONS 7.1 DESCRIPTION 7.1.1 external reset input (active LOW) Pin functions ROW 0 TO ROW 64 ROW DRIVER OUTPUTS These pads output the row signals. ROW 32 to ROW 19 2 to 15 LCD row driver outputs ROW 0 to ROW 18 18 to 36 LCD row driver outputs COL 0 to COL 101 37 to 138 LCD column driver outputs 7.1.3 ROW 50 to ROW 33 139 to 156 LCD row driver outputs The 2 supply rails VSS1 and VSS2 must be connected together. ROW 51 to ROW 64 159 to 172 LCD row driver outputs 7.1.4 VDD1 174 to 179 supply voltage 1 VDD3 180 supply voltage 3 VDD2 181 to 193 supply voltage 2 OSC 194 oscillator input SDIN 195 serial data input D/C 196 data/command input SCE 197 chip enable input (active LOW) If the internal voltage generator is not used then VDD2 and VDD3 must be connected to VDD1 or connected to power. T2 198 test 2 output 7.1.5 SCLK 199 serial clock input VSS2 200 to 213 negative power supply 2 VSS1 214 to 217 negative power supply 1 7.1.2 T1 218 test 1 input T5 219 test 5 input T4 220 test 4 input VSS1 T3 221 and 222 223 LCD supply voltage VLCDOUT 230 to 236 voltage multiplier output 237 voltage multiplier regulation input (VLCD) 16, 17, 157, 158 and 173 VSS1 AND VSS2: NEGATIVE POWER SUPPLY RAILS VDD1 TO VDD3: POSITIVE POWER SUPPLY RAILS VDD2 and VDD3 are the supply voltage for the internal voltage generator. Both have the same voltage and may be connected together outside of the chip. VDD1 is used as supply for the rest of the chip. VDD1 can be connected together with VDD2 and VDD3 but in this case care must be taken to respect the supply voltage range (see Chapter 13). VLCDIN: LCD POWER SUPPLY Positive power supply for the liquid crystal display. An external LCD supply voltage can be supplied using the VLCDIN pad. In this case VLCDOUT has to be left open-circuit and the internal voltage generator has to be programmed to zero. If the PCF8812 is in Power-down mode, the external LCD supply voltage has to be switched off. 7.1.6 test 3 input/output 224 to 229 VLCDSENSE These pads output the column signals. negative power supply 1 VLCDIN COL 0 TO COL 101 COLUMN DRIVER OUTPUTS VLCDOUT: LCD POWER SUPPLY Positive power supply for the liquid crystal display. If the internal voltage generator is used, the two supply rails VLCDIN and VLCDOUT must be connected together. If an external supply is used this pin must be left open-circuit. 7.1.7 dummy pads VLCDSENSE: VOLTAGE MULTIPLIER REGULATION (VLCD) INPUT VLCDSENSE is the input of the internal voltage multiplier regulation. If the internal voltage generator is used then VLCDSENSE must be connected to VLCDOUT. If a external supply voltage is used then the VLCDSENSE can be let open-circuit or connected to ground. 2000 Nov 22 5 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 7.1.8 PCF8812 8.2 T1 TO T5: TEST PADS The address counter assigns addresses to the display data RAM for writing. The X address X6 to X0 and the Y address Y3 to Y0 are set separately. After a write operation the address counter is automatically incremented by 1 according to the V flag (see Chapter 9). T1, T3, T4 and T5 must be connected to VSS, T2 must be left open-circuit. Not accessible to user. 7.1.9 SDIN: SERIAL DATA LINE Serial data input line. 7.1.10 8.3 SCLK: SERIAL CLOCK LINE D/C: MODE SELECT Input to select either command/address or data input. 7.1.12 Display Data RAM (DDRAM) The PCF8812 contains a 65 × 102 bit static RAM which stores the display data. The RAM is divided into 8 banks of 102 bytes (8 × 8 × 102 bits) and one bank of 102 bits (1 × 102 bits). During RAM access, data is transferred to the RAM via the serial interface. There is a direct correspondence between the X address and the column output number. Input for the clock signal 0 to 4.0 Mbits/s. 7.1.11 Address Counter (AC) SCE: CHIP ENABLE The enable pin allows data to be clocked in; the signal is active LOW. 8.4 7.1.13 The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data buses. OSC: OSCILLATOR When the on-chip oscillator is used this input must be connected to VDD. An external clock signal, if used, is connected to this input. If the oscillator and external clock are both inhibited by connecting the OSC pin to VSS the display is not clocked and may be left in a DC state. To avoid this the chip should always be put into Power-down mode before stopping the clock. 7.1.14 8.5 8.1 The display status (all dots on/off and normal/inverse video) is set by bits E and D in the command ‘display control’ (see Table 2). RES: RESET 8.6 LCD row and column drivers The PCF8812 contains 65 row and 102 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. Figure 2 shows typical waveforms. Unused outputs should be left unconnected. FUNCTIONAL DESCRIPTION Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD. An external clock signal, if used, is connected to this input. 2000 Nov 22 Display address counter The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. This signal will reset the device and must be applied to properly initialize the chip; the signal is active LOW. 8 Timing generator 6 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 frame n + 1 frame n ROW 0 R0 (t) ROW 1 R1 (t) COL 0 C0 (t) COL 1 C1 (t) Vstate1(t) Vstate2 (t) VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD − VSS V3 − VSS Vstate1(t) VLCD − V2 0V V3 − V2 V4 − V5 0V VSS − V5 V4 − VLCD VSS − VLCD VLCD − VSS V3 − VSS Vstate2 (t) VLCD − V2 0V V3 − V2 V4 − V5 0V VSS − V5 V4 − VLCD VSS − VLCD 0 1 2 3 4 5 6 7 8... ... 64 0 1 2 3 4 5 6 7 8... (1) Vstate1(t) = C1(t) − R0(t). (2) Vstate2(t) = C1(t) − R1(t). Fig.2 Typical LCD driver waveforms. 2000 Nov 22 7 ... 64 MGT637 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 DDRAM bank 0 top of LCD bank 1 bank 2 LCD bank 3 bank 7 bank 8 MGS395 Fig.3 DDRAM to display mapping. 2000 Nov 22 8 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 9 PCF8812 ADDRESSING Data is downloaded in bytes into the RAM matrix of the PCF8812 as indicated in Figs.3, 4, 5 and 6. The display RAM has a matrix of 65 × 102 bits. The columns are addressed by the address pointer. The address ranges are: X0 to X101 (1100101) and Y0 to Y8 (1000). Addresses outside of these ranges are not allowed. In vertical addressing mode (V = 1) the Y address increments after each byte (see Fig.6). After the last Y address (Y = 8) Y wraps around to 0 and X increments to address the next column. In horizontal addressing mode (V = 0) the X address increments after each byte (see Fig.5). After the last X address (X = 101) X wraps around to 0 and Y increments to address the next row. After the very last address (X = 101 and Y = 8) the address pointers wrap around to address (X = 0 and Y = 0). 9.1 Data structure handbook, full pagewidth MSB 0 LSB MSB 8 LSB 0 X address 101 Y address MGT638 Fig.4 RAM format addressing. handbook, full pagewidth 0 9 1 10 0 2 3 4 Y address 5 6 7 8 0 917 X address 101 8 MGS397 Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1). 2000 Nov 22 9 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 handbook, full pagewidth 0 1 2 102 103 104 204 205 206 306 307 308 408 409 410 510 511 512 612 613 614 714 715 716 816 817 818 0 0 Y address 917 X address 101 8 MGS396 Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0). • SDIN is sampled at the positive edge of SCLK 10 INSTRUCTIONS • D/C indicates whether the byte is a command (D/C = 0) or RAM data (D/C = 1). It is read with the eighth SCLK pulse The instruction format is divided into two modes: If D/C (mode select) is set LOW the current byte is interpreted as command byte (see Table 1). Figure 8 shows an example of a serial data stream for initializing the chip. If D/C is set HIGH the following bytes are stored in the display data RAM. After every data byte the address counter is incremented automatically. The level of the D/C signal is read during the last bit of the data byte. Every instruction can be sent in any order to the PCF8812. The MSB of a byte is transmitted first. Figure 8 shows one possible command stream, used to set-up the LCD driver. The serial interface is initialized when SCE is HIGH. In this state SCLK clock pulses have no effect and no power is consumed by the serial interface. A negative edge on SCE enables the serial interface and indicates the start of a data transmission. • If SCE stays LOW after the last bit of a command/data byte, the serial interface expects DB7 of the next byte at the next positive edge of SCLK (see Fig.12). If SCLK goes LOW after the last data bit (DB0), either: – A rising clock edge is required to latch the last data bit – Or the last bit is latched when SCE goes HIGH. • A reset pulse with RES interrupts the transmission. No data is written into the RAM. The registers are cleared. If SCE is LOW after the positive edge of RES, the serial interface is ready to receive bit 7 of a command/data byte (see Fig.12). Figures 9 and 10 show the serial bus protocol: • When SCE is HIGH, SCLK clocks are ignored. During the HIGH time of SCE the serial interface is initialized (see Fig.12) 2000 Nov 22 10 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver MSB (DB7) handbook, halfpage PCF8812 LSB (DB0) data data MGT639 Fig.7 General format of data stream. handbook, full pagewidth function set (H = 1) bias system set VOP temperature control function set (H = 0) display control Y address X address MGT640 Fig.8 Example of serial data stream. handbook, full pagewidth SCE D/C SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MGT641 Fig.9 Serial bus protocol transmission of one byte. 2000 Nov 22 11 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 handbook, full pagewidth SCE D/C SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 MGT642 Fig.10 Serial bus protocol transmission of several bytes. handbook, full pagewidth SCE D/C RES SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 MGT643 Fig.11 Serial bus reset function (SCE). handbook, full pagewidth SCE RES D/C SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 MGT644 Fig.12 Serial bus reset function (RES). 2000 Nov 22 12 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver Table 1 PCF8812 Instruction set COMMAND BYTE INSTRUCTION D/C DESCRIPTION DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (H = 0 or 1) NOP 0 0 0 0 0 0 0 0 0 no operation Function set 0 0 0 1 0 0 PD V H power-down control; entry mode; extended instruction set control (H) Write data 1 D7 D6 D5 D4 D3 D2 D1 D0 writes data to display RAM Reserved 0 0 0 0 0 0 1 X X do not use Display control 0 0 0 0 0 1 D 0 E sets display configuration Set higher or lower programming range Vop 0 0 0 0 1 0 0 0 Set Y address of RAM 0 0 1 0 0 Y3 Y2 Y1 Y0 sets Y address of RAM; 0≤Y≤8 Set X address of RAM 0 1 X6 X5 X4 X3 X2 X1 X0 sets X address part of RAM; 0 ≤ X ≤ 101 Reserved 0 0 0 0 0 0 0 0 1 do not use Reserved 0 0 0 0 0 0 0 1 X do not use Temperature control 0 0 0 0 0 0 1 TC1 TC0 HV-gen stages 0 0 0 0 0 1 0 S1 S0 Bias system 0 0 0 0 1 0 BS2 BS1 BS0 1 X X X X X X (H = 0) PRS VLCD programming range select (H = 1) Reserved 0 0 Set Vop 0 1 2000 Nov 22 set temperature coefficient (TCx) # of HV-gen voltage multiplication set bias system (BSx) do not use (reserved for test) VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 write VOP to register 13 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver Table 2 PCF8812 Explanations for symbols in Table 1 BIT 0 1 RESET STATE PD chip is active chip is in Power-down mode 1 V horizontal addressing vertical addressing 0 H use basic instruction set use extended instruction set 0 PRS VLCD programming range; LOW VLCD programming range; HIGH 0 D, E TC1 to TC0 S1 to S0 00 display blank 10 normal mode 01 all display segments on 11 inverse video mode 00 VLCD temperature coefficient 0 01 VLCD temperature coefficient 1 10 VLCD temperature coefficient 2 11 VLCD temperature coefficient 3 00 2 × voltage multiplier 01 3 × voltage multiplier 10 4 × voltage multiplier 11 5 × voltage multiplier D=0 E=0 TC1 to TC0 = 00 S1 to S0 = 00 VOP 6 to VOP0 VLCD programming VOP 6 to VOP0 = 0000000 BS2 to BS0 bias system BS2 to BS0 = 000 10.1 • Horizontal addressing (V = 0) Initialization • Normal instruction set (H = 0) Immediately following power-on, all internal registers as well as the RAM content are undefined; a reset pulse must be applied. • Display blank (E = D = 0) • Address counter X6 to X0 = 0; Y3 to Y0 = 0 • Temperature control mode (TC1 to TC0 = 0) Reset is accomplished by applying an external reset pulse (active LOW) at the pad RES. When reset occurs within the specified time, all internal registers are reset, however the RAM is still undefined. The state after reset is described in Section 10.2. • Bias system (BS2 to BS0 = 0) • VLCD is equal to 0; the HV-generator is switched off (VOP6 to VOP0 = 0 and PRS = 0) • After power-on; RAM data is undefined; the reset signal doesn’t change the content of the RAM The RES input must be ≤0.3VDD when VDD reaches VDD(min) (or higher) within a maximal time tVHRL after VDD going HIGH (see Fig.16). 10.2 • All LCD outputs at VSS (display off). Reset function After reset the LCD driver has the following state: • Power-down mode (PD = 1) 2000 Nov 22 14 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 10.3 PCF8812 Function set 10.3.1 10.3.3 PD H When H = 0 the commands ‘display control’, ‘set Y address’, ‘set X address’ and set the PRS bit (low or high range of the high voltage generator) can be performed, when H = 1 the others can be executed. The commands ‘write data’ and ‘function set’ can be executed in both cases. • All LCD outputs at VSS (display off) • Bias generator and VLCD generator off; VLCD can be disconnected • Oscillator off (external clock possible) • Serial bus; command; etc. function 10.4 • RAM contents not cleared; RAM data can be written 10.4.1 • VLCD discharged to VSS in Power-down mode. Display control D AND E The bits D and E select the display mode (see Table 2). 10.3.2 V 10.5 When V = 0, the horizontal addressing is selected. The data is written into the DDRAM as shown in Fig.5. When V = 1, the vertical addressing is selected. The data is written into the DDRAM as shown in Fig.6. Table 3 Set Y address of RAM Y3 to Y0 defines the Y address vector address of the display RAM (see Table 3). X/Y address range: note 1 Y3 Y2 Y1 Y0 0 0 0 0 bank 0 (display RAM) 0 to 101 0 0 0 1 bank 1 (display RAM) 0 to 101 0 0 1 0 bank 2 (display RAM) 0 to 101 0 0 1 1 bank 3 (display RAM) 0 to 101 0 1 0 0 bank 4 (display RAM) 0 to 101 0 1 0 1 bank 5 (display RAM) 0 to 101 0 1 1 0 bank 6 (display RAM) 0 to 101 0 1 1 1 bank 7 (display RAM) 0 to 101 1 0 0 0 bank 8 (display RAM) 0 to 101 CONTENT ALLOWED X RANGE Note 1. In bank 8 only the LSB is accessed. 10.6 Set X address of RAM The X address points to the columns. The range of X is 0 to 101 (65H). 10.7 Set HV-generator stages The PCF8812 incorporates a software configurable voltage multiplier. After reset (RES) the voltage multiplier is set to 2 × VDD2. Other voltage multiplier factors are set via the command ‘Set HV-gen stages’ (see Tables 1 and 2). 2000 Nov 22 15 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 10.8 PCF8812 Bias system 1 The bias voltage levels are set in the ratio of R - R - nR - R - R giving a ----------------- bias system. Different multiplex rates (n + 4) require different factors ‘n’ (see Table 4). This is programmed by BS2 to BS0. For MUX1 to MUX65 the optimum bias 65 – 3 = 5.062 = 5 resulting in 1/9 bias. value ‘n’ is given by: n = Table 4 Table 5 Programming the required bias system BS2 BS1 BS0 n RECOMMEND MUX RATE 0 0 0 7 1 to 100 0 0 1 6 1 to 80 0 1 0 5 1 to 65 or 1 to 65 0 1 1 4 1 to 48 1 0 0 3 1 to 40 or 1 to 34 1 0 1 2 1 to 24 1 1 0 1 1 to 18 or 1 to 16 1 1 1 0 1 to 10 or 1 to 9 or 1 to 8 LCD bias voltage SYMBOL BIAS VOLTAGES FOR n = 5 (1/9 BIAS) BIAS VOLTAGES V1 VLCD VLCD V2 (n + 3) ----------------(n + 4) 8/ 9 × VLCD V3 (n + 2) ----------------(n + 4) 7/ 9 × VLCD V4 2 ----------------(n + 4) 2/ 9 × VLCD V5 1 ----------------(n + 4) 1/ 9 × VLCD V6 VSS VSS 2000 Nov 22 16 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 10.9 PCF8812 The parameters are explained in Table 6. The maximum voltage that can be generated is dependent on the VDD2 voltage and the display load current. Two overlapping VLCD ranges are selectable via the command ‘HV-gen control’. For the LOW (PRS = 0) range a = a1 and for the HIGH (PRS = 1) range a = a2 with steps equal to ‘b’ in both ranges. It should be noted that the charge pump is turned off if VOP 6 to 0 and the bit PRS are all set to zero (see Fig.14). Temperature control Due to the temperature dependency of the liquid crystals viscosity the LCD controlling voltage VLCD must be increased with lower temperature to maintain optimum contrast. There are 4 different temperature coefficients available in the PCF8812 (see Fig.13). The coefficients are selected by bits TC1 to TC0. Table 6 shows the typical values of the different temperature coefficients. The coefficients are proportional to the programmed VLCD. For MUX 1 to 65 the optimum operating voltage of the liquid can be calculated as follows; 1 + 65 V LCD = --------------------------------------- × V th = 6.85 × V th 1 2 × 1 – ---------- 65 MGS402 handbook, halfpage VLCD (3) where Vth is the threshold voltage of the liquid crystal material used. Table 6 Tcut Typical values for parameters for the HV-generator programming SYMBOL T Fig.13 Temperature coefficients. VALUE UNIT a1 2.94 (PRS = 0) V a2 6.75 (PRS = 1) V b 0.03 V Tcut 27 °C 10.10 Set VOP value As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD (9 V) the user has to ensure, while setting the VOP register and selecting the Temperature Compensation (TC), that under all conditions and including all tolerances that VLCD remains below 9 V. The operating voltage VLCD can be set by software. The generated voltage is dependent on temperature, programmed Temperature Coefficient (TC) and the programmed voltage at reference temperature (Tcut). V LCD ( T ) = ( a + V OP × b ) ( 1 + ( T – T cut ) × TC ) (1) The voltage at reference temperature [VLCD(T = Tcut)] can be calculated as follows: (2) V LCD ( T = T ) = ( a + V OP × b ) cut 2000 Nov 22 17 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 handbook, full pagewidth VLCD a1 charge pump off b a2 a1+b 0H 01H 02H 03H 04H 05H 06H . . . 5FH 6FH 7FH 00H 01H 02H 03H 04H 05H 06H . . . 5FH 6FH 7FH LOW (PRS = 0) HIGH (PRS = 1) MGS658 VOP 6 to 0 (programmed) [00H to 7FH; programming range LOW and HIGH]. Fig.14 VOP programming of PCF8812 (at T = Tcut). 2000 Nov 22 18 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 11 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); see notes 1 and 2 SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD1 supply voltage −0.5 +6.5 V VDD2,VDD3 supply voltage for internal voltage generator −0.5 +4.5 V VLCD supply voltage range LCD −0.5 +9.0 V Vi all input voltages −0.5 VDD + 0.5 V ISS ground supply current −50 +50 mA Ii,Io DC input or output current −10 +10 mA Ptot total power dissipation − 300 mW PO power dissipation per output − 30 mW Tstg storage temperature −65 +150 °C Ves electrostatic handling voltage note 3 − ±1900 V note 4 − ±200 V Notes 1. Stresses above those listed under limiting values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are referenced to VSS unless otherwise specified. 3. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor. 4. Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 µH series inductor. 12 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”). 2000 Nov 22 19 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 13 DC CHARACTERISTICS VDD = 2.5 to 5.5 V; VSS = 0 V; VLCD = 4.5 to 9.0 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD1 supply voltage +2.5 − +5.5 V VDD2,VDD3 supply voltage for internal voltage generator LCD voltage internally generated (voltage generator enabled) +2.5 − +4.5 V VLCDIN LCD input supply voltage LCD voltage externally supplied (voltage generator disabled) +4.5 − +9.0 V VLCDOUT LCD output supply voltage LCD voltage internally generated (voltage generator enabled); note 1 +4.5 − +9.0 V IDD(tot) total supply current normal mode; VDD1 = 2.8 V; VLCD = 7.6 V; fSCLK = 0; Tamb = 25 °C; no display load; 4 × charge pump; notes 2 and 3 − 220 350 µA Power-down mode; with internal or external VLCD supply voltage; note 4 − 1.5 − µA VDD1 = 2.8 V; VLCD = 7.6 V; fSCLK = 0; T = 25 °C; no display load; notes 2, 3 and 5 − 30 − µA ILCDIN supply current from external VLCD Logic VIL LOW-level input voltage VSS − 0.3VDD V VIH HIGH-level input voltage 0.7VDD − VDD V IIL input leakage current VI = VDD1 or VSS1 −1 − +1 µA Column and row outputs Rcol column output resistance COL 0 to COL 101 IL = 10 µA outputs tested one at a time − 12 20 kΩ Rrow row output resistance ROW 0 to ROW 64 IL = 10 µA outputs tested one at a time − 12 20 kΩ Vbias(col) column bias tolerance COL 0 to COL 101 −100 0 +100 mV Vbias(row) row bias tolerance ROW 0 to ROW 64 −100 0 +100 mV 2000 Nov 22 20 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver SYMBOL PARAMETER PCF8812 CONDITIONS MIN. TYP. MAX. UNIT LCD supply voltage generator −300 0 +300 mV coefficient 0 − 0 × 10−3 − 1/°C coefficient 1 − −0.76 × 10−3 − 1/°C − −1.05 × 10−3 − 1/°C −2.10 × 10−3 − 1/°C VLCD VLCD tolerance internally generated VDD1 = 2.8 V; VLCD = 7.6 V; fSCLK = 0; Tamb = 25 °C; display-load = 10 µA; notes 3, 6 and 7 TC VLCD temperature coefficient VDD1 = 2.8 V; fSCLK = 0; Tamb = −20 to +70 °C; display load = 10 µA; note 3 coefficient 2 coefficient 3 − Notes 1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Internal clock. 3. fSCLK = 0 means no serial clock. 4. During power-down all static currents are switched off. 5. If external VLCD; the display load current is not transmitted to IDD. 6. Tolerance depend on the temperature; (typical null at Tamb = 27 °C, maximum tolerance values are measured at the temperate range limit, maximum tolerance is proportional to VLCD). 7. For TC1 to TC3. 14 AC CHARACTERISTICS VDD = 2.5 to 5.5 V; VSS = 0 V; VLCD = 4.5 to 9.0 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER fOSC oscillator frequency fclk(ext) external clock frequency fframe frame frequency tVHRL tRW CONDITIONS VDD1 = 2.8 V; Tamb = −20 to +70 °C MIN. TYP. MAX. UNIT 22 38 67 kHz 20 38 67 kHz fOSC or fclk(ext) = 38 kHz; note 1 − 73 − Hz VDD to RES LOW see Fig.16 0 − 1 µs RES LOW pulse width see Fig.16 500 − − ns VDD1 = 3.0 V ±10%; all signal timing is based on 20% to 80% of VDD and a maximum rise and fall time of 10 ns 0 − 4.00 MHz Serial bus timing characteristics fSCLK clock frequency tcyc clock cycle time 250 − − ns tPWH1 SCLK pulse width HIGH 100 − − ns tPWL1 SCLK pulse width LOW 100 − − ns tS2 SCE set-up time 60 − − ns 2000 Nov 22 21 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver SYMBOL PARAMETER tH2 SCE hold time tPWH2 SCE minimum HIGH time tH5 SCE start hold time tS3 PCF8812 CONDITIONS MIN. TYP. MAX. UNIT 100 − − ns 100 − − ns 100 − − ns D/C set-up time 100 − − ns tH3 D/C hold time 100 − − ns tS4 SDIN set-up time 100 − − ns tH4 SDIN hold time 100 − − ns note 2 Notes 1. f clk(ext) f frame = --------------520 2. tH5 is the time from the previous SCLK positive edge (irrespective of the state of SCE) to the negative edge of SCE (see Fig.15). 15 SERIAL INTERFACE handbook, full pagewidth t S2 t H2 t PWH2 SCE t S3 t H3 t H5 (t H5 ) D/C t CYC t PWL1 t S2 t PWH1 SCLK t S4 t H4 SDIN MGT645 Fig.15 Serial interface timing. 2000 Nov 22 22 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 16 RESET handbook, full pagewidth VDD t RW t RW RES VDD t VHRL t RW t RW RES MGT646 Fig.16 Reset timing. 17 APPLICATION INFORMATION Table 7 Programming example for PCF8812 SERIAL BUS BYTE STEP DISPLAY OPERATION D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SCE is going low 1 start 2 0 0 0 1 0 0 0 0 1 function set; PD = 0, V = 0; select extended instruction set (H = 1 mode) 3 0 0 0 0 1 0 0 0 1 set charge pump range HIGH PRS = 1 4 0 1 0 0 1 1 1 0 0 set VOP; VOP is set to 7.6 V 5 0 0 0 1 0 0 0 0 0 function set; PD = 0; V = 0; select normal instruction set (H = 0 mode) 6 0 0 0 0 0 1 1 0 0 display control; set normal mode (D = 1; E = 0). 7 1 1 1 1 1 1 0 0 0 data write; Y and X are initialized to 0 by default, so they aren’t set here MGS405 2000 Nov 22 23 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 SERIAL BUS BYTE STEP DISPLAY OPERATION D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 8 1 1 0 1 0 0 0 0 0 data write MGS406 9 1 1 1 1 0 0 0 0 0 data write MGS407 10 1 0 0 0 0 0 0 0 0 data write MGS407 11 1 1 1 1 1 1 0 0 0 data write MGS409 12 1 0 0 1 0 0 0 0 0 data write MGS410 13 1 1 1 1 1 1 0 0 0 data write MGS411 2000 Nov 22 24 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 SERIAL BUS BYTE STEP DISPLAY OPERATION D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 14 0 0 0 0 0 1 1 0 1 display control; set inverse video mode (D = 1; E = 1) MGS412 15 0 1 0 0 0 0 0 0 0 set X-address of RAM; set address to 0000000 MGS412 16 1 0 0 0 0 0 0 0 0 data write MGS414 The pinning of the PCF8812 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 65 × 102 pixels. 2000 Nov 22 25 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 handbook, full pagewidth DISPLAY 102 × 65 33 VSS2 VSS1 VDD1 VDD3 VDD2 PCF8812 RES 102 VLCDIN VLCDOUT VLCDSENSE 32 4 (1) CVLCD I/O CVDD VDD VSS reset MGT647 Fig.17 Application diagram; internal charge pump is used and a single VDD. handbook, full pagewidth DISPLAY 102 × 65 33 VSS2 VSS1 VDD1 VDD3 VDD2 PCF8812 RES 102 VLCDIN VLCDOUT VLCDSENSE 32 4 (1) VDD2 I/O CVDD2 CVLCD reset CVDD1 VDD1 VSS MGT648 Fig.18 Application diagram; internal charge pump is used and two separate VDD (VDD1 and VDD2). 2000 Nov 22 26 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 handbook, full pagewidth DISPLAY 102 × 65 VSS2 VSS1 VDD1 VDD3 VDD2 PCF8812 33 RES 102 VLCDIN VLCDOUT VLCDSENSE 32 4 (1) CVDD I/O VSS VLCDIN VDD reset MGT649 Fig.19 Application diagram; external high voltage generation is used. The required minimum value for the external capacitors in an application with the PCF8812 are as follows: CVLCD = 100 nF (minimum) CVDD; CVDD1; CVDD2 = 1 µF (minimum). Higher capacitor values are recommended for ripple reduction. 18 CHIP INFORMATION The PCF8812 is manufactured in n-well CMOS technology. The substrate is at VSS potential. 19 PAD INFORMATION Table 8 Bonding pad dimensions NAME DIMENSION Pad pitch 70 µm Pad size; aluminium 62 × 100 µm Bump dimensions 50 × 90 × 17.5 µm (±5) Wafer thickness; including bumps maximum 430 µm Wafer thickness; without bumps 381 µm typ. 2000 Nov 22 27 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 20 BONDING PAD LOCATION COORDINATES SYMBOL Table 9 Bonding pad location All x and y coordinates are referenced to the centre of the chip (dimensions in µm; see Fig.20). COORDINATES SYMBOL PAD x y PAD x y COL 0 37 +3605 −934.6 COL 1 38 +3535 −934.6 COL 2 39 +3465 −934.6 COL 3 40 +3395 −934.6 RES 1 +3870 +934.6 COL 4 41 +3325 −934.6 ROW 32 2 +4270 +934.6 COL 5 42 +3255 −934.6 ROW 31 3 +4340 +934.6 COL 6 43 +3185 −934.6 ROW 30 4 +4410 +934.6 COL 7 44 +3115 −934.6 ROW 29 5 +4480 +934.6 COL 8 45 +3045 −934.6 ROW 28 6 +4550 +934.6 COL 9 46 +2975 −934.6 ROW 27 7 +4620 +934.6 COL 10 47 +2905 −934.6 ROW 26 8 +4690 +934.6 COL 11 48 +2835 −934.6 ROW 25 9 +4760 +934.6 COL 12 49 +2765 −934.6 ROW 24 10 +4830 +934.6 COL 13 50 +2695 −934.6 ROW 23 11 +4900 +934.6 COL 14 51 +2625 −934.6 ROW 22 12 +4970 +934.6 COL 15 52 +2555 −934.6 ROW 21 13 +5040 +934.6 COL 16 53 +2485 −934.6 ROW 20 14 +5110 +934.6 COL 17 54 +2415 −934.6 ROW 19 15 +5180 +934.6 COL 18 55 +2345 −934.6 dummy pad 16 +5320 +934.6 56 +2275 −934.6 17 +5355 −934.6 COL 19 dummy pad 57 +2205 −934.6 ROW 0 18 +5005 −934.6 COL 20 58 +2135 −934.6 19 +4935 −934.6 COL 21 ROW 1 59 +2065 −934.6 20 +4865 −934.6 COL 22 ROW 2 60 +1995 −934.6 ROW 3 21 +4795 −934.6 COL 23 61 +1925 −934.6 22 +4725 −934.6 COL 24 ROW 4 62 +1785 −934.6 23 +4655 −934.6 COL 25 ROW 5 63 +1715 −934.6 ROW 6 24 +4585 −934.6 COL 26 64 +1645 −934.6 25 +4515 −934.6 COL 27 ROW 7 65 +1575 −934.6 26 +4445 −934.6 COL 28 ROW 8 66 +1505 −934.6 ROW 9 27 +4375 −934.6 COL 29 67 +1435 −934.6 28 +4305 −934.6 COL 30 ROW 10 68 +1365 −934.6 29 +4235 −934.6 COL 31 ROW 11 69 +1295 −934.6 30 +4165 −934.6 COL 32 ROW 12 70 +1225 −934.6 ROW 13 31 +4095 −934.6 COL 33 71 +1155 −934.6 32 +4025 −934.6 COL 34 ROW 14 72 +1085 −934.6 33 +3955 −934.6 COL 35 ROW 15 73 +1015 −934.6 ROW 16 34 +3885 −934.6 COL 36 74 +945 −934.6 35 +3815 −934.6 COL 37 ROW 17 75 +875 −934.6 36 +3745 −934.6 COL 38 ROW 18 2000 Nov 22 28 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 COORDINATES SYMBOL COORDINATES PAD SYMBOL x y PAD x y COL 39 76 +805 −934.6 COL 78 115 −2065 −934.6 COL 40 77 +735 −934.6 COL 79 116 −2135 −934.6 COL 41 78 +665 −934.6 COL 80 117 −2205 −934.6 COL 42 79 +595 −934.6 COL 81 118 −2275 −934.6 COL 43 80 +525 −934.6 COL 82 119 −2345 −934.6 COL 44 81 +455 −934.6 COL 83 120 −2415 −934.6 COL 45 82 +385 −934.6 COL 84 121 −2485 −934.6 COL 46 83 +315 −934.6 COL 85 122 −2555 −934.6 COL 47 84 +245 −934.6 COL 86 123 −2625 −934.6 COL 48 85 +175 −934.6 COL 87 124 −2695 −934.6 COL 49 86 +105 −934.6 COL 88 125 −2765 −934.6 COL 50 87 −35 −934.6 COL 89 126 −2835 −934.6 COL 51 88 −105 −934.6 COL 90 127 −2905 −934.6 COL 52 89 −175 −934.6 COL 91 128 −2975 −934.6 COL 53 90 −245 −934.6 COL 92 129 −3045 −934.6 COL 54 91 −315 −934.6 COL 93 130 −3115 −934.6 COL 55 92 −385 −934.6 COL 94 131 −3185 −934.6 COL 56 93 −455 −934.6 COL 95 132 −3255 −934.6 COL 57 94 −525 −934.6 COL 96 133 −3325 −934.6 COL 58 95 −595 −934.6 COL 97 134 −3395 −934.6 COL 59 96 −665 −934.6 COL 98 135 −3465 −934.6 COL 60 97 −735 −934.6 COL 99 136 −3535 −934.6 COL 61 98 −805 −934.6 COL 100 137 −3605 −934.6 COL 62 99 −875 −934.6 COL 101 138 −3675 −934.6 COL 63 100 −945 −934.6 ROW 50 139 −3815 −934.6 COL 64 101 −1015 −934.6 ROW 49 140 −3885 −934.6 COL 65 102 −1085 −934.6 ROW 48 141 −3955 −934.6 COL 66 103 −1155 −934.6 ROW 47 142 −4025 −934.6 COL 67 104 −1225 −934.6 ROW 46 143 −4095 −934.6 COL 68 105 −1295 −934.6 ROW 45 144 −4165 −934.6 COL 69 106 −1365 −934.6 ROW 44 145 −4235 −934.6 COL 70 107 −1435 −934.6 ROW 43 146 −4305 −934.6 COL 71 108 −1505 −934.6 ROW 42 147 −4375 −934.6 COL 72 109 −1575 −934.6 ROW 41 148 −4445 −934.6 COL 73 110 −1645 −934.6 ROW 40 149 −4515 −934.6 COL 74 111 −1715 −934.6 ROW 39 150 −4585 −934.6 COL 75 112 −1785 −934.6 ROW 38 151 −4655 −934.6 COL 76 113 −1925 −934.6 ROW 37 152 −4725 −934.6 COL 77 114 −1995 −934.6 ROW 36 153 −4795 −934.6 2000 Nov 22 29 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 COORDINATES SYMBOL COORDINATES PAD SYMBOL x PAD y x y ROW 35 154 −4865 −934.6 VDD2 193 −2130 +934.6 ROW 34 155 −4935 −934.6 OSC 194 −1890 +934.6 ROW 33 156 −5005 −934.6 SDIN 195 −1650 +934.6 dummy pad 157 −5355 −934.6 D/C 196 −1410 +934.6 dummy pad 158 −5320 +934.6 SCE 197 −1170 +934.6 ROW 51 159 −5180 +934.6 T2 198 −930 +934.6 ROW 52 160 −5110 +934.6 SCLK 199 −690 +934.6 ROW 53 161 −5040 +934.6 VSS2 200 −530 +934.6 ROW 54 162 −4970 +934.6 VSS2 201 −450 +934.6 ROW 55 163 −4900 +934.6 VSS2 202 −370 +934.6 ROW 56 164 −4830 +934.6 VSS2 203 −290 +934.6 ROW 57 165 −4760 +934.6 VSS2 204 −210 +934.6 ROW 58 166 −4690 +934.6 VSS2 205 −130 +934.6 ROW 59 167 −4620 +934.6 VSS2 206 −50 +934.6 ROW 60 168 −4550 +934.6 VSS2 207 +30 +934.6 ROW 61 169 −4480 +934.6 VSS2 208 +110 +934.6 ROW 62 170 −4410 +934.6 VSS2 209 +190 +934.6 ROW 63 171 −4340 +934.6 VSS2 210 +270 +934.6 ROW 64 172 −4270 +934.6 VSS2 211 +350 +934.6 dummy pad 173 −4050 +934.6 VSS2 212 +430 +934.6 VDD1 174 −3890 +934.6 VSS2 213 +510 +934.6 VDD1 175 −3810 +934.6 VSS1 214 +670 +934.6 VDD1 176 −3730 +934.6 VSS1 215 +750 +934.6 VDD1 177 −3650 +934.6 VSS1 216 +830 +934.6 VDD1 178 −3570 +934.6 VSS1 217 +910 +934.6 VDD1 179 −3490 +934.6 T1 218 +1150 +934.6 VDD3 180 −3250 +934.6 T5 219 +1630 +934.6 VDD2 181 −3090 +934.6 T4 220 +2030 +934.6 VDD2 182 −3010 +934.6 VSS1 221 +2110 +934.6 VDD2 183 −2930 +934.6 VSS1 222 +2190 +934.6 VDD2 184 −2850 +934.6 T3 223 +2270 +934.6 VDD2 185 −2770 +934.6 VLCDIN 224 +2510 +934.6 VDD2 186 −2690 +934.6 VLCDIN 225 +2590 +934.6 VDD2 187 −2610 +934.6 VLCDIN 226 +2670 +934.6 VDD2 188 −2530 +934.6 VLCDIN 227 +2750 +934.6 VDD2 189 −2450 +934.6 VLCDIN 228 +2830 +934.6 VDD2 190 −2370 +934.6 VLCDIN 229 +2910 +934.6 VDD2 191 −2290 +934.6 VLCDOUT 230 +3070 +934.6 VDD2 192 −2210 +934.6 VLCDOUT 231 +3150 +934.6 2000 Nov 22 30 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 COORDINATES SYMBOL PAD x y VLCDOUT 232 +3230 +934.6 VLCDOUT 233 +3310 +934.6 VLCDOUT 234 +3390 +934.6 VLCDOUT 235 +3470 +934.6 VLCDOUT 236 +3550 +934.6 VLCDSENSE 237 +3630 +934.6 Circle 1 +5185 −910.8 Circle 2 −5185 −910.8 Circle 3 −4160 +909.7 Circle 4 +4160 +909.7 Alignment marks 2000 Nov 22 31 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... dummy pad ROW 19 alignment mark ROW 0 COL 0 ROW 18 COL 25 COL 50 COL 76 dummy pad ROW 32 RES pad No.1 alignment mark VLCDSENSE VLCDOUT VLCDIN T4 VSS1 T3 T5 T1 VSS1 VSS2 SCLK T2 SCE D/C SDIN OSC VDD2 VDD3 VDD1 dummy pad ROW 64 alignment mark ROW 50 COL 101 . .. . .. . .. . .. . .. ROW 33 dummy pad ROW 51 alignment mark PC8812-1 . .. dummy pad Philips Semiconductors . .. x . .. . .. . .. 32 0,0 65 × 102 pixels matrix LCD driver andbook, full pagewidth 2000 Nov 22 y MGT653 Product specification Fig.20 Bonding pad locations. PCF8812 (1) The alignment marks are circular with a diameter of 100 µm. (2) Maximum chip size: 2.1 × 10.9 mm. Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 21 DEVICE PROTECTION DIAGRAM VDD1 VDD3 VLCDIN VLCDOUT VLCDSENSE handbook, full pagewidth VDD1 T3, T2 VSS1 VSS1 VDD2 VSS1 VSS1 VSS2 VSS2 VSS2 VSS1 COL 0-101/ROW 0-64 VDD1 SDIN SCLK SCE D/C OSC RES T1, T4, T5 VLCDIN 1 per block VSS1 VSS1 VSS1 MGT650 Fig.21 Device protection diagram. 2000 Nov 22 33 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 22 TRAY INFORMATION handbook, full pagewidth A x G C H y 1,1 2,1 1,2 2,2 x,1 3,1 D B 1,3 F x,y 1,y A ,,,,,,, ,,,,,,, A E K L M SECTION A-A J MGT651 Fig.22 Tray details. Table 10 Tray dimensions DIMENSION handbook, halfpage PC8812 MGT652 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface. Fig.23 Tray alignment. 2000 Nov 22 34 DESCRIPTION VALUE A pocket pitch; x direction 13.77 mm B pocket pitch; y direction 4.37 mm C pocket width; x direction 11.04 mm D pocket width; y direction 2.24 mm E tray width; x direction 50.8 mm F tray width; y direction 50.8 mm G distance from cut corner to pocket (1 and 1) centre 11.68 mm H distance from cut corner to pocket (1 and 1) centre 5.74 mm J tray thickness 3.96 mm K tray cross section 1.78 mm L tray cross section 2.49 mm M pocket depth 0.89 mm x no. pockets in x direction 3 y no. pockets in y direction 10 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 23 DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 24 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 25 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. 2000 Nov 22 35 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260, Tel. +66 2 361 7910, Fax. +66 2 398 3447 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com SCA 70 © Philips Electronics N.V. 2000 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403512/01/pp36 Date of release: 2000 Nov 22 Document order number: 9397 750 07415