2SK1772 Silicon N Channel MOS FET REJ03G0971-0200 (Previous: ADE-208-1318) Rev.2.00 Sep 07, 2005 Application High speed power switching Features • • • • • Low on-resistance High speed switching Low drive current 4 V gate drive device can be driven from 5 V source. Suitable for DC-DC converter, motor drive, power switch, solenoid drive Outline RENESAS Package code: PLZZ0004CA-A (Package name: UPAK R ) 3 D 2 1 1. Gate 2. Drain 3. Source 4. Drain G 4 S Note: Marking is "HY". *UPAK is a trademark of Renesas Technology Corp. Rev.2.00 Sep 07, 2005 page 1 of 6 2SK1772 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Symbol VDSS Ratings 30 Unit V VGSS ID ±20 1 V A 2 1 A A ID(pulse) IDR *1 *2 Channel dissipation Channel temperature Pch Tch 1 150 Storage temperature Tstg Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1 % 2. When using the alumina ceramic board (12.5 × 20 × 0.7mm) –55 to +150 W °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Symbol V(BR)DSS Min 30 Typ — Max — Unit V Gate to source breakdown voltage Gate to source leak current V(BR)GSS IGSS ±20 — — — — ±10 V µA IG = ±100 µA, VDS = 0 VGS = ±16 V, VDS = 0 Zero gate voltage drain current Gate to source cutoff voltage IDSS VGS(off) — 1.0 — — 50 2.0 µA V VDS = 25 V, VGS = 0 ID = 1 mA, VDS = 10 V Static drain to source on state resistance RDS(on) — — 0.4 0.6 0.6 0.85 Ω Ω ID = 0.5 A, VGS = 10 V* 3 ID = 0.5 A, VGS = 4 V* Forward transfer admittance Input capacitance |yfs| Ciss 0.6 — 1.0 85 — — S pF Output capacitance Reverse transfer capacitance Coss Crss — — 65 20 — — pF pF ID = 0.5 A, VDS = 10 V* VDS = 10 V, VGS = 0, f = 1 MHz Turn-on delay time Rise time td(on) tr — — 10 15 — — ns ns Turn-off delay time Fall time td(off) tf — — 40 30 — — ns ns Body to drain diode forward voltage Body to drain diode reverse recovery time VDF trr — — 1.2 30 — — V ns Note: 3. Pulse Test Rev.2.00 Sep 07, 2005 page 2 of 6 Test Conditions ID = 10 mA, VGS = 0 3 3 ID = 0.5 A, VGS = 10 V, 3 RL = 60 Ω* 3 IF = 1 A, VGS = 0* IF = 1 A, VGS = 0, 3 diF/dt = 50 A/µs* 2SK1772 Maximum Channel Power Dissipation Curve Maximum Safe Operation Area 1.6 ID (A) 10 1.2 Operation in this area is limited by RDS(on) 3 PW = 100 µs 0.8 0.4 50 0 100 150 Ambient Temperature C ra Drain Current s s n 0.03 3 10 30 100 VDS (V) 1.0 VDS = 10 V Pulse test ID (A) Pulse test 1.2 m Typical Transfer Characteristics 5V 1.6 1 m Drain to Source Voltage 3.5 V 4V = tio 0.1 Ta (°C) 0.8 0.6 3.0 V Drain Current ID (A) 10 V 10 pe 0.3 Typical Output Characteristics 2.0 = O 0.01 Ta = 25°C 0.1 0.3 1 200 PW PW 1 D Drain Current Channel Power Dissipation Pch** (W) (** on the almina ceramic board) Main Characteristics 0.8 2.5 V 0.4 75°C 0.4 Tc = 25°C –25°C 0.2 VGS = 2 V 0 1 2 3 4 VDS 0 (V) Pulse test 1.6 1.2 2A 0.8 1A 0.4 I D = 0.5 A 0 2 4 6 Gate to Source Voltage Rev.2.00 Sep 07, 2005 page 3 of 6 8 VGS 10 (V) 2 3 4 VGS 5 (V) Static Drain to Source on State Resistance vs. Drain Current Drain to Source Saturation Voltage vs. Gate to Source Voltage 2.0 1 Gate to Source Voltage Static Drain to Source on State Resistance RDS(on) (Ω) Drain to Source Saturation Voltage VDS(on) (V) Drain to Source Voltage 5 10 Pulse test 5 2 1 VGS = 4 V 0.5 10 V 0.2 0.1 0.05 0.1 0.2 0.5 Drain Current 1 2 ID (A) 5 2SK1772 2.0 Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance RDS(on) (Ω) Static Drain to Source on State Resistance vs. Temperature Pulse test 1.6 1.2 2A 0.8 1A VGS = 4 V 0.5 A 2A 0.4 VGS = 10 V 0 –40 0 I D = 0.5 A, 1 A 40 80 120 Case Temperature 160 5.0 Tc = 25°C 1.0 75°C 0.5 0.2 0.1 VDS = 10 V Pulse test 0.05 0.02 TC (°C) C 50 Capacitance 20 10 5 0.02 0.05 0.1 0.2 0.5 Reverse Drain Current 1.0 (A) IDR Crss 10 1 0 2.0 (A) VDD = 5 V 10 V 20 V 30 16 12 VDS 8 10 4 VDD = 5 V 0.8 1.6 Gate Charge Rev.2.00 Sep 07, 2005 page 4 of 6 10 V 20 V 2.4 3.2 Qg (nc) 0 4.0 t (ns) 40 20 30 40 500 Switching Time VGS 10 VDS 50 (V) Switching Characteristics 20 ID = 1 A VGS= 0 f = 1 MHz Drain to Source Voltage Gate to Source Voltage VGS (V) VDS (V) 2.0 Ciss Coss 100 Dynamic Input Characteristics Drain to Source Voltage ID 1.0 (pF) 100 0 0.5 1000 di/dt = 50 A/µs VGS = 0 200 Ta = 25°C 20 0.2 Typical Capacitance vs. Drain to Source Voltage 500 50 0.05 0.1 Drain Current Body-Drain Diode Reverse Recovery Time Reverse Recovery Time trr (ns) –25°C 2.0 VGS = 10 V VDD = 30 V PW = 2 µs duty ≤ 1 % 200 100 tf td(off) 50 20 tr td(on) 10 5 0.02 0.05 0.1 0.2 Drain Current 0.5 ID 1.0 (A) 2.0 2SK1772 Reverse Drain Current vs. Source to Drain Voltage Reverse Drain Current IDR (A) 2.0 1.6 Pulse test VGS = 10 V 1.2 0.8 0, –5 V 0.4 0 0.4 0.8 1.2 1.6 2.0 Source to Drain Voltage VSD (V) Rev.2.00 Sep 07, 2005 page 5 of 6 2SK1772 Package Dimensions RENESAS Code Package Name MASS[Typ.] PLZZ0004CA-A UPAK / UPAKV 0.050g 1.5 1.5 3.0 1.5 ± 0.1 0.44 Max 2.5 ± 0.1 4.25 Max (1.5) 0.44 Max (0.2) 0.53 Max 0.48 Max 0.8 Min φ1 0.4 4.5 ± 0.1 1.8 Max Unit: mm (2.5) SC-62 (0.4) JEITA Package Code Ordering Information Part Name 2SK1772HYTR-E Quantity 3000 pcs Shipping Container Taping, φ178 mm Reel Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.2.00 Sep 07, 2005 page 6 of 6 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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