RICHTEK RT8800B

RT8800/B
General Purpose 2/3-Phase PWM Controller for High-Density
Power Supply
General Description
Features
The RT8800/B are general purpose multi-phase
synchronous buck controllers dedicating for high density
power supply regulation. The parts implement 2, and 3
buck switching stages operating in interleaved phase set
automatically. The output voltage is regulated and
controlled following the input voltage of FB pin. With such
a single analog control, the RT8800/B provide a simple,
flexible, wide-range and extreme cost-effective highdensity voltage regulation solutions for various high-density
power supply application. The RT8800/B multi-phase
architecture provide high output current while maintaining
low power dissipation on power devices and low stress
on input and output capacitors. The high equivalent
operating frequency also reduces the component
dimension and the output voltage ripple in load transient.
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RT8800/B implement both voltage and current loops to
achieve good regulation, response and power stage
thermal balance. The RT8800/B apply the time sharing
DCR current sensing technology newly as well; with such
a topology, the RT8800/B extract the DCR of output
inductor as sense component to deliver a more precise
load line regulation and better thermal balance capability.
Moreover, the parts monitor the output voltage for overcurrent and over-voltage protection; Soft-start and
programmable under-voltage lockout are also provided to
assure the safety of power system.
z
z
z
z
z
z
z
z
z
z
z
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5V Power Supply Voltage
2/3-Phase Power Conversion with Automatic Phase
Selection (RT8800 : 2/3-Phase, RT8800B : 2-Phase)
Output Voltage Controlled by External Reference
Voltage
Precise Core Voltage Regulation
Power Stage Thermal Balance by DCR Current
Sensing
Extreme Low-Cost, Lossless Time Sharing Current
Sensing
Internal Soft-start
Hiccup Mode Over-Current Protection
Over-Voltage Protection
Adjustable Operating Frequency and Typical at
300kHz Per Phase
Power Good indication
Small 16-Lead VQFN Package (For RT8800 only)
RoHS Compliant and 100% Lead (Pb)-Free
Ordering Information
RT8800/B
Package Type
QV : VQFN-16L 3x3 (V-Type)
S : SOP-16
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Applications
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Desktop CPU core power
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Low Output Voltage, High power density DC-DC
Converters
Voltage Regulator Modules
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Marking Information
2-Phase
2/3-Phase
Note :
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
DS8800/B-08 April 2011
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1
RT8800/B
Pin Configurations
PWM1
PWM2
VDD
PWM3
(TOP VIEW)
VDD
DACFB
DACQ
FB
DVD
COMP
PI
RT
16 15 14 13
DVD
4
GND
17
5
6
7
8
ICOMMON
3
RT
2
FB
PI
1
DACQ
COMP
DACFB
12
ISP1
11
ISP2
10
ISP3
9
PGOOD
2
16
15
3
14
4
5
13
12
6
7
11
10
8
9
PWM2
PWM1
N/C
ISP 1
ISP 2
PGOOD
GND
ICOMMON
SOP-16
VQFN-16L 3x3
RT8800B
RT8800
Functional Pin Description
DACFB
ICOMMON
Negative input of internal buffer amplifier for reference
voltage regulation. The pin voltage is locked at internal
VREF = 0.8V by properly close the buffer amplifier feedback
loop.
Common negative input of current sense amplifiers for all
three channels.
PGOOD
DACQ
Output power-good indication. The signal is implemented
as an output signal with open-drain type.
The pin is defined as the output of internal buffer amplifier
for reference voltage regulation.
ISP1 , ISP2 , ISP3
FB
Current sense positive inputs for individual converter
channel current sense.
The pin is defined as the inverting input of internal error
amplifier.
PWM1 , PWM2 , PWM3
PWM outputs for each phase switching drive.
DVD
The pin is defined as a programmable power UVLO
detection input. Trip threshold = 0.8V at VDVD rising.
VDD
COMP
GND
The pin is defined as the output of the error amplifier and
the input of all PWM comparators.
Chip power ground.
Chip power supply. Connect this pin to a 5V supply.
Exposed Pad (17) (RT8800)
PI
The pin is defined as the positive input of the error amplifier.
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
RT
Switching frequency setting. Connect this pin to GND with
a resistor to set the frequency.
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2
DS8800/B-08 April 2011
DS8800/B-08 April 2011
VID4
PGOOD
RT 8
R15
16k
RICOMMON2
R17
0
R16
0
C6
1uF
R19
R18
VCORE
Optional
C5
1uF
RICOMMON1
430
12
Optional
ISP2
13
Optional
DVD 5
R13
27k R14
3k
ICOMMON
12V
3.3V
R12
10k
11
16
GND 10
PWM2
ISP1
R10 5.1k
R9 3.3k
R8 6.8k
COMP
VID3
RT8800B
FB
2 DACFB
3 DACQ
6
R7 13k
R11
1.8k
PI
VDD
VID2
R6 27k
7
4
VID1
R5 56k
RDROOP
C4
15 PWM1
VID0
VID5
C2
10nF
C3
R3 3k
R2
5V
1
R4 110k
R1
15k
C1
33pF
Optional for
R&C
12V
C8
1uF
R20
10
R
PHASE1
R
PHASE2
C7
1uF
6
3
2
1
5
14
PWM2
D2
SS12/SM
C10
1uF
LGATE2
PHASE2
UGATE2
LGATE1
BOOT2
10
PGND
GND
PHASE1
UGATE1
RT9602
PWM1
PVCC
VDD
11
BOOT1
D1
SS12/SM
7
8
9
4
13
12
Q1
PHB95N03LT
R24
0
PHB83N03LT
R23
0
PHB95N03LT
R22
0
PHB83N03LT
R21
0
C9
1uF
Q6
Q4
Q3
Q5
L2
0.5uH
C16
1uF
PHASE1
1uF
C12
C17
3.3nF
R26
2.2
PHASE2 L3
0.5uH
C14
3.3nF
R25
2.2
C15
2200uF
Q2
C11
2200uF
L1
C13
1uH 1000uF
C30 to C33
10uF x 4
C18 to C29
1000uF x 12
VCORE
12V
RT8800/B
Typical Application Circuit
(Note : The inductor’ s DCR value must be large than 0.3mΩ
: X7R/R-type capacitor is required for all time constant setting capacitor of DCR sensing.)
9
Figure A. 2-phase with resistive DAC
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3
VID4
13k
RT 7
DVD 4
Optional
R15
16k
C4
4.7uF
C6
1uF
C7
1uF
R17
R17
C5 1uF
VCORE
Optional
RICOMMON1
430
R16
R
R
R
PHASE1
PHASE2
PHASE3
C10 to C13
1500uF x 4
11 Optional
10
14
15
Optional
ISP2
ISP3
PWM2
PWM3
12
RICOMMON2
R14
3k
27k
PGOOD
R13
9
GND
RT8800
ICOMMON
12V
3.3V
R12
10k
1 DACFB
5V
ISP1
R10 5.1k
R9 3.3k
R8 6.8k
R7
R11
1.8k
6
PI
2 DACQ
COMP
VID3
VID2
27k
56k
RDROOP
FB
R6
R5
R4 110k
C3
10nF
R3 3k
5
VID1
VID0
VID5
R1
15k
Optional
C2
R2
C9
1uF
1uH
17
C17
1uF
12V VIN
Q4
1
24
R21
0
BOOT1
PWM1
PWM2
PWM3
19
R18
0
Q1
BOOT2
D2
2
4
5
7
16
C14
1uF
D1
UGATE2
VIN
GND
R24
2.2
12V
22
1uF
3
R20
0
Q3
BOOT3
R22
0
Q6
C19 1uF
8 R23 10
9
5VSB
C22
1uF
11 12V
15
R25
14 0
UGATE3 10
PHASE3
PVCC3
LGATE3
C20
3.3nF
Q5
23
C18
C16
3.3uF
Q2
20
RT9605
21
12V
1uF
C15
R19 2.2
PVCC2
C8
1000uF
12V
LGATE2
C1
33pF
VDD
UGATE1
PHASE2
PHASE1
3
PVCC1
16
LGATE1
NC
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4
13 PWM1
VDD
L3
0.5uH
Q9
R27
2.2
L2
0.5uH
Q7
PHASE3
C23
3.3nF
L1
0.5uH
Q8
VIN
PHASE1
12V
D3
R26
0
C21
1uF
PHASE2
VCORE
C36 to C39
10uF x 4
C24 to C35
1000uF x 12
RT8800/B
8
Figure B. 3-phase with resistive DAC
DS8800/B-08 April 2011
5V
4
3
VDD
VDA
VID1
VID0
GND
VID4
VID3
5
6
7
8
RICOMMON2
Optional
R9
16k
RT 7
VID2
DVD 4
R8
3k
C5
4.7uF
C7
1uF
C8
1uF
R12
R11
R
R
R
PHASE1
PHASE2
PHASE3
C11 to C14
1500uF x 4
C6 1uF
R10
Optional
C10
1uF
VCORE
Optional
RICOMMON1
430
11
10
14
15
Optional
ISP2
ISP3
PWM2
PWM3
12
2
1
R7 27k
PGOOD
GND
ICOMMON
12V
3.3V
R6
10k
9
1 DACFB
COMP
R5
5.1k
5V
RT8800
FB
R4
5.1k
PI
2 DACQ
6
R3 3k
5
ISP1
RT9401A/B
C4
10nF
C2
10nF
RDROOP
R1
15k
Optional
C3
R2
1uH
17
C18
1uF
12V VIN
Q4
1
24
R16
0
BOOT1
PWM1
PWM2
PWM3
19
R13
0
BOOT2
D2
2
4
5
7
16
C15
1uF
D1
Q1
UGATE2
VIN
GND
1uF
Q3
BOOT3
C21
3.3nF
9
Q6
C20 1uF
8 R19 10
R20
0
5VSB
C23
1uF
11 12V
15
14
UGATE3 10
PHASE3
PVCC3
LGATE3
R18
0
Q5
23
C19
R17 2.2
12V
22
3
R15
0
C16
3.3uF
Q2
20
RT9605
21
12V
1uF
C17
R14 2.2
PVCC2
C9
1000uF
12V
LGATE2
C1
33pF
VDD
UGATE1
PHASE2
PHASE1
3
PVCC1
16
LGATE1
NC
DS8800/B-08 April 2011
13 PWM1
VDD
Q9
Q8
L3
0.5uH
R22
2.2
L2
0.5uH
Q7
PHASE3
C24
3.3nF
L1
0.5uH
VIN
PHASE1
12V
R21
0
C22
1uF
PHASE2
VCORE
C37 to C40
10uF x 4
C25 to C36
1000uF x 12
RT8800/B
8
Figure C. 3-phase with RT9401A/B DAC generator
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5
DACFB
DACQ
FB
PI
+
Buffer
Amplifier
500mV
0.8V
VREF
OVP
MAJ
EA
SUM/N
& OCP
Detection
OCP
Oscillator
&
Ramp Generator
GND
+
+
+
+
+
+
PWMCP
PWMCP
Sample
& Hold
Sample
& Hold
Sample
& Hold
PWMCP
Mux
INH
INH
INH
PWM Logic
& Driver
PWM Logic
& Driver
PWM Logic
& Driver
GM
Mux
COMP
Soft Start
+
-
Power On
Reset
+
+
RT
-
+
+
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6
+
+
+
PGOOD VDD DVD
ISP3
ISP2
ISP1
ICOMMON
PWM3
PWM2
PWM1
RT8800/B
Function Block Diagram
DS8800/B-08 April 2011
RT8800/B
Table. Output Voltage Program
VID5
VID4
VID3
VID2
VID1
VID0
Nominal Output Voltage (V)
1
1
1
1
1
1
1.0800
1
1
1
1
1
0
1.1000
0
1
1
1
1
0
1.1125
1
1
1
1
0
1
1.1250
0
1
1
1
0
1
1.1375
1
1
1
1
0
0
1.1500
0
1
1
1
0
0
1.1625
1
1
1
0
1
1
1.1750
0
1
1
0
1
1
1.1875
1
1
1
0
1
0
1.2000
0
1
1
0
1
0
1.2125
1
1
1
0
0
1
1.2250
0
1
1
0
0
1
1.2375
1
1
1
0
0
0
1.2500
0
1
1
0
0
0
1.2625
1
1
0
1
1
1
1.2750
0
1
0
1
1
1
1.2875
1
1
0
1
1
0
1.3000
0
1
0
1
1
0
1.3125
1
1
0
1
0
1
1.3250
0
1
0
1
0
1
1.3375
1
1
0
1
0
0
1.3500
0
1
0
1
0
0
1.3625
1
1
0
0
1
1
1.3750
0
1
0
0
1
1
1.3875
1
1
0
0
1
0
1.4000
0
1
0
0
1
0
1.4125
1
1
0
0
0
1
1.4250
0
1
0
0
0
1
1.4375
1
1
0
0
0
0
1.4500
0
1
0
0
0
0
1.4625
1
0
1
1
1
1
1.4750
0
0
1
1
1
1
1.4875
1
0
1
1
1
0
1.5000
0
0
1
1
1
0
1.5125
1
0
1
1
0
1
1.5250
0
0
1
1
0
1
1.5375
1
0
1
1
0
0
1.5500
To be continued
DS8800/B-08 April 2011
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7
RT8800/B
Table. Output Voltage Program
VID5
VID4
VID3
VID2
VID1
VID0
Nominal Output Voltage (V)
0
0
1
1
0
0
1.5625
1
0
1
0
1
1
1.5750
0
0
1
0
1
1
1.5875
1
0
1
0
1
0
1.6000
1
0
1
0
0
1
1.6250
1
0
1
0
0
0
1.6500
1
0
0
1
1
1
1.6750
1
0
0
1
1
0
1.7000
1
0
0
1
0
1
1.7250
1
0
0
1
0
0
1.7500
1
0
0
0
1
1
1.7750
1
0
0
0
1
0
1.8000
1
0
0
0
0
1
1.8250
1
0
0
0
0
0
1.8500
Note: 1 : Open
0 : VSS or GND
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8
DS8800/B-08 April 2011
RT8800/B
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
(Note 1)
Supply Voltage, VDD ------------------------------------------------------------------------------------------- 7V
Input, Output or I/O Voltage ---------------------------------------------------------------------------------- GND − 0.3V to VDD + 0.3V
Power Dissipation, PD @ TA = 25°C
VQFN-16L 3X3 -------------------------------------------------------------------------------------------------SOP-16 ----------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
VQFN-16L 3X3, θJA --------------------------------------------------------------------------------------------SOP-16, θJA ----------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) -------------------------------------------------------------------------------------------
Recommended Operating Conditions
z
z
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1.47W
1W
68°C/W
100°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Voltage, VDD ------------------------------------------------------------------------------------------- 5V ± 10%
Ambient Temperature Range --------------------------------------------------------------------------------- 0°C to 70°C
Junction Temperature Range --------------------------------------------------------------------------------- 0°C to 125°C
Electrical Characteristics
(VDD = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
5
--
mA
Rising
4.0
4.2
4.5
Hysteresis
0.2
0.5
--
0.75
0.8
0.85
V
--
65
--
mV
170
200
230
kHz
50
--
400
kHz
--
1.7
--
V
--
1.0
--
V
Maximum On-Time of Each Channel
62
66
75
%
Minimum On-Time of Each Channel
--
120
--
ns
0.77
0.82
0.87
V
VDD Supply Current
Nominal Supply Current
IDD
PWM 1,2,3 Open
Power On Reset
V DD Threshold
DVD Rising Threshold
DVD Hysteresis
V
Oscillator
Free Running Frequency
fOSC
Frequency Adjustable Range
fOSC_ADJ
Ramp Amplitude
ΔVOSC
Ramp Valley
VRV
RT Pin Voltage
VRT
RRT = 16kΩ
RRT = 16kΩ
RRT = 16kΩ
To be continued
DS8800/B-08 April 2011
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9
RT8800/B
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
0.79
0.8
0.81
V
--
--
10
mA
--
65
--
dB
Reference Voltage
Reference Voltage
VDACFB
DACFB Sourcing Capability
Error Amplifier
DC Gain
Gain-Bandwidth Product
GBW
CL = 10pF
--
10
--
MHz
Slew Rate
SR
CL = 10pF
--
8
--
V/μs
--
100
--
μA
160
190
220
μA
--
500
--
mV
--
--
0.2
V
4
--
8
ms
Current Sense GM Amplifier
Recommended Full Scale Source Current
OCP trip level
IOCP
Protection
Over-Voltage Trip (V FB - VDACQ)
Power Good
PGOOD Output Low Voltage
VPGOOD
IPGOOD = 4mA
PGOOD Delay
TPGOOD_Delay 90% * V OUT to PGOOD_H
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC
51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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10
DS8800/B-08 April 2011
RT8800/B
Typical Operating Characteristics
Efficiency vs. Output Current
Load Line
1.4
100
RLL = 1.5mΩ, RICOMMON2 = 10kΩ, RDROOP = 100Ω
VIN = 12V
1.38
VIN = 12V, VOUT = 1.4V
90
70
Efficiency (%)
Output Voltage (V)
80
1.36
1.34
1.32
1.3
60
50
40
30
1.28
20
1.26
10
1.24
0
0
10
20
30
40
50
60
70
80
90
Driver RT9605
0
100
10
20
30
Output Current (A)
40
70
80
90
100
GM
1000
90
900
80
800
70
700
RICOMMON1 = 430Ω
60
600
I ADJ (uA)
Frequency (kHz)
60
Output Current (A)
Frequency vs. RRT
500
400
GM3
GM2
GM1
50
40
30
300
200
20
100
10
0
0
0
5
10 15 20 25 30
35 40 45 50 55 60
0
10
20
30
40
50
60
70
80
90 100 110
VC (mV)
RRT (k
(kΩ)
ٛ)
VREF vs. Temperature
OCP Trip Point vs. Temperature
0.815
240
0.81
210
180
0.805
150
0.8
Ix (uA)
V REF (V)
50
0.795
120
90
0.79
60
0.785
30
0.78
0
-25
-10
5
20
35
50
65
80
Temperature (°C)
DS8800/B-08 April 2011
95
110 125
-25
-10
5
20
35
50
65
80
95
Temperature (°C)
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11
RT8800/B
Frequency vs. Temperature
Load Transient Response
350
V CORE
(200mV/Div)
Frequency (kHz)
300
250
UGATE1
(20V/Div)
200
150
UGATE2
(20V/Div)
100
50
RRT = 16kΩ
UGATE3
(20V/Div)
phase 1, IOUT = 5A to 85A @SR = 93A/us)
0
-25
-10
5
20
35
50
65
80
95
110 125
Time (2.5μs/Div)
Temperature (°C)
Load Transient Response
Load Transient Response
V CORE
(200mV/Div)
V CORE
(200mV/Div)
UGATE1
(20V/Div)
UGATE1
(20V/Div)
UGATE2
(20V/Div)
UGATE2
(20V/Div)
UGATE3
(20V/Div)
UGATE3
(20V/Div)
phase2, IOUT = 5A to 85A @SR = 93A/us)
phase 3, IOUT = 5A to 85A @SR = 93A/us)
Time (2.5μs/Div)
Time (2.5μs/Div)
Over Current Protection
Over Current Protection
Short After Turn_On
Short While Turn_On
IL1+IL2
(50A/Div)
IL1+IL2
(50A/Div)
V CORE
(1V/Div)
V CORE
(1V/Div)
PWM1
(10V/Div)
PWM1
(10V/Div)
VCOMP
(2V/Div)
VCOMP
(2V/Div)
Time (10ms/Div)
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12
Time (10ms/Div)
DS8800/B-08 April 2011
RT8800/B
VID On the Fly Falling
VID On the Fly Falling
IOUT = 5A
PWM
(5V/Div)
IOUT = 90A
V CORE
(50mV/Div)
PWM
(5V/Div)
V CORE
(100mV/Div)
VFB
(200mV/Div)
VFB
(200mV/Div)
VID0
(2V/Div)
VID0
(2V/Div)
Time (25μs/Div)
Time (25μs/Div)
VID On the Fly Rising
VID On the Fly Rising
IOUT = 90A
IOUT = 5A
PWM
(5V/Div)
PWM
(5V/Div)
V CORE
(200mV/Div)
V CORE
(200mV/Div)
VFB
(200mV/Div)
VFB
(200mV/Div)
VID0
(2V/Div)
VID0
(2V/Div)
Time (10μs/Div)
DS8800/B-08 April 2011
Time (10μs/Div)
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13
RT8800/B
Application Information
RT8800/B are multiphase DC/DC controllers for extreme
low cost applications that precisely regulate CPU core
voltage and balance the current of different power channels
using time sharing current sensing method. The converter
consisting of RT8800/B and its companion MOSFET driver
RT96xx series provide high quality CPU power and all
protection functions to meet the requirement of modern
VRM.
duty width according to its magnitude above the ramp
signal. The output follows the ramp signal, SS. However
while VOUT increases, the difference between VOUT and
SSE(SS − V GS) is reduced and COMP leaves the
saturation and declines. The takeover of SS lasts until it
meets the COMP. During this interval, since the feedback
path is broken, the converter is operated in the open loop.
Phase Setting and Converter Start Up
When the Comp takes over the non-inverting input for PWM
Amplifier and when SSE (SS − VGS) < VREF, the output of
the converter follows the ramp input, SSE (SS − VGS).
Before the crossover, the output follows SS signal. And
when Comp takes over SS, the output is expected to follow
SSE (SS − VGS). Therefore the deviation of VGS is
represented as the falling of VOUT for a short while. The
COMP is observed to keep its decline when it passes the
cross-over, which shortens the duty width and hence the
falling of VOUT happens.
RT8800/B interface with companion MOSFET drivers (like
RT9602, RT9603, and RT9605) for correct converter
initialization. RT8800/B will sense the voltage on PWM
pins at the instant of POR rising. If the voltage is smaller
than (VDD − 1.2V) the related channel is activated. Tie the
PWM to VDD and the corresponding current sense pins to
GND or left float if the channel is unused. For example, for
2-Channel application, tie PWM3 to VDD and ISP3 to GND
(or let ISP3 open).
PGOOD Function and Soft Start
To indicate the condition of multiphase converter,
RT8800/B provide PGOOD signal through an open drain
connection. The output becomes high impedance after
internal SS ramp > 3.5V.
3) Mode3 ( Cross-over< SS < VGS + VREF)
Since there is a feedback loop for the error amplifier, the
output’ s response to the ramp input, SSE (SS − VGS) is
lower than that in Mode 2.
4) Mode 4 (SS > VGS + VREF)
When SS > VGS + VREF, the output of the converter follows
the desired VREF signal and the soft start is completed
now.
Voltage Control
COMP
VRAMP_Valley
Cross-over
SS_Internal
V CORE
SSE_Internal
1) Mode 1 (SS< Vramp_valley)
Initially the COMP stays in the positive saturation. When
SS< VRAMP_Valley, there is no non-inverting input available
to produce duty width. So there is no PWM signal and
VOUT is zero.
2) Mode 2 (VRAMP_Valley< SS< Cross-over)
When SS>VRAMP_Valley, SS takes over the non-inverting
input and produce the PWM signal and the increasing
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14
The voltage control loop consists of error amplifier,
multiphase pulse width modulator, driver and power
components. As conventional voltage mode PWM
controller, the output voltage is locked at the positive input
of error amplifier and the error signal is used as the control
signal of pulse width modulator. The PWM signals of
different channels are generated by comparison of EA
output and split-phase sawtooth wave. Power stage
transforms VIN to output by PWM signal on-time ratio.
Output Voltage Program
The output voltage of a RT8800/B converter is programmed
to discrete levels between 1.08V and 1.85V. The voltage
identification (VID) pins program an external voltage
reference (DACQ) with a 6-bit digital-to-analog converter
(DAC). The level of DACQ also sets the OVP threshold.
The output voltage should not be adjusted while the
converter is delivering power. Remove input power before
DS8800/B-08 April 2011
RT8800/B
VCORE vs. Temperature
1.38
CPU : P4-2.8G
VCORE = 1.35V
1.375
R = 1/3
1.37
V CORE (V)
changing the output voltage. Adjusting the output voltage
during operation may trigger the over-voltage protection.
The DAC function is a precision non-inverting summation
amplifier shown in Figure 1. The resistor values shown
are only approximations of the actual precision values
used. Grounding any combination of the VID pins increases
the DACQ voltage. The “open” circuit voltage on the VID
pins is the band gap reference voltage (VREF = 0.8V).
1.365
1.36
1.355
R = 1/9
1.35
1.345
R
VID0
VREF
(0.8V)
R
VID1
R
VID2
VDACFB
+
OP
-
VDACQ
1.335
30
35
40
R
VID4
60
65
70
VCORE vs. Temperature
Figure 1. The Structure of Discrete DAC Generator
CPU : Celeron 2.0G
VCORE = 1.55V
1.64
DAC Design Guideline
The Original R
V CORE (V)
1.62
In high temperature environment, V CORE becomes
unstable for the leakage current in VID pins is increasing.
The leakage will increase current consumption of CPU,
and then raise RT8800's VDACQ reference output, so does
VCORE voltage. Below are four comparison charts for
different CPUs.
1.6
R = 1/3
1.58
1.56
R = 1/9
1.54
Note: In Below Figure 2 to Figure 5, The Original R means
1.52
the resister values shown in typical application circuit.
30
35
40
R=1/3 and R=1/9 mean that The Original R is divided
45
50
55
60
65
70
Temperature (°C)
by 3 or 9.
Figure 4
VCORE vs. Temperature
1.66
55
RG
1.66
1.68
50
Figure 3
R
VID5
45
Temperature (°C)
RF
R
VID3
The Original R
1.34
VCORE vs. Temperature
1.64
CPU : P4-3.06G
VCORE = 1.55V
1.63
CPU : P4-3.2G
VCORE = 1.55V
The Original R
1.62
The Original R
1.61
1.62
R = 1/3
1.6
V CORE (V)
V CORE (V)
1.64
1.6
R = 1/3
1.59
1.58
1.57
1.58
R = 1/9
R = 1/9
1.56
1.56
1.55
1.54
1.54
30
35
40
45
50
55
60
65
70
30
35
40
45
50
55
60
Temperature (°C)
Temperature (°C)
Figure 2
Figure 5
DS8800/B-08 April 2011
65
70
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15
RT8800/B
In order to maintain the VDACQ within 1% tolerance in the
worst case, the total driver current of the DAC regulator
should support up to 40mA. As the design of RT8800/B,
the maximum driving current of the internal OP is 10mA.
As shown in Figure 6, we suggest to add an external
transistor 2N3904 for higher current for VDAC regulation.
VCC
VID0
VID1
VID2
VID3
VID4
VID5
1.34k
645
VREF
(0.8V)
310
VDACFB
+
OP
-
VDACQ
VIN - VO
⎡
⎤
VO - (
) x TS ⎥
⎢
DCR
VIN
IX(S/H) = ⎢IL(AVG) ⎥x
2L
⎢
⎥ RICOMMON1
⎢⎣
⎥⎦
Falling Slope = Vo/L
IL
IL(AVG)
Q1
2N3904
43
162
for switching, period = TS
Inductor Current
IL(S/H)
PI
81
2.63k
121
PWM Signal & High Side MOSFET Gate Signal
Figure 6. Immune circuit against CPU Leakage Current
Current Sensing Setting
Low Side MOSFET Gate Signal
RT8800/B senses the current flowing through inductor
via its DCR for channel current balance and droop tuning.
The differential sensing GM amplifier converts the
voltage on the sense component (can be a sense
resistor or the DCR of the inductor) to current signal
into internal circuit (see Figure 7).
L
VC
= R × C VC = DCR × IL I X =
DCR
RICOMMON1
L
DCR
IL
C
R
GMx
ESR
+ V C
VISPX
+ V
ICOMMON
RICOMMON1
GMx
1k
RICOMMON
Figure 7. Current Sense Circuit
IX =
IL x DCR
RICOMMON1
DCR
C
+ V C
Ix
The sensing circuit gets
feedback.
Figure 9 is the test circuit for GM. We apply test signal at
GM inputs and observe its signal process output by PI
pin sinking current. Figure 10 shows the variation of signal
processing of all channels. We observe zero offsets and
good linearity between phases.
L
+
-
Figure 8. Inductor current and PWM signal
Ix
by local
Figure 9. The Test Circuit of GM
IX is sampled and held just before low side MOSFET turns
off (Figure 8).
IL(S/H) x DCR
VO TOFF
; IL(S/H) = IL(AVG) x
RICOMMON1
L
2
VIN - VO
TOFF = (
) x TS
VIN
IX(S/H) =
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16
DS8800/B-08 April 2011
RT8800/B
For some case with preferable current ratio instead of
current balance, the corresponding technique is provided.
Due to different physical environment of each channel, it
is necessary to slightly adjust current loading between
channels. Figure 12. shows the application circuit of GM
for current ratio requirement. Applying KVL along L+DCR
branch and R1+C//R2 branch:
GM
70
GM3
60
I ADJ (uA)
50
GM2
40
30
L
GM1
20
dIL
dVC ⎞
⎛ VC
+ DCR x IL = R1 ⎜
+C
⎟ + VC
dt
dt ⎠
⎝ R2
dVC R1 + R2
VC
+
dt
R2
R2
For VC =
DCR x IL
R1 + R2
= R1 x C
10
0
0
20
40
60
80
100
VC (mV)
Look for its corresponding conditions:
Figure 10. The Linearity of GMx
dIL
dIL
+ DCR x IL = (R1//R2) x C x DCR x
+ DCR x IL
dt
dt
L
Let
= (R1//R2) x C
DCR
L
Figure 11 shows the time sharing technique of GM
amplifier. We apply test signal at phase 3 and observe the
waveforms at both pins of GM amplifier. The waveforms
show time sharing mechanism and the perfomance of GM
to hold both input pins equal when the shared time is on.
Time Sharing of GM
CH1:(2V/Div)
CH2:(50mV/Div)
CH3:(50mV/Div)
L
= (R1//R2) x C
DCR
R2
Then VC =
x DCR x IL
R1 + R2
Thus if
With internal current balance function, this phase would
share (R 1+R 2)/R 2 times current than other phases.
Figure 13 &14 show different settings for the power stages.
PWM3
IL
VISP3
VISP3
and
VICOMMON
1.5uH
1m
3k
1uF
VICOMMON
3k
Time (1μs/Div)
Figure 13. GM3 Setting for current ratio function
Figure 11
Current Ratio Setting
IL
IL
L
1.5uH
1m
1.5k
1uF
DCR
C
R1
+V C
Figure 14. GM1,2 Setting for current ratio function
R2
Figure 12. Application circuit for current ratio setting
DS8800/B-08 April 2011
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17
RT8800/B
L
DCR
Load Line without dead zone at light loads
1.31
C
GMx
1.3
+ V C
V ISPX
+
V ICOMMON
RICOMMON1
Ix
RICOMMON2
1.29
V CORE (V)
ESR
1.28
RICOMMOM2 open
1.27
1.26
RICOMMON2 = 82k
1.25
Figure 15. Application circuit of GM
1.24
1.23
For load line design, with application circuit in Figure 15,
it can eliminate the dead zone of load line at light loads.
0
VISPX = VICOMMON
=
VICOMMON
I × DCR
+ L
RICOMMON2 RICOMMON1
VOUT + IL × DCR
I × DCR
+ L
RICOMMON2
RICOMMON1
VOUT
RICOMMON2
+
IL × DCR
RICOMMON2
I × DCR
+ L
RICOMMON1
For the lack of sinking capability of GM, RICOMMON2 should
be small enough to compensate the negative inductor
valley current especially at light loads.
VICOMMON
I × DCR
≥ L
RICOMMON2 RICOMMON1
Assume the negative inductor valley current is −5A at no
load, then for
RICOMMON1 = 330Ω, RADJ = 160Ω, VOUT = 1.300
- 5A × 1m Ω
1.3V
≥
RICOMMON2
330 Ω
RICOMMON2 ≤ 85.8kΩ
Choose RICOMMON2 = 82kΩ
www.richtek.com
18
15
20
25
Figure 16
if GM holds input voltages equal, then
=
10
I OUT (A)
VISPX = VOUT +IL x DCR
IX =
5
Current Balance
RT8800/B senses the inductor current via inductor’ s DCR
for channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal balance
circuit.
The current balance circuit sums and averages the current
signals and then produces the balancing signals injected
to pulse width modulator. If the current of some power
channel is larger than average, the balancing signal
reduces that channels pulse width to keep current balance.
The use of single GM amplifier via time sharing technique
to sense all inductor currents can reduce the offset errors
and linearity variation between GMs. Thus it can greatly
improve signal processing especially when dealing with
such small signal as voltage drop across DCR.
Voltage Reference for Converter Output & Load Droop
The positive input of error amplifier is PI pin that sinks
current proportional to the sum of converter output current.
VDRP = 2ISINK x RDRP. The load droop proportional to load
current can be set by the resistor between PI pin & external
VDACQ produced by either buffer amplifier or other voltage
source. The PI pin voltage should be larger than 0.8V for
good droop circuit performance.
DS8800/B-08 April 2011
RT8800/B
Over Current Protection
EA
+
FB
VDACQ
PI
+ VDRP -
CH1:(5V/Div)
CH2:(5V/Div)
ISINK
2xIX1
2xIX2
PWM
2xIX3
Figure 17. Load Droop Circuit
DAC Offset Voltage Tuning
The Intel specification requires that at no load the nominal
output voltage of the regulator be offset to a value lower
than the nominal voltage corresponding to the VID code.
The offset is tuning from RG in the DAC generator as
Figure 18.
VID0
VID1
VID2
VID3
VID4
VID5
R
R
VREF
(0.8V)
R
VDACFB
+
OP
-
IL
Time (25ms/Div)
Figure 19. The Over Current Protection in the interval
Over Current Protection
VDACQ
CH1:(5V/Div)
CH2:(5V/Div)
RF
R
R
R
RG
PWM
Figure 18. The Structure of Discrete DAC Generator
If VID0~6 is set at VSS (Ground), and to suppose that
shunt resistance is Rs.
VSS
From below equation, we can tune the value of RG to
increase or decrease the base voltage of VDACQ.
VDACQ = (1 +
RF
RF
) x VREF +
x VREF
RG
RS
Time (25ms/Div)
Figure 20. Over Current Protection at steady state
Over Current Protection
Fault Detection
OCP comparator co\mpares each inductor current sensed
& sample/hold by current sense circuit with this reference
current(150uA). RT8800/B uses hiccup mode to eliminate
fault detection of OCP or reduce output current when
output is shorted to ground.
The “hiccup mode” operation of over current protection
is adopted to reduce the short circuit current. The in-rush
current at the start up is suppressed by the soft start
circuit through clamping the pulse width and output voltage
by an internal slow rising ramp.
DS8800/B-08 April 2011
www.richtek.com
19
RT8800/B
Design Procedure Suggestion
LC Filter Pole = 1.45kHz and
a.Output filter pole and zero (Inductor, output capacitor
value & ESR).
ESR Zero =3.98kHz
b.Error amplifier compensation & sawtooth wave amplitude (compensation network).
Current Loop Setting
a.GM amplifier S/H current (current sense component
DCR, ICOMMON pin external resistor value).
b. EA Compensation Network:
Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF
and use the Type 2 compensation scheme shown in
Figure 21. By calculation, the F Z = 0.88kHz,
FP = 322kHz and Middle Band Gain is 3.19 (i.e
10.07dB).
C2 68pF
b.Over-current protection trip point (RICOMMON1 resistor).
RB2
VRM Load Line Setting
RB1
a.Droop amplitude (PI pin resistor).
4.7k
C1
15k 12nF
EA
+
b.No load offset (RICOMMON2)
Power Sequence & SS
Figure 21. Type 2 compensation network of EA
DVD pin external resistor and SS pin capacitor.
2. Over-Current Protection Setting
PCB Layout
a.Sense for current sense GM amplifier input.
b.Refer to layout guide for other items.
Voltage Loop Setting
Design Example
Given:
Consider the temperature coefficient of copper
3900ppm/°C,
IL × DCR
= 150 μA
RICOMMON1
IL × 1.39m Ω
= 150 μA
330Ω
IL = 35.6A
Apply for four phase converter
VIN = 12V
VCORE = 1.5V
ILOAD(MAX) = 100A
VDROOP = 100mV at full load (1mΩ Load Line)
OCP trip point set at 35A for each channel (S/H)
DCR = 1mΩ of inductor at 25°C
L = 1.5μH
COUT = 8000μF with 5mΩ equivalent ESR.
1. Compensation Setting
a. Modulator Gain, Pole and Zero:
From the following formula:
Modulator Gain =VIN/VRAMP =12/2.4=5 (i.e 14dB)
where VRAMP : ramp amplitude of saw-tooth wave
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20
DS8800/B-08 April 2011
RT8800/B
2. Switching ripple current path:
Layout Considerations
Place the high-power switching components first, and
separate them from sensitive nodes.
1. Most critical path:
a. Input capacitor to high side MOSFET.
b. Low side MOSFET to output capacitor.
c. The return path of input and output capacitor.
The current sense circuit is the most sensitive part of
the converter. The current sense resistors tied to
ISP1,2,3 and ICOMMON should be located not more
than 0.5 inch from the IC and away from the noise
switching nodes. The PCB trace of sense nodes should
be parallel and as short as possible. R&C filter of choke
should place close to PWM and the R & C connect
directly to the pin of each output choke, use 10 mil
differencial pair, and 20 mil gap to other phase pair.
Less via as possible.
SW1
d. Separate the power and signal GND.
e. The switching nodes (the connection node of high/
low side MOSFET and inductor) is the most noisy
points. Keep them away from sensitive small-signal
node.
f . Reduce parasitic R, L by minimum length, enough
copper thickness and avoiding of via.
3. MOSFET driver should be closed to MOSFET.
L1
VOUT
VIN
RIN
COUT
CIN
RL
V
L2
SW2
Figure 22. Power Stage Ripple Current Path
DS8800/B-08 April 2011
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21
RT8800/B
Next to IC
+12V or +5V
+12V
PWM
0.1uF
VCC
BST
Next to IC
DRVH
LO1
SW
IN
RT9603
CBP
RT
CBOOT
+5VIN
VCC
CIN
GND
VCORE
COUT
COMP
CC
RT8800/B
RICOM
RC
ICOMMON
DRVL
Locate next
to FB Pin
FB
GND
RFB
CSPx
Locate near MOSFETs
PI
GND
RDRD
Figure 23. Layout Consideration
Figure 24
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22
DS8800/B-08 April 2011
RT8800/B
Figure 25
Figure 26
DS8800/B-08 April 2011
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23
RT8800/B
Figure 27
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24
DS8800/B-08 April 2011
RT8800/B
Outline Dimension
D
SEE DETAIL A
D2
L
1
E
E2
e
b
A
A1
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A3
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.800
1.000
0.031
0.039
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
1.300
1.750
0.051
0.069
E
2.950
3.050
0.116
0.120
E2
1.300
1.750
0.051
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
V-Type 16L QFN 3x3 Package
DS8800/B-08 April 2011
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25
RT8800/B
H
A
M
B
J
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
9.804
10.008
0.386
0.394
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.178
0.254
0.007
0.010
I
0.102
0.254
0.004
0.010
J
5.791
6.198
0.228
0.244
M
0.406
1.270
0.016
0.050
16–Lead SOP Plastic Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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26
DS8800/B-08 April 2011