RICHTEK RT8841

RT8841
4/3/2/1-Phase PWM Controller for High-Density Power Supply
General Description
Features
The RT8841 is a 4/3/2/1-phase synchronous buck
controller with 2 integrated MOSFET drivers for VR11 CPU
power application. RT8841 uses differential inductor DCR
current sense to achieve phase current balance and active
voltage positioning. Other features include adjustable
operating frequency, adjustable soft start, power good
indication, external error-amp compensation, over voltage
protection, over current protection and enable/shutdown
for various applications. RT8841 comes to a small footprint
with WQFN-40L 6x6 package
z
12V Power Supply Voltage
z
4/3/2/1-Phase Power Conversion
2 Embedded MOSFET Drivers
Internal Regulated 5V Output
VID Tables for Intel VRD11/VRD10.x and AMD K8,
K8_M2 CPUs
Continuous Differential Inductor DCR Current Sense
Adjustable Soft Start
Adjustable Frequency
Power Good Indication
Adjustable Over Current Protection
Over Voltage Protection
Small 40-Lead WQFN Package
RoHS Compliant and 100% Lead(Pb)-Free
z
z
z
z
z
z
z
z
Applications
z
z
Desktop CPU Core Power
Low Voltage, High Current DC/ DC Converter
Ordering Information
z
z
z
Pin Configurations
RT8841
(TOP VIEW)
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
EN/VTT
PWRGD
Package Type
QW : WQFN-40L 6x6 (W-Type)
40 39 38 37 36 35 34 33 32 31
VIDSEL
FBRTN
SS/EN
ADJ
COMP
FB
OFS
RT
IMAX
GND
1
30
2
29
3
28
4
27
5
6
26
GND
25
24
7
8
9
41
23
22
21
10
BOOT1
UGATE1
PHASE1
LGATE1
VCC12
LGATE2
PHASE2
UGATE2
BOOT2
PWM3
ISP4
ISN4
ISN3
ISP3
ISP2
ISN2
ISN1
ISP1
VCC5
PWM4
11 12 13 14 15 16 17 18 19 20
WQFN-40L 6x6
DS8841-01 April 2011
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1
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2
L2
L1
12V
12V
VCC
PWM
GND
PWM
GND
VCC
RT9619
LGATE
PHASE
UGATE
BOOT
RT9619
LGATE
PHASE
UGATE
BOOT
12V
12V
ISP4
PWM4
12 ISN4
11
20
14 ISP3
13 ISN3
21 PWM3
8
RT
9 IMAX
19 VCC5
7 OFS
4 ADJ
GND 10
VCC12 26
FBRTN 2
SS/EN 3
COMP 5
ISP2 15
16
ISN2
FB 6
PHASE2 24
LGATE2 25
UGATE2 23
ISP1 18
ISN1 17
33 to 40
VID[7:0]
32
EN/VTT
1
VIDSEL
31
PWRGD
BOOT2 22
PHASE1 28
LGATE1 27
BOOT1 30
UGATE1 29
RT8841
12V
12V
12V
L4
L3
NTC
LOAD
VCORE
RT8841
Typical Application Circuit
DS8841-01 April 2011
RT8841
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
0
1
0
1
0
1
1
1.60000V
0
1
0
1
0
1
0
1.59375V
0
1
0
1
1
0
1
1.58750V
0
1
0
1
1
0
0
1.58125V
0
1
0
1
1
1
1
1.57500V
0
1
0
1
1
1
0
1.56875V
0
1
1
0
0
0
1
1.56250V
0
1
1
0
0
0
0
1.55625V
0
1
1
0
0
1
1
1.55000V
0
1
1
0
0
1
0
1.54375V
0
1
1
0
1
0
1
1.53750V
0
1
1
0
1
0
0
1.53125V
0
1
1
0
1
1
1
1.52500V
0
1
1
0
1
1
0
1.51875V
0
1
1
1
0
0
1
1.51250V
0
1
1
1
0
0
0
1.50625V
0
1
1
1
0
1
1
1.50000V
0
1
1
1
0
1
0
1.49375V
0
1
1
1
1
0
1
1.48750V
0
1
1
1
1
0
0
1.48125V
0
1
1
1
1
1
1
1.47500V
0
1
1
1
1
1
0
1.46875V
1
0
0
0
0
0
1
1.46250V
1
0
0
0
0
0
0
1.45625V
1
0
0
0
0
1
1
1.45000V
1
0
0
0
0
1
0
1.44375V
1
0
0
0
1
0
1
1.43750V
1
0
0
0
1
0
0
1.43125V
1
0
0
0
1
1
1
1.42500V
1
0
0
0
1
1
0
1.41875V
1
0
0
1
0
0
1
1.41250V
1
0
0
1
0
0
0
1.40625V
1
0
0
1
0
1
1
1.40000V
1
0
0
1
0
1
0
1.39375V
1
0
0
1
1
0
1
1.38750V
1
0
0
1
1
0
0
1.38125V
1
0
0
1
1
1
1
1.37500V
1
0
0
1
1
1
0
1.36875V
1
0
1
0
0
0
1
1.36250V
To be continued
DS8841-01 April 2011
www.richtek.com
3
RT8841
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
1
0
1
0
0
0
0
1.35625V
1
0
1
0
0
1
1
1.35000V
1
0
1
0
0
1
0
1.34375V
1
0
1
0
1
0
1
1.33750V
1
0
1
0
1
0
0
1.33125V
1
0
1
0
1
1
1
1.32500V
1
0
1
0
1
1
0
1.31875V
1
0
1
1
0
0
1
1.31250V
1
0
1
1
0
0
0
1.30625V
1
0
1
1
0
1
1
1.30000V
1
0
1
1
0
1
0
1.29375V
1
0
1
1
1
0
1
1.28750V
1
0
1
1
1
0
0
1.28125V
1
0
1
1
1
1
1
1.27500V
1
0
1
1
1
1
0
1.26875V
1
1
0
0
0
0
1
1.26250V
1
1
0
0
0
0
0
1.25625V
1
1
0
0
0
1
1
1.25000V
1
1
0
0
0
1
0
1.24375V
1
1
0
0
1
0
1
1.23750V
1
1
0
0
1
0
0
1.23125V
1
1
0
0
1
1
1
1.22500V
1
1
0
0
1
1
0
1.21875V
1
1
0
1
0
0
1
1.21250V
1
1
0
1
0
0
0
1.20625V
1
1
0
1
0
1
1
1.20000V
1
1
0
1
0
1
0
1.19375V
1
1
0
1
1
0
1
1.18750V
1
1
0
1
1
0
0
1.18125V
1
1
0
1
1
1
1
1.17500V
1
1
0
1
1
1
0
1.16875V
1
1
1
0
0
0
1
1.16250V
1
1
1
0
0
0
0
1,15625V
1
1
1
0
0
1
1
1.15000V
1
1
1
0
0
1
0
1.14375V
1
1
1
0
1
0
1
1.13750V
1
1
1
0
1
0
0
1.13125V
1
1
1
0
1
1
1
1.12500V
1
1
1
0
1
1
0
1.11875V
To be continued
www.richtek.com
4
DS8841-01 April 2011
RT8841
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
1
1
1
1
0
0
1
1.11250V
1
1
1
1
0
0
0
1.10625V
1
1
1
1
0
1
1
1.10000V
1
1
1
1
0
1
0
1.09375V
1
1
1
1
1
0
1
OFF
1
1
1
1
1
0
0
OFF
1
1
1
1
1
1
1
OFF
1
1
1
1
1
1
0
OFF
0
0
0
0
0
0
1
1.08750V
0
0
0
0
0
0
0
1.08125V
0
0
0
0
0
1
1
1.07500V
0
0
0
0
0
1
0
1.06875V
0
0
0
0
1
0
1
1.06250V
0
0
0
0
1
0
0
1.05625V
0
0
0
0
1
1
1
1.05000V
0
0
0
0
1
1
0
1.04375V
0
0
0
1
0
0
1
1.03750V
0
0
0
1
0
0
0
1.03125V
0
0
0
1
0
1
1
1.02500V
0
0
0
1
0
1
0
1.01875V
0
0
0
1
1
0
1
1.01250V
0
0
0
1
1
0
0
1.00625V
0
0
0
1
1
1
1
1.00000V
0
0
0
1
1
1
0
0.99375V
0
0
1
0
0
0
1
0.98750V
0
0
1
0
0
0
0
0.98125V
0
0
1
0
0
1
1
0.97500V
0
0
1
0
0
1
0
0.96875V
0
0
1
0
1
0
1
0.96250V
0
0
1
0
1
0
0
0.95625V
0
0
1
0
1
1
1
0.95000V
0
0
1
0
1
1
0
0.94375V
0
0
1
1
0
0
1
0.93750V
0
0
1
1
0
0
0
0.93125V
0
0
1
1
0
1
1
0.92500V
0
0
1
1
0
1
0
0.91875V
0
0
1
1
1
0
1
0.91250V
0
0
1
1
1
0
0
0.90625V
0
0
1
1
1
1
1
0.90000V
To be continued
DS8841-01 April 2011
www.richtek.com
5
RT8841
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
0
0
1
1
1
1
0
0.89375V
0
1
0
0
0
0
1
0.88750V
0
1
0
0
0
0
0
0.88125V
0
1
0
0
0
1
1
0.87500V
0
1
0
0
0
1
0
0.86875V
0
1
0
0
1
0
1
0.86250V
0
1
0
0
1
0
0
0.85625V
0
1
0
0
1
1
1
0.85000V
0
1
0
0
1
1
0
0.84375V
0
1
0
1
0
0
1
0.83750V
0
1
0
1
0
0
0
0.83125V
Note: (1) 0 : Connected to GND
(2) 1 : Open
www.richtek.com
6
DS8841-01 April 2011
RT8841
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage
VID 7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DACOUT
0
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
0
1
OFF
0
0
0
0
0
0
1
0
1.60000V
0
0
0
0
0
0
1
1
1.59375V
0
0
0
0
0
1
0
0
1.58750V
0
0
0
0
0
1
0
1
1.58125V
0
0
0
0
0
1
1
0
1.57500V
0
0
0
0
0
1
1
1
1.56875V
0
0
0
0
1
0
0
0
1.56250V
0
0
0
0
1
0
0
1
1.55625V
0
0
0
0
1
0
1
0
1.55000V
0
0
0
0
1
0
1
1
1.54375V
0
0
0
0
1
1
0
0
1.53750V
0
0
0
0
1
1
0
1
1.53125V
0
0
0
0
1
1
1
0
1.52500V
0
0
0
0
1
1
1
1
1.51875V
0
0
0
1
0
0
0
0
1.51250V
0
0
0
1
0
0
0
1
1.50625V
0
0
0
1
0
0
1
0
1.50000V
0
0
0
1
0
0
1
1
1.49375V
0
0
0
1
0
1
0
0
1.48750V
0
0
0
1
0
1
0
1
1.48125V
0
0
0
1
0
1
1
0
1.47500V
0
0
0
1
0
1
1
1
1.46875V
0
0
0
1
1
0
0
0
1.46250V
0
0
0
1
1
0
0
1
1.45625V
0
0
0
1
1
0
1
0
1.45000V
0
0
0
1
1
0
1
1
1.44375V
0
0
0
1
1
1
0
0
1.43750V
0
0
0
1
1
1
0
1
1.43125V
0
0
0
1
1
1
1
0
1.42500V
0
0
0
1
1
1
1
1
1.41875V
0
0
1
0
0
0
0
0
1.41250V
0
0
1
0
0
0
0
1
1.40625V
0
0
1
0
0
0
1
0
1.40000V
0
0
1
0
0
0
1
1
1.39375V
0
0
1
0
0
1
0
0
1.38750V
0
0
1
0
0
1
0
1
1.38125V
0
0
1
0
0
1
1
0
1.37500V
0
0
1
0
0
1
1
1
1.36875V
To be continued
DS8841-01 April 2011
www.richtek.com
7
RT8841
Table 2. Output Voltage Program (VRD11)
Pin Nam e
Nominal Output Voltage
VID7
0
VID6
0
VID5
1
VID4
0
VID3
1
VID2
0
VID1
0
VID 0
0
D ACOUT
0
0
1
0
1
0
0
1
1.35625V
0
0
1
0
1
0
1
0
1.35000V
0
0
1
0
1
0
1
1
1.34375V
0
0
1
0
1
1
0
0
1.33750V
0
0
1
0
1
1
0
1
1.33125V
0
0
1
0
1
1
1
0
1.32500V
0
0
1
0
1
1
1
1
1.31875V
0
0
1
1
0
0
0
0
1.31250V
0
0
1
1
0
0
0
1
1.30625V
0
0
1
1
0
0
1
0
1.30000V
0
0
1
1
0
0
1
1
1.29375V
0
0
1
1
0
1
0
0
1.28750V
0
0
1
1
0
1
0
1
1.28125V
0
0
1
1
0
1
1
0
1.27500V
0
0
1
1
0
1
1
1
1.26875V
0
0
1
1
1
0
0
0
1.26250V
0
0
1
1
1
0
0
1
1.25625V
0
0
1
1
1
0
1
0
1.25000V
0
0
1
1
1
0
1
1
1.24375V
0
0
1
1
1
1
0
0
1.23750V
0
0
1
1
1
1
0
1
1.23125V
0
0
1
1
1
1
1
0
1.22500V
0
0
1
1
1
1
1
1
1.21875V
0
1
0
0
0
0
0
0
1.21250V
0
1
0
0
0
0
0
1
1.20625V
0
1
0
0
0
0
1
0
1.20000V
0
1
0
0
0
0
1
1
1.19375V
0
1
0
0
0
1
0
0
1.18750V
0
1
0
0
0
1
0
1
1.18125V
0
1
0
0
0
1
1
0
1.17500V
0
1
0
0
0
1
1
1
1.16875V
0
1
0
0
1
0
0
0
1.16250V
0
1
0
0
1
0
0
1
1.15625V
0
1
0
0
1
0
1
0
1.15000V
0
1
0
0
1
0
1
1
1.14375V
0
1
0
0
1
1
0
0
1.13750V
0
1
0
0
1
1
0
1
1.13125V
0
1
0
0
1
1
1
0
1.12500V
0
1
0
0
1
1
1
1
1.11875V
1.36250V
To be continued
www.richtek.com
8
DS8841-01 April 2011
RT8841
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage
DACOUT
VID7
0
VID6
1
VID5
0
VID4
1
VID3
0
VID2
0
VID1
0
VID0
0
1.11250V
0
1
0
1
0
0
0
1
1.10625V
0
1
0
1
0
0
1
0
1.10000V
0
1
0
1
0
0
1
1
1.09375V
0
1
0
1
0
1
0
0
1.08750V
0
1
0
1
0
1
0
1
1.08125V
0
1
0
1
0
1
1
0
1.07500V
0
1
0
1
0
1
1
1
1.06875V
0
1
0
1
1
0
0
0
1.06250V
0
1
0
1
1
0
0
1
1.05625V
0
1
0
1
1
0
1
0
1.05000V
0
1
0
1
1
0
1
1
1.04375V
0
1
0
1
1
1
0
0
1.03750V
0
1
0
1
1
1
0
1
1.03125V
0
1
0
1
1
1
1
0
1.02500V
0
1
0
1
1
1
1
1
1.01875V
0
1
1
0
0
0
0
0
1.01250V
0
1
1
0
0
0
0
1
1.00625V
0
1
1
0
0
0
1
0
1.00000V
0
1
1
0
0
0
1
1
0.99375V
0
1
1
0
0
1
0
0
0.98750V
0
1
1
0
0
1
0
1
0.98125V
0
1
1
0
0
1
1
0
0.97500V
0
1
1
0
0
1
1
1
0.96875V
0
1
1
0
1
0
0
0
0.96250V
0
1
1
0
1
0
0
1
0.95625V
0
1
1
0
1
0
1
0
0.95000V
0
1
1
0
1
0
1
1
0.94375V
0
1
1
0
1
1
0
0
0.93750V
0
1
1
0
1
1
0
1
0.93125V
0
1
1
0
1
1
1
0
0.92500V
0
1
1
0
1
1
1
1
0.91875V
0
1
1
1
0
0
0
0
0.91250V
0
1
1
1
0
0
0
1
0.90625V
0
1
1
1
0
0
1
0
0.90000V
0
1
1
1
0
0
1
1
0.89375V
0
1
1
1
0
1
0
0
0.88750V
0
1
1
1
0
1
0
1
0.88125V
0
1
1
1
0
1
1
0
0.87500V
0
1
1
1
0
1
1
1
0.86875V
To be continued
DS8841-01 April 2011
www.richtek.com
9
RT8841
Table 2. Output Voltage Program (VRD11)
Pin Nam e
Nominal Output Voltage
DACOUT
VID7
0
VID 6
1
VID5
1
VID 4
1
VID 3
1
VID2
0
VID1
0
VID0
0
0.86250V
0
1
1
1
1
0
0
1
0.85625V
0
1
1
1
1
0
1
0
0.85000V
0
1
1
1
1
0
1
1
0.84375V
0
1
1
1
1
1
0
0
0.83750V
0
1
1
1
1
1
0
1
0.83125V
0
1
1
1
1
1
1
0
0.82500V
0
1
1
1
1
1
1
1
0.81875V
1
0
0
0
0
0
0
0
0.81250V
1
0
0
0
0
0
0
1
0.80625V
1
0
0
0
0
0
1
0
0.80000V
1
0
0
0
0
0
1
1
0.79375V
1
0
0
0
0
1
0
0
0.78750V
1
0
0
0
0
1
0
1
0.78125V
1
0
0
0
0
1
1
0
0.77500V
1
0
0
0
0
1
1
1
0.76875V
1
0
0
0
1
0
0
0
0.76250V
1
0
0
0
1
0
0
1
0.75625V
1
0
0
0
1
0
1
0
0.75000V
1
0
0
0
1
0
1
1
0.74375V
1
0
0
0
1
1
0
0
0.73750V
1
0
0
0
1
1
0
1
0.73125V
1
0
0
0
1
1
1
0
0.72500V
1
0
0
0
1
1
1
1
0.71875V
1
0
0
1
0
0
0
0
0.71250V
1
0
0
1
0
0
0
1
0.70625V
1
0
0
1
0
0
1
0
0.70000V
1
0
0
1
0
0
1
1
0.69375V
1
0
0
1
0
1
0
0
0.68750V
1
0
0
1
0
1
0
1
0.68125V
1
0
0
1
0
1
1
0
0.67500V
1
0
0
1
0
1
1
1
0.66875V
1
0
0
1
1
0
0
0
0.66250V
1
0
0
1
1
0
0
1
0.65625V
1
0
0
1
1
0
1
0
0.65000V
1
0
0
1
1
0
1
1
0.64375V
1
0
0
1
1
1
0
0
0.63750V
1
0
0
1
1
1
0
1
0.63125V
1
0
0
1
1
1
1
0
0.62500V
1
0
0
1
1
1
1
1
0.61875V
To be continued
www.richtek.com
10
DS8841-01 April 2011
RT8841
Table 2. Output Voltage Program (VRD11)
Pin Nam e
Nominal Output Voltage
DACOUT
VID7
1
VID6
0
VID5
1
VID4
0
VID3
0
VID2
0
VID1
0
VID 0
0
0.61250V
1
0
1
0
0
0
0
1
0.60625V
1
0
1
0
0
0
1
0
0.60000V
1
0
1
0
0
0
1
1
0.59375V
1
0
1
0
0
1
0
0
0.58750V
1
0
1
0
0
1
0
1
0.58125V
1
0
1
0
0
1
1
0
0.57500V
1
0
1
0
0
1
1
1
0.56875V
1
0
1
0
1
0
0
0
0.56250V
1
0
1
0
1
0
0
1
0.55625V
1
0
1
0
1
0
1
0
0.55000V
1
0
1
0
1
0
1
1
0.54375V
1
0
1
0
1
1
0
0
0.53750V
1
0
1
0
1
1
0
1
0.53125V
1
0
1
0
1
1
1
0
0.52500V
1
0
1
0
1
1
1
1
0.51875V
1
0
1
1
0
0
0
0
0.51250V
1
0
1
1
0
0
0
1
0.50625V
1
0
1
1
0
0
1
0
0.50000V
1
0
1
1
0
0
1
1
X
1
0
1
1
0
1
0
0
X
1
0
1
1
0
1
0
1
X
1
0
1
1
0
1
1
0
X
1
0
1
1
0
1
1
1
X
1
0
1
1
1
0
0
0
X
1
0
1
1
1
0
0
1
X
1
0
1
1
1
0
1
0
X
1
0
1
1
1
0
1
1
X
1
0
1
1
1
1
0
0
X
1
0
1
1
1
1
0
1
X
1
0
1
1
1
1
1
0
X
1
0
1
1
1
1
1
1
X
1
1
0
0
0
0
0
0
X
1
1
0
0
0
0
0
1
X
1
1
0
0
0
0
1
0
X
1
1
0
0
0
0
1
1
X
1
1
0
0
0
1
0
0
X
1
1
0
0
0
1
0
1
X
1
1
0
0
0
1
1
0
X
1
1
0
0
0
1
1
1
X
To be continued
DS8841-01 April 2011
www.richtek.com
11
RT8841
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage
VID7
1
VID6
1
VID5
0
VID4
0
VID3
1
VID2
0
VID1
0
VID0
0
DACOUT
1
1
0
0
1
0
0
1
X
1
1
0
0
1
0
1
0
X
1
1
0
0
1
0
1
1
X
1
1
0
0
1
1
0
0
X
1
1
0
0
1
1
0
1
X
1
1
0
0
1
1
1
0
X
1
1
0
0
1
1
1
1
X
1
1
0
1
0
0
0
0
X
1
1
0
1
0
0
0
1
X
1
1
0
1
0
0
1
0
X
1
1
0
1
0
0
1
1
X
1
1
0
1
0
1
0
0
X
1
1
0
1
0
1
0
1
X
1
1
0
1
0
1
1
0
X
1
1
0
1
0
1
1
1
X
1
1
0
1
1
0
0
0
X
1
1
0
1
1
0
0
1
X
1
1
0
1
1
0
1
0
X
1
1
0
1
1
0
1
1
X
1
1
0
1
1
1
0
0
X
1
1
0
1
1
1
0
1
X
1
1
0
1
1
1
1
0
X
1
1
0
1
1
1
1
1
X
1
1
1
0
0
0
0
0
X
1
1
1
0
0
0
0
1
X
1
1
1
0
0
0
1
0
X
1
1
1
0
0
0
1
1
X
1
1
1
0
0
1
0
0
X
1
1
1
0
0
1
0
1
X
1
1
1
0
0
1
1
0
X
1
1
1
0
0
1
1
1
X
1
1
1
0
1
0
0
0
X
1
1
1
0
1
0
0
1
X
1
1
1
0
1
0
1
0
X
1
1
1
0
1
0
1
1
X
1
1
1
0
1
1
0
0
X
1
1
1
0
1
1
0
1
X
1
1
1
0
1
1
1
0
X
1
1
1
0
1
1
1
1
X
X
To be continued
www.richtek.com
12
DS8841-01 April 2011
RT8841
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage
VID7
1
VID6
1
VID5
1
VID4
1
VID3
0
VID2
0
VID1
0
VID0
0
DACOUT
1
1
1
1
0
0
0
1
X
1
1
1
1
0
0
1
0
X
1
1
1
1
0
0
1
1
X
1
1
1
1
0
1
0
0
X
1
1
1
1
0
1
0
1
X
1
1
1
1
0
1
1
0
X
1
1
1
1
0
1
1
1
X
1
1
1
1
1
0
0
0
X
1
1
1
1
1
0
0
1
X
1
1
1
1
1
0
1
0
X
1
1
1
1
1
0
1
1
X
1
1
1
1
1
1
0
0
X
1
1
1
1
1
1
0
1
X
1
1
1
1
1
1
1
0
OFF
1
1
1
1
1
1
1
1
OFF
X
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) X : Don't Care
DS8841-01 April 2011
www.richtek.com
13
RT8841
Table 3. Output Voltage Program (K8)
VID4
VID3
VID2
VID1
VID0
Nominal Output Voltage DACOUT
0
0
0
0
0
1.550
0
0
0
0
1
1.525
0
0
0
1
0
1.500
0
0
0
1
1
1.475
0
0
1
0
0
1.450
0
0
1
0
1
1.425
0
0
1
1
0
1.400
0
0
1
1
1
1.375
0
1
0
0
0
1.350
0
1
0
0
1
1.325
0
1
0
1
0
1.200
0
1
0
1
1
1.275
0
1
1
0
0
1.250
0
1
1
0
1
1.225
0
1
1
1
0
1.200
0
1
1
1
1
1.175
1
0
0
0
0
1.150
1
0
0
0
1
1.125
1
0
0
1
0
1.100
1
0
0
1
1
1.075
1
0
1
0
0
1.050
1
0
1
0
1
1.025
1
0
1
1
0
1.000
1
0
1
1
1
0.975
1
1
0
0
0
0.950
1
1
0
0
1
0.925
1
1
0
1
0
0.900
1
1
0
1
1
0.875
1
1
1
0
0
0.850
1
1
1
0
1
0.825
1
1
1
1
0
0.800
1
1
1
1
1
Shutdown
Note: (1) 0 : Connected to GND
(2) 1 : Open
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14
DS8841-01 April 2011
RT8841
Table 4. Output Voltage Program (K8_M2)
Pin Name
Nominal Output Voltage DACOUT
VID5
VID4
VID3
VID2
VID1
VID0
0
0
0
0
0
0
1.5500
0
0
0
0
0
1
1.5250
0
0
0
0
1
0
1.5000
0
0
0
0
1
1
1.4750
0
0
0
1
0
0
1.4500
0
0
0
1
0
1
1.4250
0
0
0
1
1
0
1.4000
0
0
0
1
1
1
1.3750
0
0
1
0
0
0
1.3500
0
0
1
0
0
1
1.3250
0
0
1
0
1
0
1.3000
0
0
1
0
1
1
1.2750
0
0
1
1
0
0
1.2500
0
0
1
1
0
1
1.2250
0
0
1
1
1
0
1.2000
0
0
1
1
1
1
1.1750
0
1
0
0
0
0
1.1500
0
1
0
0
0
1
1.1250
0
1
0
0
1
0
1.1000
0
1
0
0
1
1
1.0750
0
1
0
1
0
0
1.0500
0
1
0
1
0
1
1.0250
0
1
0
1
1
0
1.0000
0
1
0
1
1
1
0.9750
0
1
1
0
0
0
0.9500
0
1
1
0
0
1
0.9250
0
1
1
0
1
0
0.9000
0
1
1
0
1
1
0.8750
0
1
1
1
0
0
0.8500
0
1
1
1
0
1
0.8250
0
1
1
1
1
0
0.8000
0
1
1
1
1
1
0.7750
1
0
0
0
0
0
0.7625
1
0
0
0
0
1
0.7500
To be continued
DS8841-01 April 2011
www.richtek.com
15
RT8841
Table 4. Output Voltage Program (K8_M2)
Pin Name
Nominal Output Voltage DACOUT
VID5
VID4
VID3
VID2
VID1
VID0
1
0
0
0
1
0
0.7375
1
0
0
0
1
1
0.7250
1
0
0
1
0
0
0.7125
1
0
0
1
0
1
0.7000
1
0
0
1
1
0
0.6875
1
0
0
1
1
1
0.6750
1
0
1
0
0
0
0.6625
1
0
1
0
0
1
0.6500
1
0
1
0
1
0
0.6375
1
0
1
0
1
1
0.6250
1
0
1
1
0
0
0.6125
1
0
1
1
0
1
0.6000
1
0
1
1
1
0
0.5875
1
0
1
1
1
1
0.5750
1
1
0
0
0
0
0.5625
1
1
0
0
0
1
0.5500
1
1
0
0
1
0
0.5375
1
1
0
0
1
1
0.5250
1
1
0
1
0
0
0.5125
1
1
0
1
0
1
0.5000
1
1
0
1
1
0
0.4875
1
1
0
1
1
1
0.4750
1
1
1
0
0
0
0.4625
1
1
1
0
0
1
0.4500
1
1
1
0
1
0
0.4375
1
1
1
0
1
1
0.4250
1
1
1
1
0
0
0.4125
1
1
1
1
0
1
0.4000
1
1
1
1
1
0
0.3875
1
1
1
1
1
1
0.3750
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) The voltage above are load independent for desktop and server platforms. For mobile platforms the voltage above
correspond to zero load current.
www.richtek.com
16
DS8841-01 April 2011
RT8841
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
VIDSEL
VID DAC Selection Pin.
2
FBRTN
Negative remote sense pin of output voltage.
3
SS/EN
Connect this pin to GND by a capacitor to adjust soft start time.
Pull this pin to GND to disable controller.
4
ADJ
Connect this pin to GND by a resistor to set loadline.
5
COMP
Output of error-amp and input of PWM comparator.
6
FB
Inverting input of error-amp.
7
OFS
Connect this pin to GND by a resistor to set no-load offset voltage.
8
RT
Connect this pin to GND by a resistor to adjust frequency.
9
IMAX
Negative input of OCP comparator. (Positive input of OCP
comparator is ADJ).
10
GND
Ground Pin.
11,14,15,18
ISP4, ISP3, ISP2, ISP1 Positive current sense pin of channel 1, 2, 3 and 4.
12,13,16,17
ISN4, ISN3, ISN2, ISN1 Negative current sense pin of channel 1, 2, 3 and 4.
19
VCC5
5V LDO output for system power supply pin.
20,21
PWM4, PWM3
PWM output for channel 4 and channel 3.
22,30
BOOT2, BOOT1
Bootstrap supply for channel 2 and channel 1.
23,29
UGATE2, UGATE1
Upper gate driver for channel 2 and channel 1.
24,28
PHASE2, PHASE1
Switching node of channel 2 and channel 1.
25,27
LGATE2, LGATE1
Lower gate driver for channel 2 and channel 1.
26
VCC12
IC power supply. Connect to 12V.
31
PWRGD
Power good indicator.
32
EN/VTT
VTT voltage detector input.
VID7 to VID0
Voltage identification input for DAC.
33 to 40
41 (Exposed pad)
GND
Exposed pad should be soldered to PCB board and connected to
GND.
VID Table Selection
VIDSEL
VID [7]
Table
VTT
X
VR11
GND
X
VR10.x
VCC5
VTT
K8
VCC5
GND
K8_M2
DS8841-01 April 2011
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17
RT8841
Function Block Diagram
Modulator
Waveform
Generator
RT
VCC12
Power-On
Reset
POR
5V
Regulator
COMP
VCC5
EA
+
FB
BOOT1
Offset
OFS
MOSFET
Driver
+
-
UGATE1
PHASE1
LGATE1
+
OV
+
150mV
BOOT2
+
MOSFET
Driver
Transient
Response
Enhancement
PWM3
-
SS/EN
EN/VTT
+
PHASE2
LGATE2
+
OV
OC
VIDOFF
POR
UGATE2
Soft Start
and
Fault
Logic
CH3_EN
Detector
+
PWM4
-
CH4_EN
Detector
+
-
+
VID
Table
Generator
-
I_SEN2
+
VIDSEL
VID7 to VID0
FBRTN
-
-
I_SEN3
+
+
-
OC
+
-
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18
CH1
Current
SENSE
CH2
Current
SENSE
ISP1
ISN1
ISP2
ISN2
AVG
ADJ
IMAX
I_SEN1
+
850mV
I_SEN4
CH3
Current
SENSE
CH4
Current
SENSE
ISP3
ISN3
ISP4
ISN4
DS8841-01 April 2011
RT8841
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
z
z
(Note 1)
Supply Input Voltage ------------------------------------------------------------------------------------------------------- −0.3V to 15V
BOOTx to PHASEx -------------------------------------------------------------------------------------------------------- −0.3V to 15V
BOOTx to GND
DC --------------------------------------------------------------------------------------------------------------------------- −0.3V to 30V
<200ns --------------------------------------------------------------------------------------------------------------------- −0.3V to 42V
PHASEx to GND
DC --------------------------------------------------------------------------------------------------------------------------- −2V to 15V
<200ns --------------------------------------------------------------------------------------------------------------------- −5V to 30V
Input/Output Voltage ------------------------------------------------------------------------------------------------------- −0.3V to 7V
Power Dissipation, PD @ TA = 25°C
WQFN−40L 6x6 ------------------------------------------------------------------------------------------------------------- 2.778W
Package Thermal Resistance (Note 2)
WQFN-40L 6x6, θJA -------------------------------------------------------------------------------------------------------- 36°C/W
Junction Temperature ------------------------------------------------------------------------------------------------------ 150°C
Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------- 260°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------------ 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
z
z
z
(Note 4)
Supply Voltage, VCC12 -------------------------------------------------------------------------------------------------- 12V ± 10%
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------------- 0°C to 70°C
Electrical Characteristics
(VCC12 = 12V, VGND = 0V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
12
6
13.2
--
V
mA
VCC12 Supply Input
VCC12 Supply Voltage
VCC12 Supply Current
VCC5 power
VCC5 Supply Voltage
VVCC12
ICC
No switching
10.8
--
VVCC5
ILOAD = 10mA
4.75
5.0
5.25
V
VCC5 Output Sourcing
Power-On Reset
VCC12 Rising Threshold
VCC12 Hysteresis
EN/VTT
EN/VTT Rising Threshold
Enable Hysteresis
IVCC5
10
--
--
mA
VVCC12TH
VVCC12HY
VCC12 Rising
VCC12 Falling
9.2
--
9.6
0.9
10.0
--
V
V
VENVTT
VENVTTHY
EN/VTT Rising
EN/VTT Falling
0.80
--
0.85
100
0.90
--
V
mV
0.8V to 1.6V
−5
--
+5
0.5V to 0.8V
−8
--
+8
Reference Voltage accuracy
DAC Accuracy
mV
To be continued
DS8841-01 April 2011
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19
RT8841
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Error Amplifier
DC Gain
Gain-Bandwidth
ADC
GBW
No Load
CLOAD = 10pF
---
80
10
---
dB
MHz
Slew Rate
Output voltage range
SR
VCOMP
CLOAD = 10pF
10
0.5
--
-3.6
V/us
V
Max Current
IEA_SLEW
Slew
300
--
--
uA
PWRGD Low Voltage
Soft-Start Delay
V BOOT Duration
VPGOOD
TD1
TD3
IPWRGD = 4mA
----
-2
0.8
0.4
---
V
ms
ms
PWRGD Delay
TD5
Measured the time form V BOOT change
to PWRGD = 1
--
1.6
--
ms
Max Current
IGMMAX
VCSP = 1.3V
Sink Current from CSN
100
--
--
uA
Input Offset Voltage
Running Frequency
RT Pin Voltage
Ramp Amplitude
Soft Start
Soft Start Current
VID change Current
Gate Driver
VOSCS
fOSC
VRT
VRAMP
RRT = 40kΩ
RRT = 40kΩ
RRT = 40kΩ
−1.5
270
1.52
--
0
300
1.60
1.60
1.5
330
1.68
--
mV
kHz
V
V
ISS1
ISS2
Slew
Slew
13
130
16
160
19
190
uA
uA
UGATE Drive Source
RUGATEsr
--
1
--
Ω
UGATE Drive Sink
RUGATEsk
--
1
--
Ω
LGATE Drive Source
LGATE Drive Sink
Protection
Over-Voltage Threshold
Over-Current Threshold
Dynamic Characteristic
UGATE Rise Time
UGATE Fall Time
LGATE Rise Time
LGATE Fall Time
Input Threshold
VID7 to VID0,
VIDSEL Rising Threshold
RLGATEsr
RLGATEsk
BOOT − PHASE = 8V
250mA Source Current
BOOT − PHASE = 8V
250mA Sink Current
VLGATE = 8V
250mA Sink Current
---
1
0.8
---
Ω
Ω
VOVP
VOCP
Sweep FB Voltage, VFB,EAP
Sweep IMAX Voltage, VIMAX,ADJ
125
−13
150
0
175
+13
mV
mV
Ciss = 3000p
-----
15
10
15
10
-----
ns
ns
ns
ns
VID7 to VID0 Rising,
VIDSEL Rising
--
1/2V TT +
12.5mV
--
V
VID7 to VID0 Falling,
VIDSEL Falling
--
25
--
mV
Power Sequence
Current Sense Amplifier
VID7 to VID0,
VIDSEL Hysteresis
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20
trUGATE
tfUGATE
trLGATE
tfLGATE
VID7 to 0 ,
VIDSEL
VID7 to
0_Hy ,
VIDSEL_Hy
DS8841-01 April 2011
RT8841
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a effective single layer thermal conductivity test board of
JEDEC thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
DS8841-01 April 2011
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21
RT8841
Typical Operating Characteristics
Frequency vs. RRT
Output Voltage vs. Temperature
1200
1.324
1.323
1.322
Output Voltage (V)
Frequency (kHz)
1000
800
600
400
1.321
1.320
1.319
1.318
1.317
1.316
200
1.315
0
0
40
80
120
160
200
240
-40
280
-20
0
20
40
60
80
100
RRT (k
ohm)
(kΩ)
Temperature
Frequency vs. Temperature
Power On from VTT/EN
380
120
140
RRT = 30.1kΩ
375
Frequency (kHz)
VIN = 12V, IOUT = 0A
1.314
VOUT
(1V/Div)
370
365
VTT/EN
(1V/Div)
360
PGOOD
(1V/Div)
355
PHASE
(10V/Div)
350
VIN = 12V, VOUT = 1.4V, IOUT = 0A
345
-40
-20
0
20
40
60
80
100
120
140
Time (2ms/Div)
Temperature (°C)
Power Off from VTT/EN
VOUT
(1V/Div)
VOUT
(1V/Div)
VTT/EN
(1V/Div)
VIN
(10V/Div)
SS
(2V/Div)
PHASE
(10V/Div)
PGOOD
(2V/Div)
VIN = 12V, VOUT = 1.4V, IOUT = 0A
Time (40us/Div)
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22
Power On from VIN
PHASE
(10V/Div)
VIN = 12V, VOUT = 1.4V, IOUT = 0A
Time (4ms/Div)
DS8841-01 April 2011
RT8841
Power Off from VIN
ACLL Drop
VOUT
(1V/Div)
VOUT
(20mV/Div)
VIN
(10V/Div)
SS
(2V/Div)
PHASE
(10V/Div)
IOUT
(A)
67.5
35
IOUT = 35 to 67.5A
VIN = 12V, VOUT = 1.4V, IOUT = 0A
Time (4ms/Div)
Time (20us/Div)
ACLL Overshoot
Dynamic VID
Rising
VOUT
(20mV/Div)
IOUT
(A)
VOUT
(500mV/Div)
67.5
35
VID
(1V/Div)
IOUT = 67.5 to 35A
Time (20us/Div)
Time (40us/Div)
Dynamic VID
Output Short then Power On
Falling
VIN = 12V, VOUT = 1.4V
VOUT
(1V/Div)
VOUT
(500mV/Div)
PGOOD
(1V/Div)
SS
(2V/Div)
VID
(1V/Div)
PHASE
(10V/Div)
Time (40us/Div)
DS8841-01 April 2011
Time (1ms/Div)
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23
RT8841
Power On then Output Short
OVP
VIN = 12V, VOUT = 1.4V
VOUT
(1V/Div)
PGOOD
(1V/Div)
PGOOD
(1V/Div)
FB
(500mV/Div)
SS
(2V/Div)
SS
(2V/Div)
PHASE
(10V/Div)
PHASE
(10V/Div)
Time (1ms/Div)
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24
FB
Time (40us/Div)
DS8841-01 April 2011
RT8841
Application Information
Frequency vs. RRT
1200
Power Ready Detection
During start-up, RT8841 will detect VCC12, VCC5 and VTT.
When VCC12 > 9.6V, VCC5 > 4.6V and VTT > 0.85V POR
will go high. POR (Power On Reset) is the internal signal
to indicate all voltage powers are ready to let RT8841 and
the companioned MOSFET drivers to work properly. When
POR = L, RT8841 will try to turn off both high side and low
side MOSFETs.
V CC 12
+
9.6V
V CC 5
V TT
0.85V
600
400
200
0
0
40
80
120
160
200
240
280
RRT (k
ohm)
(kΩ)
Figure 2. RRT vs Phase Switching Frequency
Output current of OPSS (ISS) is limited and variant
CMP
POR
+
800
Soft Start
+
4.6V
CMP
1000
Frequency (kHz)
RT8841 is a 4/3/2/1-phase synchronous buck DC/DC
converter with 2 embedded MOSFET drivers. The internal
VID DAC is designed to interface with the Intel 8-bit VR11
compatible CPUs.
CMP
POR : Power On Reset
V DAC
OPSS
+
-
SSQ
-
SS
Figure 1. Circuit for Power Ready Detection
+-
EAP
(ErrorAmp positive input)
ADJ
C SS
R ADJ
NTC
Phase Detection
The number of operational phases is determined by the
internal circuitry that monitors the ISNx voltages during
start up. Normally, the RT8841 operates as a 4-phase
PWM controller. Pull ISN4 and ISP4 to VCC5 programs
3-phase operation, pull ISN3 and ISP3 to VCC5 programs
2-phase operation, and pull ISN2 and ISP2 to VCC5
programs 1-phase operation. RT8841 detects the voltage
of ISN4, ISN3 and ISN2 at POR rising edge. At the rising
edge, RT8841 detects whether the voltage of ISN4, ISN3
and ISN2 are higher than “VCC5 − 1V” respectively to
decide how many phases should be active. Phase
detection is only active during start up. When POR = H,
the number of operational phases is determined and
latched. The unused PWM pin can be connected to 5V,
GND or left open.
Phase Switching Frequency
The phase switching frequency of the RT8841 is set by
an external resistor connected from the RT pin to GND.
The frequency follows the graph in Figure 2.
DS8841-01 April 2011
Figure 4. Circuit for Soft Start and Dynamic VID
The VOUT start-up time is set by a capacitor from the SS
pin to GND. In power_on_reset state (POR = L), the SS
pin is held at GND. After power_on_reset stae (POR = H)
and an extra delay 1600us, VSS and VSSQ begin to rise till
VSSQ = VBOOT. When VSSQ = VBOOT, RT8841 stays in this
state for 800us waiting for valid VID code sent by CPU.
After receiving valid VID code, VOUT continues ramping up
or down to the voltage specified by VID code. Before
PWRGD = H, output current of OPSS (ISS) is limited to
8uA (ISS1). When PWRGD = H, ISS is limited to 80uA (ISS2).
The soft start waveform is shown in Figure 5.
VOUT will trace VEAP which is equal to “VSSQ − VADJ”.
VADJ is a small voltage signal which is proportional to
IOUT. This voltage is used to generate loadline and will be
described later. T1 is the delay time from power_on_reset
state to the beginning of VOUT rising.
T1 = 1600μs + 0.6V x CSS/ISS1
(1)
T2 is the soft start time from VOUT = 0 to VOUT = VBOOT.
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25
RT8841
T2 = VBOOT x CSS/ISS1
(2)
T3 is the dwelling time for VOUT = VBOOT. T3 = 800μs.
T4 is the soft start time from VOUT = VBOOT to VOUT =
VDAC.
T4 ~= |VDAC − VBOOT| x CSS/ISS1
VCC12
VCC5
C2
(3)
T5 is the power good delay time, T5 ~= 1600μs.
V TT
pin connects to the negative remote sense pin of CPU
(VCCN) directly. The ErrorAmp compares EAP (= VDAC −
VADJ) with the VFB to regulate the output voltage.
C FB
R FB
V CCP
(Positive remote
sense pin of CPU)
0.85V
(Negative remote
sense pin of CPU)
V CCN
V DAC
IOFSP
SS
SSQ
T1
T2
T3
T4
T5
+
V DAC
+EAP
EA
+
COMP
-
FBRTN
IOFSN
R ADJ
SS
SSQ
VBOOT
PWRGD
FB
9.6V
4.6V
C1
R1
ADJ
Figure 6. Circuit for VOUT Differential Sensing and No
Load Offset
Figure 5. Soft Start Waveforms
No-Load Offset
Dynamic VID
The RT8841 can accept VID input changing while the
controller is running. This allows the output voltage (VOUT)
to change while the DC/DC converter is running and
supplying current to the load. This is commonly referred
to as VID on-the-fly (OTF). A VID OTF can occur under
either light or heavy load conditions. The CPU changes
the VID inputs in multiple steps from the start code to the
finish code. This change can be positive or negative.
Theoretically, VOUT should follow VDAC which is a staircase
waveform. In RT8841, as mentioned in soft start session,
VDAC slew rate is limited by ISS2/CSS when PWRGD = H.
This slew rate limiter works as a low pass filter of VDAC
and makes the bandwidth of VDAC waveform finite. By
smoothening VDAC staircase waveform, VOUT will no longer
overshoot or undershoot. On the other hand, CSS will
increase the settling time of VOUT during VID OTF. In most
cases, 1nF to 30nF ceramic capacitor is suitable for CSS.
Output Voltage Differential Sensing
The RT8841 uses differential sensing by a high gain low
offset ErrorAmp. The CPU voltage is sensed between the
FB and FBRTN pins. A resistor (RFB) connects FB pin and
In Figure 6, IOFSN or IOFSP are used to generate no-load
offset. Either IOFSN or IOFSP is active during normal operation.
It should be noted that users can only enable one polarity
of no-load offset. Do not connect OFS pin to GND and to
VCC5 at the same time. Connect a resistor from OFS pin
to GND to activate IOFSN. IOFSN flows through RADJ from
ADJ pin to GND. In this case, negative no-load offset voltage
(VOFSN) is generated.
VOFSN = IOFSN x RADJ = 0.8 x RADJ/ROFS
(4)
Connect a resistor from OFS pin to VCC5 to activate IOFSP.
IOFSP flows through RFB from the VCCP to FB pin. In this
case, positive no-load offset voltage (VOFSP) is generated.
When positive no-load offset is selected, the RT8841 will
generate another internal 8uA current source to eliminate
dead zone problem of droop function. This 8uA current
will be injected into ADJ resistors, producing a small initial
negative no-load offset. Therefore, when OFS pin is
connected to VCC5 through a resistor, the positive noload offset can be calculated as :
VOFSP = IOFSP × RFB − 8uA × RADJ
R
= 6.4 × FB − 8uA × R ADJ
ROFS
(5)
the positive remote sense pin of the CPU (VCCP). FBRTN
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26
DS8841-01 April 2011
RT8841
RT8841 provides wide range no-load positive offset for overclocking applications. The IOFSP capability can supply from
30uA to 640uA, which means in Equation (5), ROFS can
range from 240kΩ to 10kΩ. Other resistances of ROFS
exceeding this range can also provide no-load positive
offset but cannot be guaranteed by Equation (5).
Load Transient Quick Response
CFB
C2
RFB
R1 C1
IOUT
VOUT
Then the output current of CSA will follow the equation
below :
IX = [IL x DCR − VOFS-CSA + 235n x (RCSP − RCSN)]/RCSN
235nA is typical value of CSA input offset current.
VOFS-CSA is the input offset voltage of CSA. VOFS-CSA of
RT8841 is smaller than +/- 1mV. Usually, “VOFS-CSA +
235n x (RCSP − RCSN)” is negligible except at very light
load and the equation can be simplified as the equation
below :
IX = IL x DCR/RCSN
VOUT
FB
FB
EAP = VQR - VADJ
COMP
-
-
+
+
EAP - VQR
QR
FB
= VEAP
L
RS
QR
Figure 7. Load Transient Quick Response
CSA: Current Sense Amplifier
IX
V OFS_CSA
In steady state, the voltage of VFB is controlled to be very
close to VEAP. While a load step transient from light load
to heavy load could cause VFB lower than VEAP by several
tens of mV. In prior design, owing to limited control
bandwidth, controller is hard to prevent VOUT undershoot
during quick load transient from light load to heavy load.
RT8841 detects load transient by comparing VFB and VEAP.
If VFB suddenly drops below “VEAP − VQR”, VQR is a
predetermined voltage. The quick response indicator QR
rises up. When QR = H, RT8841 turns on all high side
MOSFETs and turn off all low side MOSFETs. The
sensitivity of quick response can be adjusted by the values
of CFB and RFB. Smaller RFB and/or larger CFB will make
QR easier to be triggered. Figure 7 is the circuit and typical
waveforms.
Output Current Sensing
The RT8841 provides low input offset current-sense
amplifier (CSA) to monitor the output current of every
channel. Output current of CSA (IX[n]) is used for channel
current balance and active voltage position. In this inductor
current sensing topology, RS and CS must be set according
to the equation below :
DS8841-01 April 2011
ISP
R CSP
ISN
R CSN
CS
+
235nA
+
-
L/DCR = RS x CS
DCR
= VEAP - VQR
235nA
Figure 8. Circuit for Channel Current Sensing
Loadline
Output current of CSA is summed and averaged in
RT8841. Then 0.5Σ(IX[n]) is sent to ADJ pin. Because
ΣIX[n] is a PTC (Positive Temperature Coefficient) current,
an NTC (Negative Temperature Coefficient) resistor is
needed to connect ADJ pin to GND. If the NTC resistor is
properly selected to compensate the temperature
coefficient of I X[n], the voltage on ADJ pin will be
proportional to IOUT without temperature effect. In RT8841,
the positive input of ErrorAmp is “VDAC − VADJ”. VOUT will
follow “VDAC − VADJ”, too. Thus, the output voltage
decreasing linearly with IOUT is obtained. The loadline is
defined as
LL(loadline) = ΔVOUT/ΔIOUT = ΔVADJ/ΔIOUT
= 0.5 x DCR x RADJ/RCSN
Briefly, the resistance of RADJ sets the resistance of
loadline. The temperature coefficient of RADJ compensates
the temperature effect of loadline.
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27
RT8841
Current Balance
COMP
RAMP[1]
Interleaved
+
-
+
CMP
-
BUF
PWM[1]
+
CMP
-
BUF
PWM[n]
IERR[1] x R CB
RAMP[n]
+
-
If the initial current distribution is constant ratio type,
according to Equation(8), reduce RCSN[1] can reduce IL[1]
and improve current balance. If the initial current distribution
is constant difference type, according to Equation(7),
increase RCSP[1] can reduce IL[1] and improve current
balance.
Over Current Protection (OCP)
IERR[n] x R CB
V CC 5
Figure 9. Circuit for Channel Current Balance
R1
In Figure 8, IX[n] is the current signal which is proportional
to current flowing through channel n. In Figure 9, the
current error signals IERR[n] (= IX[n] − AVG(IX[n])) are used
to raise or lower the internal sawtooth waveforms
(RAMP[1] to RAMP[n]) which are compared with ErrorAmp
output (COMP) to generate PWM signal. The raised
sawtooth waveform will decrease the PWM duty of the
corresponding channel while the lowered will increase.
Eventually, current flowing through each channel will be
balanced.
Channel Current Adjust
If channel current is not balanced due to asymmetric PCB
layout of power stage, external resistors can be adjusted
to correct current imbalance. Figure 10 shows two types
of current imbalance, constant ratio type and constant
difference type.
I1
I2
IOUT , total
Constant ratio
I1
I2
IOUT, total
Constant difference
Figure 10. Channel Current vs. Total Current
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28
ADJ
IMAX
+
CMP
-
OCP
R2
Figure 11. Over Current Protection
In Figure 11, VIMAX is equal to 5V x R2/(R1 + R2). In
RT8841, VADJ is proportional to IOUT and is thermally
compensated. Once VADJ is larger than VIMAX, OCP is
triggered and latched. RT8841 will turn off both high side
MOSFET and low side MOSFET of all channels. A 20uS
delay is used in OCP detection circuit to prevent false
trigger.
Over Voltage Protectiom (OVP)
The over voltage protection monitors the output voltage
via the FB pin. Once VFB exceeds “VEAP + 150mV”, OVP
is triggered and latched. RT8841 will try to turn on low
side MOSFET and turn off high side MOSFET to protect
CPU. A 20μs delay is used in OVP detection circuit to
prevent false trigger.
Loop Compensation
The RT8841 is a synchronous Buck converter with two
control loops : voltage loop and current balance loop. Since
the function of the current balance loop is to maintain the
current balance between each active channel, its influence
to converter stability will be negligible compared with the
voltage feedback loop. Therefore, to compensate the
voltage loop will be the main task to maintain converter
stability.
The converter duty-to-output transfer function Gd is :
VOUT
D
Gd =
S
S2
1+
+
2
R L ⎛ 1 ⎞
C ⎜
⎟
⎝ LC ⎠
DS8841-01 April 2011
RT8841
and the modulator gain of the converter is :
Fm = 1
VP
Where VOUT is the output voltage of the converter, R is
the loading resistance, L and C are the output inductance
and capacitance, and VP is the peak-to-peak voltage of
ramp applied at modulator input. The overall loop gain after
compensation can be described as :
Loop Gain = T = Gd x Fm x A
Where A denotes as compensation gain. To compensate
a typical voltage mode buck converter, there are two
ordinary compensation schemes, well known as type-II
compensator and type-III compensator. The choice of using
type-II or type-III compensator will be up to platform
designers, and the main concern will be the position of
the capacitor ESR zero and mid-frequency to highfrequency gain boost. Typically, the ESR zero of output
capacitor will tend to stabilize the effect of output LC double
poles, hence the positon of the output capacitor ESR zero
in frequency domain may influence the design of voltage
loop compensation. If FZERO,ESR is <1/2FCO where FCO
denotes cross-over frequency, type-II compensation will
be sufficient for voltage stability. If FZERO,ESR is > 1/2FCO
(or higher gain and phase margin is required at midfrequency to high-frequency), then type-III compensation
may be a better solution for voltage loop compensation.
A typical type-II compensation network is shown in
Figure 13.
C2
Then determine R2 by the boosted gain of loop gain at
crossover :
R2 = R1×
R1
FZERO, ESR =
FLC =
1
2π × RESR × C
1
2π × LC
After determining the phase margin at crossover
frequency, the position of zero and pole produced by
type-II compensation network, FZ and FP, can then be
determined. The bode plot of type-II compensation is
shown in Figure14, where
1
2π × R2 × C1
1
FP =
2π × R2 × (C1 // C2)
FZ =
FZ can be determined by the following Equation :
F
F
tan-1 ⎛⎜ CO ⎞⎟ − tan-1 ⎛⎜ Z ⎞⎟ ≥ 90D
⎝ FZ ⎠
⎝ FCO ⎠
⎛
⎞
FCO
+P.M. − tan-1 ⎜
⎟
⎝ FZERO, ESR ⎠
By properly choosing FZ to fit equation (22), C1 can then
be determined by :
C1
1
2π × R2 × FZ
and C2 can be determined by :
EA
+
+ V REF
-
Figure 13. Type-II Compensation
R1 can be determined independently from DC
considerations. Normally choose R1 that the current
passing by will be around 1mA. Therefore,
R1 =
VIN(MAX)
2
⎛ FZERO, ESR ⎞
FCO
×⎜
⎟ × FZERO, ESR
FLC
⎝
⎠
Where VIN(MAX) is the max input voltage of power stage,
VP is the peak-to-peak voltage of ramp applied at modulator
input, FZERO,ESR is the frequency of output capacitor ESR
zero, and FLC is the frequency of output LC :
C1 =
R2
VP
C2 =
1
F2CO
− 1
2π × R2 ×
FZ
C1
A typical type-III compensation contains two zeros and
two poles where the extra one zero and one pole compared
with type-II compensation are added for stabilizing the
system when ESR zero is relatively far from LC double
poles in frequency domain. Figure15. and Figure.16 shows
the typical circuit and bode plot of the type-III compensation.
VREF
1mA
DS8841-01 April 2011
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29
RT8841
After determining desired phase margin, according to the
following Equation :
FP = FP1 = FP2
⎞ ≥ P.M. + 45D
⎟
2
⎠
Gain (dB)
F
F
tan-1 ⎛⎜ CO ⎞⎟ − tan-1 ⎛⎜ Z
⎝ FZ ⎠
⎝ FCO
and
F 2
FP = CO
FZ
FZ and FP can be determined by choosing proper FCO to
FZ ratio to meet Equation (25). Again, R1 can be determined
by the Equation (16).
R2 can be determined by the following Equation :
R2 = R1×
2
VP
VIN(MAX)
F
F
× ⎛⎜ CO ⎞⎟ × Z
⎝ FLC ⎠ FCO
Frequency (Hz)
Figure 16. Bode Plot of the Type-III Compensation
Layout Considerations
For best performance of the RT8841, the following
guidelines must be strictly followed :
Other component values of the Type-III compensation can
then be calculated as :
1
2π × R2 × FZ
1
C2 =
`
Input bulk capacitors and MLCCS have to be put near
high side MOSFETs. The connection plane of input
capacitors and high side MOSFETs then can be kept as
square as possible.
`
The shape of phase planes (the connection plane
between high side MOSFETs, low side MOSFETs and
output inductors) have to be as square as possible. Long
traces, thin bars or separated islands must be avoided
in phase planes.
`
Keep snubber circuits or damping elements near its
objects. Phase RC snubbers have to be close to low
side MOSFETs, UGATE damping resistors have to be
close to high side MOSFETs, and boot to phase damping
resistors have to be close to high side MOSFETs and
phase planes. Also keep the traces of these snubbers
circuits as short as possible.
`
The area of VIN plane (power stage 12V VIN) and VOUT
plane (output bulk capacitors and inductors connection
plane) have to be as wide as possible. Long traces or
thin bars must be avoided in these planes. The plane
trace width must be wide enough to carry large input/
output current (40mil/A).
`
The following traces have to be wide and short : UGATE,
LGATE, BOOT, PHASE, and VCC12. Make sure the
width of these traces are wide enough to carry large
driving current(at least 40mil).
`
The voltage feedback loop contains two traces, VCC
and VSS, which are Kelvin sensed from CPU socket or
output capacitors. These two traces are suggested above
C1 =
Gain (dB)
2π × R2 × FP − 1
C1
1
C3 =
2π × R1× FZ
1
R3 =
2π × C3 × FP
FZ
FP
Frequency (Hz)
Figure 14. Bode Plot of Type-II Compensation
C2
C3
R3
R1
R2
C1
EA
+
+ V REF
-
Figure 15. Type-III Compensation
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30
FZ = FZ1 = FZ2
DS8841-01 April 2011
RT8841
10mil width and put away from high (di/dt) switching
elements such as high side MOSFETs, low side
MOSFETs, phase plane etc. The circuit elements of
voltage feedback loop, such as feedback loop short
resistors and voltage loop compensation RCs, have to
be kept near the RT8841 and also away from switching
elements.
`
The current sense mechanism of the RT8841 is fully
differential Kelvin sense. Therefore, the current sense
loops of the RT8841 contain two traces : the positive
traces(ISP1 to ISP4) come from the positive node of
output inductors(the node connecting phase plane) and
the negative traces (ISN1 to ISN4) come from the
negative node of output inductors(the node connecting
output plane).
DO NOT connect the current sense traces from phase
plane or output plane. Only connect these traces from
both sides of output inductors can achieve the goal of
precise Kelvin sense. The current sense feedback loops
have to be routed away from switching elements, and
the current sense RC elements have to be put near
their respective ISN or ISP pins of the RT8841 and also
away from noise switching elements. At least 10 mil
width is suggested for current sense feedback loops.
DS8841-01 April 2011
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31
RT8841
Outline Dimension
D
SEE DETAIL A
D2
L
1
E
E2
e
b
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A3
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
5.950
6.050
0.234
0.238
D2
4.000
4.750
0.157
0.187
E
5.950
6.050
0.234
0.238
E2
4.000
4.750
0.157
0.187
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 40L QFN 6x6 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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32
DS8841-01 April 2011