INTEGRATED CIRCUITS DATA SHEET SAA7126H; SAA7127H Digital video encoder Product specification File under Integrated Circuits, IC22 1999 May 31 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H FEATURES • Monolithic CMOS 3.3 V device, 5 V I2C-bus optionally • Digital PAL/NTSC encoder • System pixel frequency 13.5 MHz • 54 MHz double-speed multiplexed D1 interface capable of splitting data into two separate channels (encoded and baseband) • Macrovision Pay-per-View copy protection system rev. 7.01 and rev. 6.1 as option; ‘handsfree’ Macrovision pulse support through on-chip timer for pulse amplitude modulation; this applies to SAA7126H only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information. • Four Digital-to-Analog Converters (DACs) for CVBS (CSYNC, VBS), RED (Cr, C), GREEN (Y, VBS) and BLUE (Cb, CVBS) two times oversampled (signals in parenthesis are optionally). RED (Cr), GREEN (Y) and BLUE (Cb) signal outputs with 9-bit resolution, whereas all other signal outputs have 10-bit resolution; CSYNC is an advanced composite sync on the CVBS output for RGB display centring. • Real-time control of subcarrier • Controlled rise/fall times of output syncs and blanking • Cross-colour reduction filter • On-chip crystal oscillator (3rd-harmonic or fundamental crystal) • Closed captioning encoding and World Standard Teletext (WST) and North-American Broadcast Text System (NABTS) teletext encoding including sequencer and filter • Down mode (low output voltage) or power-save mode of DACs • Copy Generation Management System (CGMS) encoding (CGMS described by standard CPR-1204 of EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via the I2C-bus • QFP44 package. • Fast I2C-bus control port (400 kHz) The SAA7126H; SAA7127H encodes digital Cb-Y-Cr video data to an NTSC or PAL CVBS or S-video signal. Simultaneously, RGB or bypassed but interpolated Cb-Y-Cr signals are available via three additional Digital-to-Analog Converters (DACs). The circuit at a 54 MHz multiplexed digital D1 input port accepts two CCIR compatible Cb-Y-Cr data streams with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data with overlay and MPEG decoded data without overlay, whereas one data stream is latched at the rising, the other one at the falling clock edge. GENERAL DESCRIPTION • Line 23 Wide Screen Signalling (WSS) encoding • Video Programming System (VPS) data encoding in line 16 (CCIR line count) • Encoder can be master or slave • Programmable horizontal and vertical input synchronization phase • Programmable horizontal sync output phase • Internal Colour Bar Generator (CBG) It includes a sync/clock generator and on-chip DACs. ORDERING INFORMATION PACKAGE TYPE NUMBER SAA7126H SAA7127H 1999 May 31 NAME DESCRIPTION VERSION QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 2 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDA analog supply voltage 3.15 3.3 3.45 V VDDD digital supply voltage 3.0 3.3 3.6 V IDDA analog supply current − 77 100 mA IDDD digital supply current − 37 46 mA Vi input signal voltage levels TTL compatible Vo(p-p) analog output signal voltages Y, C and CVBS without load (peak-to-peak value) 1.30 1.45 1.55 V RL load resistance 75 − 300 Ω LElf(i) low frequency integral linearity error − − ±3 LSB LElf(d) low frequency differential linearity error − − ±1 LSB Tamb ambient temperature 0 − 70 °C BLOCK DIAGRAM XTALI handbook, full pagewidth RESET SDA SCL 40 VDD(I2C) SA RES 20 42 35 34 I2C-BUS INTERFACE 21 9 to 16 MP1 SAA7126H SAA7127H MP2 XCLK 43 37 4 VDDA2 VDDA4 VDDA1 VDDA3 25 28 31 36 I2C-bus control clock and timing I2C-bus control Y DATA MANAGER 8 7 LLC1 SYNC/CLOCK I2C-bus control 1 TTXRQ RCV2 XTAL 41 I2C-bus control MP7 to MP0 RCV1 Y ENCODER CbCr OUTPUT INTERFACE C 30 D 23 TTX 44 I2C-bus control I2C-bus control 26 CVBS RED GREEN Y n.c. 24, 27 5 VSSD1 18 38 VSSD3 VSSD2 6 17 39 VDDD1 VDDD3 VDDD2 19 RTCI 2 SP 3 AP Fig.1 Block diagram. 1999 May 31 3 29 RGB PROCESSOR CbCr A 22 32 33 VSSA1 VSSA3 VSSA2 MHB498 BLUE Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H PINNING SYMBOL TYPE PIN DESCRIPTION RES − 1 reserved pin; do not connect SP I 2 test pin; connected to digital ground for normal operation AP I 3 test pin; connected to digital ground for normal operation LLC1 I 4 line-locked clock input; this is the 27 MHz master clock VSSD1 − 5 digital ground 1 VDDD1 − 6 digital supply voltage 1 RCV1 I/O 7 raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal RCV2 I/O 8 raster control 2 for video port; this pin provides an HS pulse of programmable length or receives an HS pulse MP7 I 9 MP6 I 10 MP5 I 11 double-speed 54 MHz MPEG port; it is an input for “CCIR 656” style multiplexed Cb-Y-Cr data; data is sampled on the rising and falling clock edge; data sampled on the rising edge is then sent to the encoding part of the device; data sampled on the falling edge is sent to the RGB part of the device (or vice versa, depending on programming) MP4 I 12 MP3 I 13 MP2 I 14 MP1 I 15 MP0 I 16 VDDD2 − 17 digital supply voltage 2 VSSD2 − 18 digital ground 2 RTCI I 19 real-time control input (I2C-bus register SRES = 0): if the LLC1 clock is provided by an SAA7111 or SAA7151B, RTCI should be connected to the RTCO pin of the respective decoder to improve the signal quality. Sync reset input (I2C-bus register SRES = 1): a HIGH impulse resets synchronization of the encoder (first field, first line). VDD(I2C) − 20 sense input for I2C-bus voltage; connect to I2C-bus supply SA I 21 select I2C-bus address; LOW selects slave address 88H, HIGH selects slave address 8CH VSSA1 − 22 analog ground 1 for RED (Cr) (C) and GREEN (Y) (VBS) outputs RED O 23 analog output of RED (Cr) or (C) signal n.c. − 24 not connected VDDA1 − 25 analog supply voltage 1 for RED (Cr) (C) output GREEN O 26 analog output of GREEN (Y) or (VBS) signal n.c. − 27 not connected VDDA2 − 28 analog supply voltage 2 for GREEN (Y) (VBS) output BLUE O 29 analog output of BLUE (Cb) or (CVBS) signal CVBS O 30 analog output of CVBS (CSYNC) or (VBS) signal VDDA3 − 31 analog supply voltage 3 for BLUE (Cb) (CVBS) and CVBS (CSYNC) (VBS) outputs VSSA2 − 32 analog ground 2 for BLUE (Cb) (CVBS) and CVBS (CSYNC) (VBS) outputs VSSA3 − 33 analog ground 3 for the DAC reference ladder and the oscillator XTAL O 34 crystal oscillator output XTALI I 35 crystal oscillator input; if the oscillator is not used, this pin should be connected to ground VDDA4 − 36 analog supply voltage 4 for the DAC reference ladder and the oscillator 1999 May 31 4 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H SYMBOL TYPE PIN DESCRIPTION XCLK O 37 clock output of the crystal oscillator I 41 I2C-bus serial clock input SDA I/O 42 I2C-bus serial data input/output TTXRQ O 43 teletext request output, indicating when text bits are requested TTX I 44 teletext bit stream input 44 TTX handbook, full pagewidth RES 1 33 VSSA3 SP 2 32 VSSA2 AP 3 31 VDDA3 LLC1 4 30 CVBS VSSD1 5 29 BLUE SAA7126H SAA7127H VDDD1 6 28 VDDA2 RCV1 7 27 n.c. RCV2 8 26 GREEN 5 VSSA1 22 SA 21 VDD(I2C) 20 RTCI 19 VSSD2 18 VDDD2 17 MP1 15 23 RED MP0 16 MP5 11 MP2 14 24 n.c. MP3 13 25 VDDA1 MP4 12 MP7 9 MP6 10 Fig.2 Pin configuration. 1999 May 31 34 XTAL SCL 35 XTALI reset input, active LOW. After reset is applied, all digital I/Os are in input mode; PAL black burst on CVBS, VBS and C; RGB outputs set to lowest voltage. The I2C-bus receiver waits for the START condition. 36 VDDA4 40 37 XCLK I 38 VSSD3 RESET 39 VDDD3 digital supply voltage 3 40 RESET digital ground 3 39 41 SCL 38 − 42 SDA − 43 TTXRQ VSSD3 VDDD3 MHB499 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H VPS data for program dependent automatic start and stop of such featured VCR’s is loadable via the I2C-bus. FUNCTIONAL DESCRIPTION The digital video encoder encodes digital luminance and colour difference signals into analog CVBS, S-video and simultaneously RGB or Cr-Y-Cb signals. NTSC-M, PAL B/G and sub-standards are supported. The IC also contains closed caption and extended data services encoding (line 21), and supports anti-taping signal generation in accordance with Macrovision. It is also possible to load data for copy generation management system into line 20 of every field (525/60 line counting). Both interlaced and non-interlaced operation is possible for all standards. A number of possibilities are provided for setting different video parameters such as: The basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of “RS-170-A” and “ITU-R BT.470-3”. • Black and blanking level control • Colour subcarrier frequency • Variable burst amplitude etc. For ease of analog post filtering the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. During reset (RESET = LOW) and after reset is released, all digital I/O stages are set to the input mode and the encoder is set to PAL mode and outputs a ‘black burst’ signal on CVBS and S-video outputs, while RGB outputs are set to their lowest output voltages. A reset forces the I2C-bus interface to abort any running bus transfer. The total filter transfer characteristics are illustrated in Figs 3 to 8. The DACs for Y, C and CVBS are realized with full 10-bit resolution; 9-bit resolution for RGB output. The Cr-Y-Cb to RGB dematrix can be bypassed optionally in order to provide the upsampled Cr-Y-Cb input signals. Data manager In the data manager, alternatively to the external video data, a pre-defined colour look-up table located in this block can be read out in a pre-defined sequence (8 steps per active video line), achieving a colour bar test pattern generator without need for an external data source. The 8-bit multiplexed Cb-Y-Cr formats are “CCIR 656” (D1 format) compatible, but the SAV and EAV codes can be decoded optionally; when the device is operated in slave mode. Two independent data streams can be processed, one latched by the rising edge of LLC1, the other latched by the falling edge of LLC1. The purpose of that is e.g. to forward one of the data streams containing both video and On Screen Display (OSD) information to the RGB outputs, and the other stream containing video only to the encoded outputs CVBS and S-video. Encoder VIDEO PATH The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y and C signals. For optimum display of RGB signals through a euro-connector TV set, an early composite sync pulse (up to 31LLC1 clock periods) can be provided optionally on the CVBS output. Luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). After insertion of a fixed synchronization pulse tip level, in accordance with standard composite synchronization schemes, a blanking level can be set. Other manipulations used for the Macrovision anti-taping process such as additional insertion of AGC super-white pulses (programmable in height) are supported by SAA7126H only. It is also possible to connect a Philips digital video decoder (SAA7111, SAA7711A, SAA7112 or SAA7151B) to the SAA7126H; SAA7127H. Information concerning the actual subcarrier, PAL-ID and (with SAA7111 and newer types) definite subcarrier phase can be inserted via the RTCI pin, connected to the RTCO pin of a decoder. The SAA7126H; SAA7127H synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock. In order to enable easy analog post filtering, luminance is interpolated from 13.5 MHz data rate to 27 MHz data rate, providing luminance in 10-bit resolution. The transfer characteristic of the luminance interpolation filter are illustrated in Figs 5 and 6. Appropriate transients at start/end of active video and for synchronization pulses are ensured. Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using a 50 Hz field rate. 1999 May 31 6 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y and C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 3 and 4. The actual line number where data is to be encoded in, can be modified in a certain range. The amplitude, beginning and ending of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on the subcarrier. It is also possible to encode closed caption data for 50 Hz field frequencies at 32 times the horizontal line frequency. The data clock frequency is in accordance with the definition for NTSC-M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. ANTI-TAPING (SAA7126H ONLY) For more information contact your nearest Philips Semiconductors sales office. The numeric ratio between the Y and C outputs is in accordance with set standards. RGB processor TELETEXT INSERTION AND ENCODING This block contains a dematrix in order to produce red, green and blue signals to be fed to a SCART plug. Pin TTX receives a WST or NABTS teletext bitstream sampled at the LLC clock. Two protocols are provided: at each rising edge of output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at input pin TTX. Or: the signal TTXRQ performs only a single LOW-to-HIGH transition and remains at HIGH level for 360, 296 or 288 teletext bits, depending on the chosen standard. Before Y, Cb and Cr signals are de-matrixed, individual gain adjustment for Y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. The transfer curves of luminance and colour difference components of RGB are illustrated in Figs 7 and 8. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. Output interface/DACs In the output interface, encoded Y and C signals are converted from digital-to-analog in a 10-bit resolution. Y and C signals are also combined to a 10-bit CVBS signal. TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which are selectable independently for both fields. The internal insertion window for text is set to 360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Fig.14. The CVBS output occurs with the same processing delay (equal to 51 LLC clock periods, measured from MP input to the analog outputs) as the Y, C and RGB outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 15⁄16 with respect to Y and C DACs to make maximum use of conversion ranges. VIDEO PROGRAMMING SYSTEM (VPS) ENCODING Red, green and blue signals are also converted from digital-to-analog, each providing a 9-bit resolution. Five bytes of VPS information can be loaded via the I2C-bus and will be encoded in the appropriate format into line 16. Outputs of the DACs can be set together via software control to minimum output voltage (approximately 0.2 V DC) for either purpose. Alternatively, the buffers can be switched into 3-state output condition; this allows for ‘wired AND’ing with other 3-state outputs and can also be used as a power-save mode. CLOSED CAPTION ENCODER Using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. 1999 May 31 7 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H from line 0 to line 15 counted from the first serration pulse in half line steps. Synchronization The synchronization of the SAA7126H; SAA7127H is able to operate in two modes; slave mode and master mode. Whenever a synchronization information cannot be derived directly from the inputs, the SAA7126H; SAA7127H will calculate it from the internal horizontal, vertical and PAL phase. This gives good flexibility with respect to external synchronization but the circuit does not suppress illegal settings. In such an event, e.g the odd/even information may vanish as it does in the non-interlaced modes. In master mode (see Fig.10), the circuit generates all necessary timings in the video signal itself, and it can provide timing signals at the RCV1 and RCV2 ports. In slave mode, it accepts timing information either from the RCV pins or from the embedded timing data of the CCIR 656 data stream. For the SAA7126H; SAA7127H, the only difference between master and slave mode is that it ignores the timing information at its inputs in master mode. Thus, if in slave mode, any timing information is missing, the IC will continue running free without a visible effect. But there must not be any additional pulses (with wrong phase) because the circuit will not ignore them. In master mode, the line lengths are fixed to 1728 clocks at 50 Hz and 1716 clocks at 60 Hz. To allow non-interlaced frames, the field lengths can be varied by ±0.5 lines. In the event of non-interlace, the SAA7126H; SAA7127H does not provide odd/even information and the output signal does not contain the PAL ‘Bruch sequence’. At the RCV1 pin the IC can provide: In slave mode (see Fig.9), an interface circuit decides, which signal is expected at the RCV1 port and which information is taken from its active slope. The polarity can be chosen, if PRCV1 is logic 0 the rising slope will be active. • A Vertical Sync (VS) signal with 2.5 (50 Hz) or 3 (60 Hz) lines duration • An odd/even signal which is LOW in odd fields • A Field Sequence (FSEQ) signal which is HIGH in the first field of the 4 or 8 field sequence. The signal can be: • A Vertical Sync (VS) pulse; the active slope sets the vertical phase At the RCV2 pin, there is a horizontal pulse of programmable phase and duration available. This pulse can be suppressed in the programmable inactive part of a field giving a composite blank signal. • An odd/even signal; the active slope sets the vertical phase, the internal field flag to odd and optionally sets the horizontal phase The directions and polarities of the RCV ports can be chosen independently. Timing references can be found in Tables 29 and 37. • A Field Sequence (FSEQ) signal; it marks the first field of the 4 (NTSC) or 8 (PAL) field sequence. In addition to the odd/even signal, it also sets the PAL phase and optionally defines the subcarrier phase. Clock On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. The input at LLC1 can either be an external clock source or the buffered on-chip clock XCLK. The internal crystal oscillator can be run with either a 3rd-harmonic or a fundamental crystal. The horizontal phase can be set via a separate input RCV2. In the event of VS pulses at RCV1, this is mandatory. It is also possible to set the signal path to blank via this input. I2C-bus interface The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write and readable, except one read only status byte. From the CCIR 656 data stream, the SAA7126H; SAA7127H decodes only the start of the first line in the odd field. All other information is ignored and may miss. If this kind of slave mode is active, the RCV pins may be switched to output mode. The I2C-bus slave address is defined as 88H with pin 21 (SA) tied LOW and as 8CH with pin 21 (SA) tied HIGH. In slave mode, the horizontal trigger phase can be programmed to any point in the line, the vertical phase 1999 May 31 8 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H The RGB, respectively Cr-Y-Cb path features a gain setting individually for luminance (GY) and colour difference signals (GCD). Input levels and formats The SAA7126H; SAA7127H expects digital Y, Cb, Cr data with levels (digital codes) in accordance with “CCIR 601”. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. Table 1 “CCIR 601” signal component levels SIGNALS(1) COLOUR Y Cb Cr R(2) G(2) B(2) White 235 128 128 235 235 235 Yellow 210 16 146 235 235 16 Cyan 170 166 16 16 235 235 Green 145 54 34 16 235 16 Magenta 106 202 222 235 16 235 Red 81 90 240 235 16 16 Blue 41 240 110 16 16 235 Black 16 128 128 16 16 16 Notes 1. Transformation: a) R = Y + 1.3707 × (Cr − 128) b) G = Y − 0.3365 × (Cb − 128) − 0.6982 × (Cr − 128) c) B = Y + 1.7324 × (Cb − 128). 2. Representation of R, G and B (or Cr, Y and Cb) at the output is 9 bits at 27 MHz. Table 2 8-bit multiplexed format (similar to “CCIR 601” ) BITS TIME Sample Luminance pixel number 0 1 2 3 4 5 6 7 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 0 Colour pixel number 1999 May 31 1 0 9 2 3 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Slave receiver (slave address 88H) REGISTER FUNCTION Status byte (read only) Null Wide screen signal Wide screen signal 10 D6 D5 D4 D3 D2 D1 D0 00H 01H to 25H VER2 0 VER1 0 VER0 0 CCRDO 0 CCRDE 0 0 0 FSEQ 0 O_E 0 26H 27H WSS7 WSSON WSS6 0 WSS5 WSS13 WSS4 WSS12 WSS3 WSS11 WSS2 WSS10 WSS1 WSS9 WSS0 WSS8 28H 29H 2AH 2BH 2CH 2DH 2EH to 37H 38H 39H 3AH 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH DECCOL SRES CG07 CG15 CGEN VBSEN1 0 0 0 CBENB VPSEN VPS57 VPS117 VPS127 VPS137 VPS147 CHPS7 GAINU7 GAINV7 GAINU8 DECFIS 0 CG06 CG14 0 VBSEN0 0 0 0 0 CCIRS VPS56 VPS116 VPS126 VPS136 VPS146 CHPS6 GAINU6 GAINV6 DECOE BS5 BE5 CG05 CG13 0 CVBSEN 0 0 0 0 0 VPS55 VPS115 VPS125 VPS135 VPS145 CHPS5 GAINU5 GAINV5 BLCKL5 BS4 BE4 CG04 CG12 0 CEN 0 GY4 GCD4 SYMP 0 VPS54 VPS114 VPS124 VPS134 VPS144 CHPS4 GAINU4 GAINV4 BLCKL4 BS3 BE3 CG03 CG11 CG19 CVBSTRI 0 GY3 GCD3 DEMOFF 0 VPS53 VPS113 VPS123 VPS133 VPS143 CHPS3 GAINU3 GAINV3 BLCKL3 BS2 BE2 CG02 CG10 CG18 RTRI 0 GY2 GCD2 CSYNC 0 VPS52 VPS112 VPS122 VPS132 VPS142 CHPS2 GAINU2 GAINV2 BLCKL2 BS1 BE1 CG01 CG09 CG17 GTRI 0 GY1 GCD1 MP2C2 EDGE2 VPS51 VPS111 VPS121 VPS131 VPS141 CHPS1 GAINU1 GAINV1 BLCKL1 BS0 BE0 CG00 CG08 CG16 BTRI 0 GY0 GCD0 MP2C1 EDGE1 VPS50 VPS110 VPS120 VPS130 VPS140 CHPS0 GAINU0 GAINV0 BLCKL0 5EH GAINV8 DECPH BLNNL5 BLNNL4 BLNNL3 BLNNL2 BLNNL1 BLNNL0 5FH 60H 61H CCRS1 0 DOWNB CCRS0 0 DOWNA BLNVB5 0 INPI BLNVB4 0 YGS BLNVB3 0 0 BLNVB2 0 SCBW BLNVB1 0 PAL BLNVB0 0 FISE Product specification D7 SAA7126H; SAA7127H Real-time control, burst start Sync reset enable, burst end Copy generation 0 Copy generation 1 CG enable, copy generation 2 Output port control Null Gain luminance for RGB Gain colour difference for RGB Input port control 1 VPS enable, input control 2 VPS byte 5 VPS byte 11 VPS byte 12 VPS byte 13 VPS byte 14 Chrominance phase Gain U Gain V Gain U MSB, real-time control, black level Gain V MSB, real-time control, blanking level CCR, blanking level VBI Null Standard control DATA BYTE(1) SUB ADDR (HEX) Philips Semiconductors Table 3 Digital video encoder 1999 May 31 Bit allocation map This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D4 D3 D2 D1 D0 RTC enable, burst amplitude Subcarrier 0 62H 63H RTCE FSC07 BSTA6 FSC06 BSTA5 FSC05 BSTA4 FSC04 BSTA3 FSC03 BSTA2 FSC02 BSTA1 FSC01 BSTA0 FSC00 Subcarrier 1 Subcarrier 2 Subcarrier 3 Line 21 odd 0 Line 21 odd 1 Line 21 even 0 Line 21 even 1 RCV port control 64H 65H 66H 67H 68H 69H 6AH 6BH FSC15 FSC23 FSC31 L21O07 L21O17 L21E07 L21E17 SRCV11 FSC14 FSC22 FSC30 L21O06 L21O16 L21E06 L21E16 SRCV10 FSC13 FSC21 FSC29 L21O05 L21O15 L21E05 L21E15 TRCV2 FSC12 FSC20 FSC28 L21O04 L21O14 L21E04 L21E14 ORCV1 FSC11 FSC19 FSC27 L21O03 L21O13 L21E03 L21E13 PRCV1 FSC10 FSC18 FSC26 L21O02 L21O12 L21E02 L21E12 CBLF FSC09 FSC17 FSC25 L21O01 L21O11 L21E01 L21E11 ORCV2 FSC08 FSC16 FSC24 L21O00 L21O10 L21E00 L21E10 PRCV2 Trigger control Trigger control Multi control Closed caption, teletext enable RCV2 output start RCV2 output end MSBs RCV2 output TTX request H start TTX request H delay, length CSYNC advance, Vsync shift TTX odd request vertical start TTX odd request vertical end TTX even request vertical start TTX even request vertical end First active line Last active line TTX mode, MSB vertical Null Disable TTX line Disable TTX line 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH HTRIG1 VTRIG1 FLC1 SCCLN1 RCV2S1 RCV2E1 RCV2S9 TTXHS1 TTXHD1 VS_S1 TTXOVS1 TTXOVE1 TTXEVS1 TTXEVE1 FAL1 LAL1 TTXEVS8 0 LINE6 LINE14 HTRIG0 VTRIG0 FLCO SCCLN0 RCV2S0 RCV2E0 RCV2S8 TTXHS0 TTXHD0 VS_S0 TTXOVS0 TTXOVE0 TTXEVS0 TTXEVE0 FAL0 LAL0 TTXOVS8 0 LINE5 LINE13 HTRIG7 HTRIG6 HTRIG5 HTRIG4 HTRIG3 HTRIG2 HTRIG10 HTRIG9 HTRIG8 VTRIG4 VTRIG3 VTRIG2 SBLBN BLCKON PHRES1 PHRES0 LDEL1 LDEL0 CCEN1 CCEN0 TTXEN SCCLN4 SCCLN3 SCCLN2 RCV2S7 RCV2S6 RCV2S5 RCV2S4 RCV2S3 RCV2S2 RCV2E7 RCV2E6 RCV2E5 RCV2E4 RCV2E3 RCV2E2 0 RCV2E10 RCV2E9 RCV2E8 0 RCV2S10 TTXHS7 TTXHS6 TTXHS5 TTXHS4 TTXHS3 TTXHS2 TTXHL3 TTXHL2 TTXHL1 TTXHL0 TTXHD3 TTXHD2 CSYNCA4 CSYNCA3 CSYNCA2 CSYNCA1 CSYNCA0 VS_S2 TTXOVS7 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVS3 TTXOVS2 TTXOVE7 TTXOVE6 TTXOVE5 TTXOVE4 TTXOVE3 TTXOVE2 TTXEVS7 TTXEVS6 TTXEVS5 TTXEVS4 TTXEVS3 TTXEVS2 TTXEVE7 TTXEVE6 TTXEVE5 TTXEVE4 TTXEVE3 TTXEVE2 FAL7 FAL6 FAL5 FAL4 FAL3 FAL2 LAL7 LAL6 LAL5 LAL4 LAL3 LAL2 TTX60 LAL8 TTXO FAL8 TTXEVE8 TTXOVE8 0 0 0 0 0 0 LINE12 LINE11 LINE10 LINE9 LINE8 LINE7 LINE20 LINE19 LINE18 LINE17 LINE16 LINE15 Note 1. All bits labelled ‘0’ are reserved. They must be programmed with logic 0. Product specification D5 SAA7126H; SAA7127H D6 Philips Semiconductors 11 D7 Digital video encoder 1999 May 31 DATA BYTE(1) SUB ADDR (HEX) REGISTER FUNCTION Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H I2C-bus format I2C-bus address; see Table 5 Table 4 S SLAVE ADDRESS Table 5 ACK SUBADDRESS ACK DATA 0 ACK -------- DATA n ACK P Explanation of Table 4 PART DESCRIPTION S START condition Slave address 1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X; note 1 ACK acknowledge, generated by the slave Subaddress; note 2 subaddress byte DATA data byte -------- continued data bytes and ACKs P STOP condition Notes 1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read. 2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed. Slave receiver Table 6 Subaddresses 26H and 27H DATA BYTE LOGIC LEVEL − WSS DESCRIPTION wide screen signalling bits 3 to 0 = aspect ratio 7 to 4 = enhanced services 10 to 8 = subtitles 13 to 11 = reserved WSSON Table 7 0 wide screen signalling output is disabled; default after reset 1 wide screen signalling output is enabled Subaddress 28H DATA BYTE BS LOGIC LEVEL − DESCRIPTION REMARKS starting point of burst in clock cycles PAL: BS = 33 (21H); default after reset NTSC: BS = 25 (19H) DECCOL DECFIS 1999 May 31 0 disable colour detection bit of RTCI input 1 enable colour detection bit of RTCI input 0 field sequence as FISE in subaddress 61 1 field sequence as FISE bit in RTCI input 12 bit RTCE must be set to logic 1 (see Fig.13) bit RTCE must be set to logic 1 (see Fig.13) Philips Semiconductors Product specification Digital video encoder Table 8 SAA7126H; SAA7127H Subaddress 29H DATA BYTE LOGIC LEVEL − BE DESCRIPTION REMARKS ending point of burst in clock cycles PAL: BE = 29 (1DH); default after reset NTSC: BE = 29 (1DH) SRES Table 9 0 pin 19 is Real-Time Control Input (RTCI) 1 pin 19 is Sync Reset input (SRES) a HIGH impulse resets synchronization of the encoder (first field, first line) Subaddresses 2AH to 2CH DATA BYTE LOGIC LEVEL DESCRIPTION CG − LSB of the respective bytes are encoded immediately after run-in, the MSBs of the respective bytes have to carry the CRCC bits, in accordance with the definition of copy generation management system encoding format. CGEN 0 copy generation data output is disabled; default after reset 1 copy generation data output is enabled Table 10 Subaddress 2DH DATA BYTE BTRI GTRI RTRI CVBSTRI CEN CVBSEN VBSEN0 VBSEN1 1999 May 31 LOGIC LEVEL DESCRIPTION 0 DAC for BLUE output in 3-state mode (high-impedance) 1 DAC for BLUE output in normal operation mode; default after reset 0 DAC for GREEN output in 3-state mode (high-impedance) 1 DAC for GREEN output in normal operation mode; default after reset 0 DAC for RED output in 3-state mode (high-impedance) 1 DAC for RED output in normal operation mode; default after reset 0 DAC for CVBS output in 3-state mode (high-impedance) 1 DAC for CVBS output in normal operation mode; default after reset 0 RED output signal is switched to R DAC; default after reset 1 chrominance output signal is switched to R DAC 0 BLUE output signal is switched to B DAC; default after reset 1 CVBS output signal is switched to B DAC 0 if CSYNC = 0, CVBS output signal is switched to CVBS DAC; default after reset 1 if CSYNC = 0, luminance (VBS) output signal is switched to CVBS DAC 0 GREEN output signal is switched to G DAC; default after reset 1 luminance (VBS) output signal is switched to G DAC 13 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Table 11 Subaddresses 38H and 39H DATA BYTE DESCRIPTION GY0 to GY4 gain luminance of RGB (Cr, Y and Cb) output, ranging from (1 − 16⁄32) to (1 + 15⁄32). Suggested nominal value = −6 (11010b), depending on external application. GCD0 to GCD4 gain colour difference of RGB (Cr, Y and Cb) output, ranging from (1 − 16⁄32) to (1 + 15⁄32). Suggested nominal value = −6 (11010b), depending on external application. Table 12 Subaddress 3AH DATA BYTE MP2C1 MP2C2 CSYNC DEMOFF SYMP CBENB LOGIC LEVEL DESCRIPTION 0 input data is twos complement from MP1 input port (encoder path) 1 input data is straight binary from MP1 input port; default after reset 0 input data is twos complement from MP2 input port (RGB path) 1 input data is straight binary from MP2 input port; default after reset 0 If VBSEN0 = 0, CVBS output signal is switched to CVBS DAC. If VBSEN0 = 1, luminance output signal is switched to CVBS DAC; default after reset. 1 advanced composite sync is switched to CVBS DAC 0 Y, Cb and Cr for RGB dematrix is active; default after reset 1 Y, Cb and Cr for RGB dematrix is bypassed 0 horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default after reset 1 horizontal and vertical trigger is decoded out of “CCIR 656” compatible data at MP port 0 data from input ports is encoded; default after reset 1 colour bar with fixed colours is encoded Table 13 Subaddress 54H DATA BYTE EDGE1 EDGE2 CCIRS VPSEN 1999 May 31 LOGIC LEVEL DESCRIPTION 0 MP1 data is sampled on the rising clock edge; default after reset 1 MP1 data is sampled on the falling clock edge 0 MP2 data is sampled on the rising clock edge; default after reset 1 MP2 data is sampled on the falling clock edge 0 If SYMP = 1, horizontal and vertical trigger is decoded out of “CCIR 656” compatible data at MP2 port; default after reset. 1 If SYMP = 1, horizontal and vertical trigger is decoded out of “CCIR 656” compatible data at MP1 port. 0 video programming system data insertion is disabled; default after reset 1 video programming system data insertion in line 16 is enabled 14 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Table 14 Subaddresses 55H to 59H DATA BYTE DESCRIPTION REMARKS VPS5 fifth byte of video programming system data VPS11 eleventh byte of video programming system data VPS12 twelfth byte of video programming system data VPS13 thirteenth byte of video programming system data VPS14 fourteenth byte of video programming system data LSBs of the respective bytes are encoded immediately after run-in and framing code in line 16; all other bytes are not relevant for VPS Table 15 Subaddress 5AH DATA BYTE CHPS DESCRIPTION VALUE phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees RESULT 6BH PAL-B/G and data from input ports 95H PAL-B/G and data from look-up table A3H NTSC-M and data from input ports 46H NTSC-M and data from look-up table Table 16 Subaddresses 5BH and 5DH DATA BYTE GAINU DESCRIPTION variable gain for Cb signal; input representation in accordance with “CCIR 601” CONDITIONS REMARKS white-to-black = 92.5 IRE GAINU = −2.17 × nominal to +2.16 × nominal GAINU = 0 output subcarrier of U contribution = 0 GAINU = 118 (76H) output subcarrier of U contribution = nominal white-to-black = 100 IRE GAINU = −2.05 × nominal to +2.04 × nominal GAINU = 0 output subcarrier of U contribution = 0 GAINU = 125 (7DH) output subcarrier of U contribution = nominal Table 17 Subaddresses 5CH and 5EH DATA BYTE GAINV 1999 May 31 DESCRIPTION variable gain for Cr signal; input representation in accordance with “CCIR 601” CONDITIONS REMARKS white-to-black = 92.5 IRE GAINV = −1.55 × nominal to +1.55 × nominal GAINV = 0 output subcarrier of V contribution = 0 GAINV = 165 (A5H) output subcarrier of V contribution = nominal white-to-black = 100 IRE GAINV = −1.46 × nominal to +1.46 × nominal GAINV = 0 output subcarrier of V contribution = 0 GAINV = 175 (AFH) output subcarrier of V contribution = nominal 15 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Table 18 Subaddress 5DH DATA BYTE BLCKL DECOE DESCRIPTION CONDITIONS variable black level; input white-to-sync = 140 IRE; note 1 representation in accordance with BLCKL = 0; note 1 “CCIR 601” BLCKL = 63 (3FH); note 1 real-time control REMARKS recommended value: BLCKL = 58 (3AH) output black level = 29 IRE output black level = 49 IRE white-to-sync = 143 IRE; note 2 recommended value: BLCKL = 51 (33H) BLCKL = 0; note 2 output black level = 27 IRE BLCKL = 63 (3FH); note 2 output black level = 47 IRE logic 0 disable odd/even field control bit from RTCI logic 1 enable odd/even field control bit from RTCI (see Fig.13) Notes 1. Output black level/IRE = BLCKL × 2/6.29 + 28.9. 2. Output black level/IRE = BLCKL × 2/6.18 + 26.5. Table 19 Subaddress 5EH DATA BYTE BLNNL DECPH DESCRIPTION variable blanking level real-time control CONDITIONS REMARKS white-to-sync = 140 IRE; note 1 recommended value: BLNNL = 46 (2EH) BLNNL = 0; note 1 output blanking level = 25 IRE BLNNL = 63 (3FH); note 1 output blanking level = 45 IRE white-to-sync = 143 IRE; note 2 recommended value: BLNNL = 53 (35H) BLNNL = 0; note 2 output blanking level = 26 IRE BLNNL = 63 (3FH); note 2 output blanking level = 46 IRE logic 0 disable subcarrier phase reset bit from RTCI logic 1 enable subcarrier phase reset bit from RTCI (see Fig.13) Notes 1. Output black level/IRE = BLNNL × 2/6.29 + 25.4. 2. Output black level/IRE = BLNNL × 2/6.18 + 25.9; default after reset: 35H. Table 20 Subaddress 5FH DATA BYTE DESCRIPTION BLNVB variable blanking level during vertical blanking interval is typically identical to value of BLNNL CCRS select cross-colour reduction filter in luminance; see Table 21 1999 May 31 16 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Table 21 Logic levels and function of CCRS CCRS1 CCRS0 DESCRIPTION 0 0 no cross-colour reduction; for overall transfer characteristic of luminance see Fig.5 0 1 cross-colour reduction #1 active; for overall transfer characteristic see Fig.5 1 0 cross-colour reduction #2 active; for overall transfer characteristic see Fig.5 1 1 cross-colour reduction #3 active; for overall transfer characteristic see Fig.5 Table 22 Subaddress 61H DATA BYTE FISE PAL SCBW YGS INPI DOWNA DOWNB LOGIC LEVEL DESCRIPTION 0 864 total pixel clocks per line; default after reset 1 858 total pixel clocks per line 0 NTSC encoding (non-alternating V component) 1 PAL encoding (alternating V component); default after reset 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4) 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4); default after reset 0 luminance gain for white − black 100 IRE; default after reset 1 luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black 0 PAL switch phase is nominal; default after reset 1 PAL switch phase is inverted compared to nominal if RTC is enabled (see Table 23) 0 DAC for CVBS in normal operational mode; default after reset 1 DAC for CVBS forced to lowest output voltage 0 DACs for R, G and B in normal operational mode 1 DACs for R, G and B forced to lowest output voltage; default after reset Table 23 Subaddress 62AH DATA BYTE RTCE 1999 May 31 LOGIC LEVEL DESCRIPTION 0 no real-time control of generated subcarrier frequency; default after reset 1 real-time control of generated subcarrier frequency through SAA7151B or SAA7111; for timing see Fig.13 17 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Table 24 Subaddress 62BH DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation in accordance with “CCIR 601” CONDITIONS REMARKS white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding recommended value: BSTA = 63 (3FH) BSTA = 0 to 2.02 × nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding recommended value: BSTA = 45 (2DH) BSTA = 0 to 2.82 × nominal white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding recommended value: BSTA = 67 (43H) BSTA = 0 to 1.90 × nominal white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 × nominal recommended value: BSTA = 47 (2FH); default after reset Table 25 Subaddresses 63H to 66H (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION FSC0 to FSC3 ffsc = subcarrier frequency (in multiples of line frequency); fllc = clock frequency (in multiples of line frequency) CONDITIONS REMARKS f fsc 32 FSC = round -------- × 2 ; f llc FSC3 = most significant byte; FSC0 = least significant byte note 1 Note 1. Examples: a) NTSC-M: ffsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1FH). b) PAL-B/G: ffsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBH). Table 26 Subaddresses 67H to 6AH DATA BYTE DESCRIPTION REMARKS L21O0 first byte of captioning data, odd field L21O1 second byte of captioning data, odd field L21E0 first byte of extended data, even field L21E1 second byte of extended data, even field 1999 May 31 18 LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format. Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Table 27 Subaddress 6BH DATA BYTE LOGIC LEVEL PRCV2 ORCV2 CBLF PRCV1 ORCV1 TRCV2 SRCV1 DESCRIPTION 0 polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively; default after reset 1 polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively 0 pin RCV2 is switched to input; default after reset 1 pin RCV2 is switched to output 0 If ORCV2 = HIGH, pin RCV2 provides an HREF signal (horizontal reference pulse that is defined by RCV2S and RCV2E, also during vertical blanking interval); default after reset. If ORCV2 = LOW and bit SYMP = LOW, the signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1); default after reset. 1 If ORCV2 = HIGH, pin RCV2 provides a ‘composite-blanking-not’ signal, for example a reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking interval, which is defined by FAL and LAL. If ORCV2 = LOW and bit SYMP = LOW, the signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking signal. 0 polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after reset 1 polarity of RCV1 as output is active LOW, falling edge is taken when input 0 pin RCV1 is switched to input; default after reset 1 pin RCV1 is switched to output 0 horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded frame sync of “CCIR 656” input (at bit SYMP = HIGH); default after reset 1 horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW) − defines signal type on pin RCV1; see Table 28 Table 28 Logic levels and function of SRCV1 DATA BYTE AS OUTPUT AS INPUT 0 VS VS vertical sync each field; default after reset 1 FS FS frame sync (odd/even) 1 0 FSEQ FSEQ 1 1 not applicable not applicable SRCV11 SRCV10 0 0 FUNCTION field sequence, vertical sync every fourth field (PAL = 0) or eighth field (PAL = 1) − Table 29 Subaddresses 6CH and 6DH DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to signal on RCV1 or RCV2 input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of all internally generated timing signals; reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = 39H 1999 May 31 19 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Table 30 Subaddress 6DH DATA BYTE VTRIG DESCRIPTION sets the vertical trigger phase related to signal on RCV1 input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; variation range of VTRIG = 0 to 31 (1FH) Table 31 Subaddress 6EH DATA BYTE LOGIC LEVEL SBLBN BLCKON DESCRIPTION 0 vertical blanking is defined by programming of FAL and LAL; default after reset 1 vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz) 0 encoder in normal operation mode 1 output signal is forced to blanking level; default after reset PHRES − selects the phase reset mode of the colour subcarrier generator; see Table 32 LDEL − selects the delay on luminance path with reference to chrominance path; see Table 33 FLC − field length control; see Table 34 Table 32 Logic levels and function of PHRES DATA BYTE DESCRIPTION PHRES1 PHRES0 0 0 no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset 0 1 reset every two lines 1 0 reset every eight fields 1 1 reset every four fields Table 33 Logic levels and function of LDEL DATA BYTE DESCRIPTION LDEL1 LDEL0 0 0 no luminance delay; default after reset 0 1 1 LLC luminance delay 1 0 2 LLC luminance delay 1 1 3 LLC luminance delay Table 34 Logic levels and function of FLC DATA BYTE DESCRIPTION FLC1 FLC0 0 0 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset 0 1 non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz 1 0 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz 1 1 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz 1999 May 31 20 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Table 35 Subaddress 6FH DATA BYTE LOGIC LEVEL DESCRIPTION CCEN − enables individual line 21 encoding; see Table 36 TTXEN 0 disables teletext insertion; default after reset 1 enables teletext insertion − selects the actual line, where closed caption or extended data are encoded; line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems SCCLN Table 36 Logic levels and function of CCEN DATA BYTE DESCRIPTION CCEN1 CCEN0 0 0 line 21 encoding off; default after reset 0 1 enables encoding in field 1 (odd) 1 0 enables encoding in field 2 (even) 1 1 enables encoding in both fields Table 37 Subaddresses 70H to 72H DATA BYTE RCV2S DESCRIPTION start of output signal on RCV2 pin values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed; first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2S = 11AH [0FDH] RCV2E end of output signal on RCV2 pin values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed; last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2E = 694H (687H) Table 38 Subaddress 73H DATA BYTE TTXHS DESCRIPTION REMARKS start of signal on pin TTXRQ; see Fig.14 PAL: TTXHS = 42H NTSC: TTXHS = 54H Table 39 Subaddress 74H DATA BYTE DESCRIPTION REMARKS TTXHL length of TTXRQ window; only active at old TTX protocol: bit TTXO = 1 TTXHL = 0: TTXRQ = 1398LLC; TTXHL = 15: TTXRQ = 1413LLC TTXHD indicates the delay in clock cycles between rising edge of TTXRQ output and valid data at pin TTX minimum value: TTXHD = 2 1999 May 31 21 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Table 40 Subaddress 75H DATA BYTE VS_S DESCRIPTION vertical sync shift between RCV1 and RCV2 (switched to output); in master mode it is possible to shift H-sync (RCV2; CBLF = 0) against V-sync (RCV1; SRCV1 = 00) standard value: VS_S = 3 CSYNCA advanced composite sync against RGB output from 0LLC to 31LLC Table 41 Subaddresses 76H, 77H and 7CH DATA BYTE TTXOVS DESCRIPTION REMARKS first line of occurrence of signal on pin TTXRQ in odd field line = (TTXOVS + 4) for M-systems PAL: TTXOVS = 05H; NTSC: TTXOVS = 06H line = (TTXOVS + 1) for other systems TTXOVE last line of occurrence of signal on pin TTXRQ in odd field line = (TTXOVE + 3) for M-systems PAL: TTXOVE = 16H; NTSC: TTXOVE = 10H line = TTXOVE for other systems Table 42 Subaddresses 78H, 79H and 7CH DATA BYTE TTXEVS DESCRIPTION REMARKS first line of occurrence of signal on pin TTXRQ in even field line = (TTXEVS + 4) for M-systems PAL: TTXEVS = 04H; NTSC: TTXEVS = 05H line = (TTXEVS + 1) for other systems TTXEVE last line of occurrence of signal on pin TTXRQ in even field line = (TTXEVE + 3) for M-systems PAL: TTXEVS = 16H; NTSC: TTXEVS = 10H line = TTXEVE for other systems Table 43 Subaddress 7CH DATA BYTE TTXO TTX60 LOGIC LEVEL DESCRIPTION 0 new TTX protocol selected: at each rising edge of TTXRQ a single TTX bit is requested see Fig.14; default after reset 1 old TTX protocol selected: the encoder provides a window of TTXRQ going HIGH; the length of the window depends on the chosen TTX standard see Fig.14 0 enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset 1 enables world standard teletext 60 Hz (FISE = 1) Table 44 Subaddresses 7AH to 7CH DATA BYTE DESCRIPTION FAL first active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines LAL last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines FAL = 0 coincides with the first field synchronization pulse LAL = 0 coincides with the first field synchronization pulse 1999 May 31 22 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Table 45 Subaddresses 7EH and 7FH DATA BYTE LINE DESCRIPTION individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits, disabled line = LINExx (50 Hz field rate) this bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE In subaddresses 5BH, 5CH, 5DH, 5EH and 62H all IRE values are rounded up. Slave transmitter Table 46 Slave transmitter (slave address 89H) REGISTER FUNCTION DATA BYTE SUBADDRESS Status byte 00H D7 D6 D5 VER2 VER1 VER0 D4 D3 CCRDO CCRDE D2 D1 D0 0 FSEQ O_E Table 47 Subaddress 00H DATA BYTE LOGIC LEVEL DESCRIPTION VER − version identification of the device: it will be changed with all versions of the IC that have different programming models; current version is 000 binary CCRDO 1 closed caption bytes of the odd field have been encoded 0 the bit is reset after information has been written to the subaddresses 67H and 68H; it is set immediately after the data has been encoded 1 closed caption bytes of the even field have been encoded 0 the bit is reset after information has been written to the subaddresses 69H and 6AH; it is set immediately after the data has been encoded 1 during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields) 0 not first field of a sequence 1 during even field 0 during odd field CCRDE FSEQ O_E 1999 May 31 23 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H MBE737 handbook, full 6 pagewidth Gv (dB) 0 −6 −12 −18 −24 (1) (2) −30 −36 −42 −48 −54 0 2 4 6 8 10 (1) SCBW = 1. (2) SCBW = 0. Fig.3 Chrominance transfer characteristic 1. MBE735 handbook, halfpage 2 Gv (dB) 0 (1) (2) −2 −4 −6 0 0.4 0.8 1.2 f (MHz) 1.6 (1) SCBW = 1. (2) SCBW = 0. Fig.4 Chrominance transfer characteristic 2. 1999 May 31 24 12 f (MHz) 14 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H MGD672 6 Gv full pagewidth handbook, (dB) (4) 0 (2) (3) −6 (1) −12 −18 −24 −30 −36 −42 −48 −54 0 2 4 6 8 10 12 14 f (MHz) (1) (2) (3) (4) CCRS1 = 0; CCRS0 = 1. CCRS1 = 1; CCRS0 = 0. CCRS1 = 1; CCRS0 = 1. CCRS1 = 0; CCRS0 = 0. Fig.5 Luminance transfer characteristic 1. MBE736 handbook, halfpage 1 Gv (dB) (1) 0 −1 −2 −3 −4 −5 0 2 4 f (MHz) 6 (1) CCRS1 = 0; CCRS0 = 0. Fig.6 Luminance transfer characteristic 2. 1999 May 31 25 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H MGB708 handbook, full pagewidth Gv 6 (dB) 0 −6 −12 −18 −24 −30 −36 −42 −48 −54 0 2 4 6 8 10 12 f (MHz) 14 Fig.7 Luminance transfer characteristic in RGB. MGB706 handbook, full pagewidth Gv 6 (dB) 0 −6 −12 −18 −24 −30 −36 −42 −48 −54 0 2 4 6 8 10 Fig.8 Colour difference transfer characteristic in RGB. 1999 May 31 26 12 f (MHz) 14 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H handbook, full pagewidth CVBS output RCV2 input 55LLC MP input 51LLC MHB500 HTRIG = 0 PRCV2 = 0. TRCV2 = 1. ORCV2 = 0. Fig.9 Sync and video input timing. handbook, full pagewidth CVBS output RCV2 output MHB501 49LLC RCV2S = 0. PRCV2 = 0. ORCV2 = 1. Fig.10 Sync and video output timing. 1999 May 31 27 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H CHARACTERISTICS VDDD = 3.0 to 3.6 V; Tamb = 0 to 70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Supplies VDDA analog supply voltage 3.15 3.45 V VDDD digital supply voltage 3.0 3.6 V IDDA analog supply current note 1 − 100 mA IDDD digital supply current VDDD = 3.3 V; note 1 − 46 mA Inputs VIL LOW-level input voltage (pins LLC1, RCV1, RCV2, MP7 to MP0, RTCI, SA, RESET and TTX) −0.5 +0.8 V VIH HIGH-level input voltage (pins LLC1, RCV1, RCV2, MP7 to MP0, RTCI, SA, RESET and TTX) 2.0 VDDD + 0.3 V ILI input leakage current − 1 µA Ci input capacitance clocks − 10 pF data − 8 pF I/Os at high-impedance − 8 pF Outputs; pins RCV1, RCV2 and TTXRQ VOL LOW-level output voltage IOL = 2 mA − 0.4 V VOH HIGH-level output voltage IOH = 2 mA 2.4 − V 0.3VDD(I2C) V I2C-bus; SDA and SCL VIL LOW-level input voltage −0.5 VIH HIGH-level input voltage 0.7VDD(I2C) VDD(I2C) + 0.3 V Ii input current Vi = LOW or HIGH −10 +10 µA VOL LOW-level output voltage (pin SDA) IOL = 3 mA − 0.4 V Io output current during acknowledge 3 − mA cycle time note 2 34 41 ns Clock timing (pins LLC1 and XCLK) TLLC1 δ duty factor tHIGH/TLLC1 LLC1 input 40 60 % duty factor tHIGH/TXCLK XCLK output typical 50% 40 60 % tr rise time note 2 − 5 ns tf fall time note 2 − 6 ns Input timing; pins LLC1, RCV1, RCV2, MP7 to MP0, RTCI, SA and TTX tSU;DAT input data set-up time 6 − ns tHD;DAT input data hold time 3 − ns Crystal oscillator fn nominal frequency (usually 27 MHz) 3rd-harmonic − 30 MHz ∆f/fn permissible deviation of nominal frequency note 3 −50 +50 10−6 1999 May 31 28 Philips Semiconductors Product specification Digital video encoder SYMBOL SAA7126H; SAA7127H PARAMETER CONDITIONS MIN. MAX. UNIT CRYSTAL SPECIFICATION Tamb ambient temperature 0 70 °C CL load capacitance 8 − pF RS series resistance − 80 Ω C1 motional capacitance (typical) 1.5 − 20% 1.5 + 20% fF C0 parallel capacitance (typical) 3.5 − 20% 3.5 + 20% pF Data and reference signal output timing CL output load capacitance 7.5 40 pF th output hold time 4 − ns td output delay time − 25 ns 1.30 1.55 V CVBS and RGB outputs Vo(p-p) output signal voltage (peak-to-peak value) note 4 ∆Vo inequality of output signal voltages − 2 % Rs(int) internal serial resistance 1 3 Ω RL output load resistance 75 300 Ω B output signal bandwidth of DACs 10 − MHz −3 dB LElf(i) low frequency integral linearity error of DACs − ±3 LSB LElf(d) low frequency differential linearity error of DACs − ±1 LSB td(pipe)(MP) total pipeline delay from MP port − 51 LLC 27 MHz Notes 1. At maximum supply voltage with highly active input signals. 2. The data is for both input and output direction. 3. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 4. For full digital range, without load, VDDA = 3.3 V. The typical voltage swing is 1.45 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V. 1999 May 31 29 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H TLLC1 handbook, full pagewidth t HIGH 2.6 V 1.5 V 0.6 V XCLK tf tr TLLC1 t HIGH 2.4 V 1.5 V 0.8 V LLC1 tSU; DAT t HD; DAT tf tr 2.0 V input data valid not valid valid 0.8 V td th output data 2.4 V not valid valid valid 0.6 V MHB502 Fig.11 Clock data timing. handbook, full pagewidth LLC MP(n) Cb(0) Y(0) Cr(0) Y(1) Cb(2) RCV2 MGB699 The data demultiplexing phase is coupled to the internal horizontal phase. The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S). Fig.12 Functional timing. 1999 May 31 30 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Explanation of RTCI data bits handbook, full pagewidth H/L transition count start LOW HPLL increment (1) 128 13 3 bits reserved 4 bits reserved (4) 0 (5) (3) FSCPLL increment (2) 22 (7) (6) 0 RTCI time slot: 0 1 14 19 64 valid sample not used in SAA7126H/27H (1) (2) (3) (4) (5) (6) (7) (8) invalid sample 67 69 72 74 68 8/LLC MHB503 (8) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment. SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit. Sequence bit: PAL: 0 = (R − Y) line normal, 1 = (R − Y) line inverted; NTSC: 0 = no change. Reset bit: only from SAA7111 and SAA7112 decoder. FISE bit: 0 = 50 Hz, 1 = 60 Hz. Odd/even bit: odd_even from external. Colour detection: 0 = no colour detected, 1 = colour detected. Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems. Fig.13 RTCI timing. 1. The HPLL increment is not evaluated by SAA7126H; SAA7127H. 2. The SAA7126H; SAA7127H generates the subcarrier frequency from the FSCPLL increment if enabled (see item 7.). 3. The PAL bit indicates the line with inverted (R − Y) component of colour difference signal. 4. If the reset bit is enabled (RTCE = 1; DECPH = 1; PHRES = 00), the phase of the subcarrier is reset in each line whenever the reset bit of RTCI input is set to logic 1. 5. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the SAA7126H; SAA7127H takes this bit instead of the FISE bit in subaddress 61H. 6. If the odd/even bit is enabled (RTCE = 1; DECOE = 1), the SAA7126H; SAA7127H ignores it’s internally generated odd/even flag and takes the odd/even bit from RTCI input. 7. If the colour detection bit is enabled (RTCE = 1; DECCOL = 1) and no colour was detected (colour detection bit = 0), the subcarrier frequency is generated by the SAA7126H; SAA7127H. In the other case (colour detection bit = 1) the subcarrier frequency is evaluated out of FSCPLL increment. If the colour detection bit is disabled (RTCE = 1; DECCOL = 0), the subcarrier frequency is evaluated out of FSCPLL increment, independent of the colour detection bit of RTCI input. 1999 May 31 31 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Time ti(TTXW) is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s (world standard TTX) or 288 teletext bits at a text data rate of 5.7272 Mbits/s (NABTS). The insertion window is not opened if the control bit TTXEN is zero. Teletext timing Time tFD is the time needed to interpolate input data TTX and insert it into the CVBS and VBS output signal, such that it appears at tTTX = 9.78 µs (PAL) or tTTX = 10.5 µs (NTSC) after the leading edge of the horizontal synchronization pulse. Time td(pipe)(MP) is the pipeline delay time introduced by the source that is gated by TTXRQ in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH state at output pin TTXRQ, a new teletext bit must be provided by the source (new protocol) or a window of TTXRQ going HIGH is provided and the number of teletext bits, depending on the chosen TTX standard, is requested at input pin TTX (old protocol). Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of outgoing horizontal synchronization pulse. handbook, full pagewidth CVBS/Y t TTX text bit #: 1 t i(TTXW) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 TTX t PD t FD TTXRQ (new) TTXRQ (old) MHB504 Fig.14 Teletext timing. 1999 May 31 32 24 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 0.1 µF 0.1 µF DGND 27.0 MHz X1 AGND 0.1 µF use one capacitor for each VDDA AGND 3rd harmonic XTALI XTAL 35 34 VDDD1 to VDDD3 VDDA4 VDDA1 to VDDA3 6, 17, 39 36 25, 28, 31 use one capacitor for each VDDD DAC1 2 Ω (1) 23 RED 23 Ω 75 Ω 2 Ω (1) DAC2 26 GREEN 23 Ω 33 75 Ω digital inputs and outputs SAA7126H SAA7127H 2 Ω (1) DAC3 29 BLUE 23 Ω 75 Ω 2 Ω (1) DAC4 30 CVBS 4.7 Ω 22, 32, 33 VSSD1 to VSSD3 VSSA1 to VSSA3 DGND AGND Fig.15 Application circuit. 0.70 V (p-p)(2) AGND UG 0.70 V (p-p)(2) AGND UB 0.70 V (p-p)(2) AGND UCVBS 1.23 V (p-p)(2) AGND MHB505 Product specification (1) Typical value. (2) For 100⁄100 colour bar. UR SAA7126H; SAA7127H 75 Ω 5, 18, 38 Philips Semiconductors 1 nF 10 pF 10 pF +3.3 V analog Digital video encoder 0.1 µH APPLICATION INFORMATION ook, full pagewidth 1999 May 31 +3.3 V digital DGND Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Analog output voltages The analog output voltages are dependent on the open-loop voltage of the operational amplifiers for full-scale conversion (typical value 1.375 V), the internal series resistor (typical value 2 Ω), the external series resistor and the external load impedance. The digital output signals in front of the DACs under nominal conditions occupy different conversion ranges, as indicated in Table 48 for a 100⁄100 colour bar signal. Values for the external series resistors result in a 75 Ω load. Table 48 Digital output signals conversion range CONVERSION RANGE (peak-to-peak) CVBS, SYNC TIP-TO-PEAK CARRIER (digits) Y (VBS) SYNC TIP-TO-WHITE (digits) RGB (Y) BLACK-TO-WHITE AT GDY = GDC = −6 (digits) 1016 881 712 1999 May 31 34 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 10 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT307-2 1999 May 31 EUROPEAN PROJECTION 35 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H If wave soldering is used the following conditions must be observed for optimal results: SOLDERING Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. 1999 May 31 When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 36 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable suitable LQFP, QFP, TQFP not recommended(3)(4) suitable SSOP, TSSOP, VSO not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 1999 May 31 37 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 May 31 38 Philips Semiconductors Product specification Digital video encoder SAA7126H; SAA7127H NOTES 1999 May 31 39 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1999 SCA 65 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545006/01/pp40 Date of release: 1999 May 31 Document order number: 9397 750 05278