SM74101 SM74101 Tiny 7A MOSFET Gate Driver Literature Number: SNOSBA2 SM74101 Tiny 7A MOSFET Gate Driver General Description Features The SM74101 MOSFET gate driver provides high peak gate drive current in the tiny LLP-6 package (SOT23 equivalent footprint), with improved power dissipation required for high frequency operation. The compound output driver stage includes MOS and bipolar transistors operating in parallel that together sink more than 7A peak from capacitive loads. Combining the unique characteristics of MOS and bipolar devices reduces drive current variation with voltage and temperature. Under-voltage lockout protection is provided to prevent damage to the MOSFET due to insufficient gate turn-on voltage. The SM74101 provides both inverting and non-inverting inputs to satisfy requirements for inverting and non-inverting gate drive with a single device type. ■ Renewable Energy Grade ■ Compound CMOS and bipolar outputs reduce output ■ ■ ■ ■ ■ ■ ■ ■ current variation 7A sink/3A source current Fast propagation times (25 ns typical) Fast rise and fall times (14 ns/12 ns rise/fall with 2 nF load) Inverting and non-inverting inputs provide either configuration with a single device Supply rail under-voltage lockout protection Dedicated input ground (IN_REF) for split supply or single supply operation Power Enhanced 6-pin LLP package (3.0mm x 3.0mm) Output swings from VCC to VEE which can be negative relative to input ground Block Diagram 30159901 Block Diagram of SM74101 © 2011 National Semiconductor Corporation 301599 www.national.com SM74101 Tiny 7A MOSFET Gate Driver July 18, 2011 SM74101 Pin Configurations 30159902 LLP-6 Ordering Information Order Number Package Type NSC Package Drawing Package Marking Supplied As 1000 shipped on Tape & Reel SM74101SD LLP-6 SDE06A L264B SM74101SDE LLP-6 SDE06A L264B 250 units on Tape & Reel SM741SDX LLP-6 SDE06A L264B 4500 Units on Tape & Reel Pin Descriptions Pin Name Description Application Information 1 IN Non-inverting input pin TTL compatible thresholds. Pull up to VCC when not used. 2 VEE Power ground for driver outputs Connect to either power ground or a negative gate drive supply for positive or negative voltage swing. 3 VCC Positive Supply voltage input Locally decouple to VEE. The decoupling capacitor should be located close to the chip. 4 OUT Gate drive output Capable of sourcing 3A and sinking 7A. Voltage swing of this output is from VEE to VCC. 5 IN_REF Ground reference for control inputs Connect to power ground (VEE) for standard positive only output voltage swing. Connect to system logic ground when VEE is connected to a negative gate drive supply. 6 INB Inverting input pin TTL compatible thresholds. Connect to IN_REF when not used. Exposed Pad Exposed Pad, underside of package Internally bonded to the die substrate. Connect to VEE ground pin for low thermal impedance. --- www.national.com 2 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC to VEE VCC to IN_REF −0.3V to 15V −0.3V to 15V Electrical Characteristics −0.3V to 15V −0.3V to 5V −55°C to +150°C +150°C −40°C+125°C 2kV TJ = −40°C to +125°C, VCC = 12V, INB = IN_REF = VEE = 0V, No Load on output, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units 14 V 3.0 3.5 V SUPPLY VCC VCC Operating Range VCC – IN_REF and VCC - VEE 3.5 UVLO VCC Under-voltage Lockout (rising) VCC – IN_REF 2.4 VCCH VCC Under-voltage Hysteresis 230 ICC VCC Supply Current 1.0 mV 2.0 mA CONTROL INPUTS VIH Logic High VIL Logic Low 2.3 V VthH High Threshold 1.3 VthL Low Threshold 0.8 HYS Input Hysteresis IIL Input Current Low IN = INB = 0V -1 0.1 1 µA IIH Input Current High IN = INB = VCC -1 0.1 1 µA 0.8 V 1.75 2.3 V 1.35 2.0 V 400 mV OUTPUT DRIVER ROH Output Resistance High IOUT = -10mA (Note 2) 30 50 Ω ROL Output Resistance Low IOUT = 10mA (Note 2) 1.4 2.5 Ω ISOURCE Peak Source Current OUT = VCC/2, 200ns pulsed current 3 A ISINK Peak Sink Current OUT = VCC/2, 200ns pulsed current 7 A SWITCHING CHARACTERISTICS td1 Propagation Delay Time Low to High, IN/ INB rising ( IN to OUT) CLOAD = 2 nF, see Figure 1 25 40 ns td2 Propagation Delay Time High to Low, IN / INB falling (IN to OUT) CLOAD = 2 nF, see Figure 1 25 40 ns tr Rise time CLOAD = 2 nF , see Figure 1 14 ns tf Fall time CLOAD = 2 nF , see Figure 1 12 ns TJ = 150°C 500 mA 40 °C/W 7.5 °C/W LATCHUP PROTECTION AEC –Q100, METHOD 004 THERMAL RESISTANCE θJA Junction to Ambient, 0 LFPM Air Flow LLP-6 Package θJC Junction to Case LLP-6 Package Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The output resistance specification applies to the MOS device only. The total output current capability is the sum of the MOS and Bipolar devices. 3 www.national.com SM74101 IN/INB to IN_REF IN_REF to VEE Storage Temperature Range Maximum Junction Temperature Operating Junction Temperature ESD Rating Absolute Maximum Ratings (Note 1) SM74101 Timing Waveforms 30159905 30159904 (b) (a) FIGURE 1. (a) Inverting, (b) Non-Inverting www.national.com 4 SM74101 Typical Performance Characteristics Supply Current vs Frequency Supply Current vs Capacitive Load 30159908 30159907 Rise and Fall Time vs Supply Voltage Rise and Fall Time vs Temperature 30159909 30159910 Rise and Fall Time vs Capacitive Load Delay Time vs Supply Voltage 30159911 30159912 5 www.national.com SM74101 Delay Time vs Temperature RDSON vs Supply Voltage 30159913 30159914 UVLO Thresholds and Hysteresis vs Temperature Peak Current vs Supply Voltage 30159916 30159915 www.national.com 6 SM74101 Simplified Application Block Diagram 30159903 FIGURE 2. Simplified Application Block Diagram circuit and separate input/output ground pins provide the option of single supply or split supply configurations. When driving the MOSFET gates from a single positive supply, the IN_REF and VEE pins are both connected to the power ground. The isolated input and output stage grounds provide the capability to drive the MOSFET to a negative VGS voltage for a more robust and reliable off state. In split supply configuration, the IN_REF pin is connected to the ground of the controller which drives the SM74101 inputs. The VEE pin is connected to a negative bias supply that can range from the IN_REF potential to as low as 14 V below the Vcc gate drive supply. For reliable operation, the maximum voltage difference between VCC and IN_REF or between VCC and VEE is 14V. The minimum recommended operating voltage between Vcc and IN_REF is 3.5V. An Under Voltage Lock Out (UVLO) circuit is included in the SM74101 which senses the voltage difference between VCC and the input ground pin, IN_REF. When the VCC to IN_REF voltage difference falls below 2.8V the driver is disabled and the output pin is held in the low state. The UVLO hysteresis prevents chattering during brown-out conditions; the driver will resume normal operation when the VCC to IN_REF differential voltage exceeds 3.0V. Detailed Operating Description The SM74101 is a high speed , high peak current (7A) single channel MOSFET driver. The high peak output current of the SM74101 will switch power MOSFET’s on and off with short rise and fall times, thereby reducing switching losses considerably. The SM74101 includes both inverting and non-inverting inputs that give the user flexibility to drive the MOSFET with either active low or active high logic signals. The driver output stage consists of a compound structure with MOS and bipolar transistor operating in parallel to optimize current capability over a wide output voltage and operating temperature range. The bipolar device provides high peak current at the critical Miller plateau region of the MOSFET VGS , while the MOS device provides rail-to-rail output swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage VCC and the power ground potential at the VEE pin. The control inputs of the driver are high impedance CMOS buffers with TTL compatible threshold voltages. The negative supply of the input buffer is connected to the input ground pin IN_REF. An internal level shifting circuit connects the logic input buffers to the totem pole output drivers. The level shift 7 www.national.com SM74101 Layout Considerations Attention must be given to board layout when using SM74101. Some important considerations include: 1. A Low ESR/ESL capacitor must be connected close to the IC and between the VCC and VEE pins to support high peak currents being drawn from VCC during turn-on of the MOSFET. 2. Proper grounding is crucial. The driver needs a very low impedance path for current return to ground avoiding inductive loops. Two paths for returning current to ground are a) between SM74101 IN_REF pin and the ground of the circuit that controls the driver inputs and b) between SM74101 VEE pin and the source of the power MOSFET being driven. Both paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance. These ground paths should be distinctly separate to avoid coupling between the high current output paths and the logic signals that drive the SM74101. With rise and fall times in the range of 10 to 30nsec, care is required to minimize the lengths of current carrying conductors to reduce their inductance and EMI from the high di/dt transients generated when driving large capacitive loads. 3. If either channel is not being used, the respective input pin (IN or INB) should be connected to either VEE or VCC to avoid spurious output signals. 30159906 FIGURE 3. The schematic above shows a conceptual diagram of the SM74101 output and MOSFET load. Q1 and Q2 are the switches within the gate driver. Rg is the gate resistance of the external MOSFET, and Cin is the equivalent gate capacitance of the MOSFET. The equivalent gate capacitance is a difficult parameter to measure as it is the combination of Cgs (gate to source capacitance) and Cgd (gate to drain capacitance). The Cgd is not a constant and varies with the drain voltage. The better way of quantifying gate capacitance is the gate charge Qg in coloumbs. Qg combines the charge required by Cgs and Cgd for a given gate drive voltage Vgate. The gate resistance Rg is usually very small and losses in it can be neglected. The total power dissipated in the MOSFET driver due to gate charge is approximated by: Thermal Performance INTRODUCTION The primary goal of the thermal management is to maintain the integrated circuit (IC) junction temperature (Tj) below a specified limit to ensure reliable long term operation. The maximum TJ of IC components should be estimated in worst case operating conditions. The junction temperature can be calculated based on the power dissipated on the IC and the junction to ambient thermal resistance θJA for the IC package in the application board and environment. The θJA is not a given constant for the package and depends on the PCB design and the operating environment. PDRIVER = VGATE x QG x FSW Where FSW = switching frequency of the MOSFET. For example, consider the MOSFET MTD6N15 whose gate charge specified as 30 nC for VGATE = 12V. Therefore, the power dissipation in the driver due to charging and discharging of MOSFET gate capacitances at switching frequency of 300 kHz and VGATE of 12V is equal to DRIVE POWER REQUIREMENT CALCULATIONS IN SM74101 SM74101 is a single low side MOSFET driver capable of sourcing / sinking 3A / 7A peak currents for short intervals to drive a MOSFET without exceeding package power dissipation limits. High peak currents are required to switch the MOSFET gate very quickly for operation at high frequencies. PDRIVER = 12V x 30 nC x 300 kHz = 0.108W. In addition to the above gate charge power dissipation, - transient power is dissipated in the driver during output transitions. When either output of the SM74101 changes state, current will flow from VCC to VEE for a very brief interval of time through the output totem-pole N and P channel MOSFETs. The final component of power dissipation in the driver is the power associated with the quiescent bias current consumed by the driver input stage and Under-voltage lockout sections. Characterization of the SM74101 provides accurate estimates of the transient and quiescent power dissipation components. At 300 kHz switching frequency and 30 nC load used in the example, the transient power will be 8 mW. The 1 mA nominal quiescent current and 12V VGATE supply produce a 12 mW typical quiescent power. Therefore the total power dissipation PD = 0.118 + 0.008 + 0.012 = 0.138W. We know that the junction temperature is given by TJ = PD x θJA + TA Or the rise in temperature is given by www.national.com 8 copper pad, which can readily dissipate heat to the surroundings, θJA as low as 40°C / Watt is achievable with the package. The resulting Trise for the driver example above is thereby reduced to just 5.5 degrees. Therefore TRISE is equal to TRISE = 0.138 x 40 = 5.5°C For LLP-6 package, the integrated circuit die is attached to leadframe die pad which is soldered directly to the printed circuit board. This substantially decreases the junction to ambient thermal resistance (θJA). By providing suitable means of heat dispersion from the IC to the ambient through exposed 9 www.national.com SM74101 TRISE = TJ − TA = PD x θJA SM74101 Physical Dimensions inches (millimeters) unless otherwise noted 6-Lead LLP Package NS Package Number SDE06A www.national.com 10 SM74101 Notes 11 www.national.com SM74101 Tiny 7A MOSFET Gate Driver Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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