TI SN65HVD179

SN65HVD179
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SLLS668A – FEBRUARY 2006 – REVISED MAY 2006
5 V FULL-DUPLEX RS-485/RS-422 DRIVERS AND BALANCED RECEIVERS
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
The SN65HVD179 is a differential line driver and
differential-input line receiver that operate with a 5-V
power supply. Each driver and receiver has separate
input and output pins for full-duplex bus
communication designs. They are designed for
balanced transmission lines and interoperation with
ANSI TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11, and
ISO 8482:1993 standard-compliant devices.
Designed for INTERBUS Applications
Balanced Receiver Thresholds
1/2 Unit-Load (up to 64 nodes on the bus)
Bus-Pin ESD Protection 15 kV HBM
Bus-Fault Protection of –7V to 12V
Thermal Shutdown Protection
Power-Up/Down Glitch-free Bus Inputs and
Outputs
APPLICATIONS
•
•
•
•
•
•
•
Digital Motor Control
Utility Meters
Chassis-to-Chassis Interconnections
Electronic Security Stations
Industrial, Process, and Building Automation
Point-of-Sale (POS) Terminals and Networks
DTE/DCE Interfaces
The differential bus driver and receiver are
monolithic, integrated circuits designed for full-duplex
bi-directional data communication on multipoint
bus-transmission lines at signaling rates (1) up to 25
Mbps. The SN65HVD179 is fully enabled with no
external enabling pins.
The 1/2 unit load receiver has a higher receiver input
resistance. This results in lower bus leakage currents
over the common-mode voltage range, and reduces
the total amount of current that a 485 driver is forced
to source or sink when transmitting.
The balanced differential receiver input threshold
makes the SN65HVD179 more compatible with
fieldbus requirements that define an external failsafe
structure.
(1)
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
BALANCED RECEIVER INPUT THRESHOLDS
SN65HVD179
D PACKAGE (TOP VIEW)
VIT –(T Y P )
VIT+ (T Y P )
Recevier Output High
VCC
R
D
GND
8
2
7
3
6
4
5
A
B
Z
Y
0.20 V
0.15 V
0.10 V
0.05 V
0V
VID
-0.05 V
-0.10 V
-0.15 V
-0.20 V
Receiver Output Low
1
D
R
3
2
5
6
8
7
Y
Z
A
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
SN65HVD179
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SLLS668A – FEBRUARY 2006 – REVISED MAY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
SIGNALING RATE
UNIT LOADS
BASE PART NUMBER
SOIC MARKING
25 Mbps
1/2
SN65HVD179
SN65HVD179
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1) (2)
UNIT
VCC
Supply voltage range
–0.3 V to 6 V
VA, VB, VY, VZ
Voltage range at any bus terminal (A, B, Y, Z)
–9 V to 14 V
VTRANS
Voltage input, transient pulse through 100 Ω. See Figure 8 (A, B, Y, Z) (3)
–50 to 50 V
VI
Voltage input range (D, DE, RE)
PCONT
Continuous total power dissipation
IO
Output current (receiver output only, R)
(1)
(2)
(3)
(4)
–0.5 V to 7 V
Internally limited (4)
11 mA
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
This tests survivability only and the output state of the receiver is not specified.
The Thermal shutdown of this device internally limits the continuous total power dissipation. Thermal shutdown typically occurs when the
junction temperature reaches 165°C.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VCC
Supply voltage
VI or VIC
Voltage at any bus terminal (separately or common mode)
1/tUI
Signaling rate
RL
Differential load resistance
VIH
High-level input voltage
D
2
VCC
VIL
Low-level input voltage
D
0
0.8
VID
Differential input voltage
–12
12
IOH
High-level output current
IOL
Low-level output current
TJ
Junction temperature (2)
(1)
(2)
4.5
5.5
–7 (1)
12
25
54
Driver
V
Mbps
Ω
60
–60
Receiver
UNIT
V
mA
–8
Driver
60
Receiver
8
–40
150
mA
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
See thermal characteristics table for information regarding this specification.
ELECTROSTATIC DISCHARGE PROTECTION
PARAMETER
MIN
TYP (1)
Bus terminals and GND
Human body model (2)
All pins
±4
Charged-device-model (3)
All pins
±1
All typical values at 25°C and with a 5-V supply.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
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MAX
UNIT
±16
Human body model
(1)
(2)
(3)
2
TEST CONDITIONS
kV
SN65HVD179
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SLLS668A – FEBRUARY 2006 – REVISED MAY 2006
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
VI(K)
TEST CONDITIONS
Input clamp voltage
II = –18 mA
MIN TYP (1)
IO = 0
|VOD(SS)|
Steady-state differential output voltage
4
1.7
2.6
RL = 100 Ω, See Figure 1 (RS-422)
2.4
3.2
Vtest = –7 V to 12 V, See Figure 2
1.6
Change in magnitude of steady-state
differential output voltage between states
RL = 54 Ω, See Figure 1 and Figure 2
VOD(RING)
Differential Output Voltage overshoot and
undershoot
RL = 54 Ω, CL = 50 pF, See Figure 5 and
Figure 3 for definition
VOC(PP)
Peak-to-peak common-mode output
voltage
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode
output voltage
High-impedance state output current
IZ(S) or
IY(S)
Short Circuit output Current
II
Input current
C(OD)
Differential output capacitance
(1)
(2)
UNIT
VCC
RL = 54 Ω, See Figure 1 (RS-485)
∆|VOD(SS)|
IZ(Z) or
IY(Z)
MAX
–1.5
–0.2
V
0.2
10 (2)
%
2.2
3.3
V
–0.1
0.1
0.5
See Figure 4
VCC = 0 V, VZ or VY = 12 V,
Other input at 0 V
VCC = 0 V, VZ or VY = –7 V,
Other input at 0 V
VZ or VY = –7 V
VZ or VY = 12 V
Other input
at 0 V
90
µA
–10
–250
250
–250
250
VI = 0, VI = 2.0
0
100
16
mA
µA
pF
All typical values are at 25°C and with a 5-V supply.
10% of the peak-to-peak Differential Output voltage swing, per TIA/EIA-485.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tr
Differential output signal rise time
tf
Differential output signal fall time
tsk(p)
Pulse skew (|tPHL - tPLH|)
tsk(pp) (2)
Part-to-part skew
(1)
(2)
RL = 54 Ω, CL = 50 pF,
See Figure 5
MIN
TYP (1)
MAX
4
8
12
ns
3
6
12
ns
UNIT
1.4
ns
1
ns
All typical values are at 25°C and with a 5-V supply.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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SN65HVD179
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
VIT+
Positive-going differential input
threshold voltage
IO = –8 mA
VIT–
Negative-going differential input
threshold voltage
IO = 8 mA
Vhys
Hysteresis voltage (VIT+– VIT–)
VO
Output voltage
MAX
V
–0.2
50
mV
4.0
VID = –200 mV, IO = 8 mA, See Figure 6
Bus input current
ICC
Supply current
UNIT
0.2
VID = 200 mV, IO = –8 mA, See Figure 6
IA or IB
0.20
0.3
VA or VB = 12 V, VCC = 0 V
0.24
0.4
VA or VB = –7 V
Other input
at 0 V
V
0.3
VA or VB = 12 V
VA or VB = –7 V, VCC = 0 V
(1)
MIN TYP (1)
–0.35
–0.19
–0.25
–0.14
D at 0 V or VCC and No Load
mA
2.7
mA
All typical values are at 25°C and with a 5-V supply.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
MIN TYP (1)
MAX
24
40
UNIT
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tsk(p)
Pulse skew (|tPHL - tPLH|)
tsk(pp) (2)
Part-to-part skew
5
tr
Output signal rise time
2
4
ns
tf
Output signal fall time
2
4
ns
(1)
(2)
4
TEST CONDITIONS
VI = 0 V to 3 V, CL = 15 pF,
See Figure 7
ns
5
CL = 15 pF, See Figure 7
ns
All typical values are at 25°C and with a 5-V supply
.tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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SN65HVD179
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SLLS668A – FEBRUARY 2006 – REVISED MAY 2006
THERMAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted (1)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
Low-K board (3), No airflow
230.8
High-K board (4), No airflow
135.1
θJA
Junction–to–ambient thermal resistance (2)
θJB
Junction–to–board thermal resistance
High-K board
44.4
θJC
Junction–to–case thermal resistance
No board
43.5
PD
Device power dissipation
RL= 60 Ω, CL = 50 pF, Input to D a 50% duty
cycle square wave at indicated signaling rate
TA
Ambient air temperature
TJSD
Thermal shutdown junction temperature
(1)
(2)
(3)
(4)
°C/W
°C/W
°C/W
420
Low-K board, No airflow
–40
55
High-K board, No airflow
–40
85
165
UNIT
mW
°C
°C
See Application Information section for an explanation of these parameters.
The intent of θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
PARAMETER MEASUREMENT INFORMATION
375 Ω ±1%
II
Y
IY
VOD
0 or 3 V
Z
RL
Y
D
VOD
0 or 3 V
IZ
60 Ω ±1%
+
_ −7 V < V(test) < 12 V
Z
VI
VZ
VY
375 Ω ±1%
Figure 1. Driver VOD Test Circuit: Voltage and Current
Definitions
Figure 2. Driver VOD With Common-Mode Loading Test
Circuit
VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot
from theVOD(H) and VOD(L) steady state values.
VOD(SS)
VOD(RING)
0 V Differential
VOD(RING)
-VOD(SS)
Figure 3. VOD(RING) Waveform and Definitions
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SN65HVD179
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SLLS668A – FEBRUARY 2006 – REVISED MAY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
VY
Y
27 Ω ± 1%
D
Input
VZ
Z
Y
VOC(PP)
Z
27 Ω ± 1%
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,t r <6ns, t f <6ns, ZO = 50 Ω
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Y
W
»
W
Z
»
W
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
IA
A
IO
R
VA
VA + VB
VID
VIC
VB
B
VO
IB
2
Figure 6. Receiver Voltage and Current Definitions
A
Input
Generator
VI
3 V
R
50 W
1.5 V
1.5 V
VI
1.5 V
0 V
B
VO
CL = 15 pF
±20%
tPLH
tPHL
90 %
1.5 V
Generator : PRR = 500 kHz , 50 %
Duty Cycle , t < 6 ns , t < 6 ns ,
Z = 50 W
VO
CL Includes Fixture
and Instrumentation
Capacitance
1.5 V
10%
t
r
10%
t
Figure 7. Receiver Switching Test Circuit and Voltage Waveforms
6
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VOH
90 %
f
VOL
SN65HVD179
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SLLS668A – FEBRUARY 2006 – REVISED MAY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
A
Y
D
R
Z
100 W
±1%
+
-
Pulse Generator
15 ms duration
1% Duty Cycle
tr, tf £ 100 ns
100 W
±1%
B
+
-
Figure 8. Test Circuit, Transient Overvoltage Test
FUNCTION TABLES
DRIVER
INPUT
RECEIVER
DIFFERENTIAL INPUTS
OUTPUTS
D
Y
OUTPUTS
Z
VID = VA–VB
R
H
H
L
VID≤– 0.2 V
L
L
L
H
–0.2 V < VID < 0.2 V
?
Open
L
H
0.2 V ≤ VID
H
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SN65HVD179
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SLLS668A – FEBRUARY 2006 – REVISED MAY 2006
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D Input
R Output
VCC
Input
VCC
470 W
5W
Output
9V
9V
125 kW
A Input
B Input
VCC
VCC
R1
22 V
R1
22 V
R3
R3
Input
Input
22 V
R2
22 V
R2
Y and Z Outputs
VCC
16 V
Output
16 V
SN65HVD379
8
R1/R2
R3
9 kΩ
45 kΩ
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TYPICAL CHARACTERISTICS
RMS SUPPLY CURRENT
vs
SIGNALING RATE
70
TA =25°C
RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
ICC (RMS Supply Current, mA)
65
60
VCC = 5.0 VDC
55
50
45
40
0
5
10
15
20
25
Signaling Rate (Mbps)
Figure 9.
BUS INPUT CURRENT
vs
INPUT VOLTAGE
DRIVER LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
0.12
250
200
TA = 25°C
RE = 0 V
DE = 0 V
VCC = 5 V
DE = VCC
D=0V
0.1
IOL - Low-level Output Current - A
II - Bus Input Current - µA
150
100
50
0
VCC = 5 V
-50
-100
-150
0.08
0.06
0.04
0.02
0
-200
-250
-0.02
-7
-4
-1
2
5
8
11
14
0
VI - Bus Input Voltage - V
1
2
3
4
5
VOL - Low-Level Output Voltage - V
Figure 10.
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
DRIVER HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
2.9
0.01
VCC = 5 V
DE = VCC
D=0V
VOD - Driver Differential Voltage - V
IOH - High-level Output Current - A
-0.01
-0.03
-0.05
-0.07
-0.09
VCC = 5 V
DE at VCC
D at VCC
2.8
2.7
2.6
2.5
-0.11
2.4
-0.13
0
1
2
3
4
-40
5
-15
10
Figure 12.
Figure 13.
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
60
TA = 25°C
RL = 54 W
D = VCC
DE = VCC
IO - Driver Output Current - mA
50
40
30
20
10
0
0
1
2
3
4
VCC - Supply Voltage - V)
Figure 14.
10
35
TA - Free-Air Temperature - °C
VOH - High-Level Output Voltage - V
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5
6
60
85
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APPLICATION INFORMATION
THERMAL CHARACTERISTICS OF IC PACKAGES
θJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
θJA is not a constant and is a strong function of:
• the PCB design (50% variation)
• altitude (20% variation)
• device power (5% variation)
θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-K board gives average in-use condition
thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-K board
gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer
25 mm long and 2-oz thick. A 4% to 50% difference in θJA can be measured between these two test cards
θJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by
the operating power. It is measured by putting the mounted package up against a copper block cold plate to
force heat to flow from die, through the mold compound into the copper block.
θJC is a useful thermal characteristic when a heatsink applied to package. It is not a useful characteristic to
predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a
nonstandard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal
simulation of a package system.
θJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate
structure. θJB is only defined for the high-K test card.
θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis
of package system, see Figure 15.
Figure 15. Thermal Resistance
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PACKAGE OPTION ADDENDUM
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20-Apr-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65HVD179D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD179DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD179DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD179DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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Addendum-Page 1
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Following are URLs where you can obtain information on other Texas Instruments products and application
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Products
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amplifier.ti.com
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www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
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www.ti.com/video
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www.ti.com/wireless
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