SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 MEMORY STICK™ INTERCONNECT EXTENDER CHIPSET WITH LVDS SN65LVDT14—ONE DRIVER PLUS FOUR RECEIVERS SN65LVDT41—FOUR DRIVERS PLUS ONE RECEIVER FEATURES APPLICATIONS • • • • • • • • • Integrated 110-Ω Nominal Receiver Line Termination Resistor Operates From a Single 3.3-V Supply Greater Than 125 Mbps Data Rate Flow-Through Pin-Out LVTTL Compatible Logic I/Os ESD Protection On Bus Pins Exceeds 16 kV Meets or Exceeds the Requirements of ANSI/TIA/EIA-644A Standard for LVDS 20-Pin PW Thin Shrink Small-Outline Package With 26-Mil Terminal Pitch • • • Memory Stick Interface Extensions With Long Interconnects Between Host and Memory Stick™ Serial Peripheral Interface™ (SPI) Interface Extension to Allow Long Interconnects Between Master and Slave MultiMediaCard™ Interface in SPI Mode General-Purpose Asymmetric Bidirectional Communication DESCRIPTION The SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. It is designed to be used at the Memory Stick end of an LVDS based Memory Stick interface extension. The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package. It is designed to be used at the host end of an LVDS based Memory Stick interface extension. SN65LVDT41 LOGIC DIAGRAM (POSITIVE LOGIC) 1D 2D 3D 4D SN65LVDT14 LOGIC DIAGRAM (POSITIVE LOGIC) 1Y 1A 1Z 2Y 1B 1R 2A 2Z 3Y 2B 3Z 4Y 3B 4A 4Z 4B 5A 5Y 5B 5Z 3A 5R 2R 3R 4R 5D Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Serial Peripheral Interface is a trademark of Motorola. MultiMediaCard is a trademark of MultiMediaCard Association. Memory Stick is a trademark of Sony. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2006, Texas Instruments Incorporated SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TYPICAL MEMORY STICK INTERFACE EXTENSION SN65LVDT41 1Y 1D SCLK Memory BS Stick Host SDIO Controller DIR SN65LVDT14 1A SCLK 1Z 2Y 2D 2A BS 2Z 3Y 3D 2B 3A DIR 3Z 4Y 4D 5A 5R SCLK Memory BS Stick 2R SDIO 3R 3B 4A SD1 4Z CBT 1R 1B 4R 4B CBT 5Y SD2 5D 5B 5Z ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) Supply voltage range (2) Input voltage range Electrostatic discharge SN65LVDT14, SN65LVDT41 UNIT VCC -0.5 to 4 V D or R -0.5 to 6 V A, B, Y, or Z -0.5 to 4 V Human body model (3), A, B, Y, Z, and GND ±16 KV Human body model (3), all pins ±8 KV ±500 V Charged device model (4), all pins Continuous total power dissipation See Dissipation Rating Table Storage temperature range Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) (4) -65 to 150 °C 260 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. PACKAGE DISSIPATION RATINGS 2 PACKAGE TA <25°C POWER RATING OPERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING PW 774 mW 6.2 mW/°C 402 mW Submit Documentation Feedback SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 3.3 3.6 VCC Supply voltage 3 VIH High-level input voltage 2 VIL Low-level input voltage |VID| Magnitude of differential input voltage VIC Common-mode input voltage, See Figure 1 TA Operating free-air temperature UNIT V V 0.1 V 0.8 V 0.6 V V ID 2 2.4 V ID 2 VCC - 0.8 V 85 °C -40 2.5 VIC − Common-Mode Input Voltage − V Max at VCC > 3.15 V Max at VCC = 3 V 2 1.5 1 0.5 Minimum 0 0 0.1 0.2 0.3 0.4 0.5 0.6 |VID|− Differential Input Voltage − V Figure 1. VIC vs VID and VCC RECEIVER ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP (1) MAX Positive-going differential input voltage threshold VITH- Negative-going differential input voltage threshold VOH High-level output voltage IOH = -8 mA VOL Low-level output voltage IOL = 8 mA 0.4 V II Input current (A or B inputs) VI = 0 V and VI = 2.4 V, other input open ±40 µA II(OFF) Power-off input current (A or B inputs) VCC = 0 V, VI = 2.4 V ±40 µA Ci Input capacitance, A or B input to GND VI = A sin 2πft + CV Zt Termination impedance VID = 0.4 sin2.5E09 t V (1) See Figure 2 and Table 1 100 UNIT VITH+ -100 2.4 V 5 88 mV pF 132 Ω All typical values are at 25°C and with a 3.3-V supply. Submit Documentation Feedback 3 SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 DRIVER ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS RL = 100 Ω, See Figure 3 and Figure 5 |VOD| Differential output voltage magnitude ∆|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage IIH High-level input current VIH = 2 V IIL Low-level input current VIL = 0.8 V IOS Short-circuit output current IO(OFF) Power-off output current (1) See Figure 6 MIN TYP (1) MAX 247 340 454 UNIT mV -50 50 1.125 1.375 -50 50 mV 150 mV 20 µA 10 µA 50 VOY or VOZ = 0 V ±24 VOD = 0 V ±12 VCC = 1.5 V, VO = 2.4 V ±1 V mA µA All typical values are at 25°C and with a 3.3-V supply. DEVICE ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER ICC (1) Supply current TEST CONDITIONS SN65LVDT14 SN65LVDT41 TYP (1) MIN Driver RL = 100 Ω, Driver VI = 0.8 V or 2 V, Receiver VI = ±0.4 V MAX 25 35 UNIT mA All typical values are at 25°C and with a 3.3-V supply. RECEIVER SWITCHING CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tPLH Propagation delay time, low-to-high-level output 1 2.6 3.8 ns tPHL Propagation delay time, high-to-low-level output 1 2.6 3.8 ns tr Output signal rise time 0.15 1.2 ns tf Output signal fall time 0.15 1.2 ns tsk(p) Pulse skew (|tPHL - tPLH|) 150 600 ps tsk(o) Output skew (1) 100 400 ps tsk(pp) Part-to-part skew (2) 1 ns (1) (2) 4 CL = 10 pF, See Figure 4 tsk(o) is the magnitude of the time difference between the tpLH or tpHL of all the receivers of a single device with all of their inputs connected together. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 DRIVER SWITCHING CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tr Differential output signal rise time tf Differential output signal fall time tsk(p) Pulse skew (|tPHL - tPLH|) Output tsk(pp) Part-to-part skew (2) NOM MAX 0.9 1.7 2.9 0.9 1.6 2.9 0.26 1 0.26 RL = 100 Ω, CL = 10 pF, See Figure 7 skew (1) tsk(o) (1) (2) RL = 100 Ω, CL = 10 pF, See Figure 7 MIN UNIT ns 1 150 500 ps 80 150 ps 1.5 ns tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. PARAMETER MEASUREMENT INFORMATION A V IA V IB VID 2 R VIA VIC B VO VIB Figure 2. Receiver Voltage Definitions Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON-MODE INPUT VOLTAGE VIA VIB VID VIC 1.25 V 1.15 V 100 mV 1.2 V 1.15 V 1.25 V -100 mV 1.2 V 2.4 V 2.3 V 100 mV 2.35 V 2.3 V 2.4 V -100 mV 2.35 V 0.1 V 0.0 V 100 mV 0.05 V 0.0 V 0.1 V -100 mV 0.05 V 1.5 V 0.9 V 600 mV 1.2 V 0.9 V 1.5 V -600 mV 1.2 V 2.4 V 1.8 V 600 mV 2.1 V 1.8 V 2.4 V -600 mV 2.1 V 0.6 V 0.0 V 600 mV 0.3 V 0.0 V 0.6 V -600 mV 0.3 V Submit Documentation Feedback 5 SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 IOY Y II D IOZ VOD V VOY Z OY V OZ 2 VI VOC VOZ Figure 3. Driver Voltage and Current Definitions VID VIA CL 10 pF VIB VO VIA 1.4 V VIB 1V VID 0.4 V 0V –0.4 V tPHL VO tPLH VOH 80% VCC/2 20% VOL tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps, pulse width = 0.5 ± 0.05 µs. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 4. Receiver Timing Test Circuit and Waveforms 3.75 kΩ Y VOD Input Z 100 Ω + _ 0 V ≤ Vtest ≤ 2.4 V 3.75 kΩ Figure 5. Driver VDO Test Circuit 6 Submit Documentation Feedback SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 49.9 Ω, ±1% (2 Places) 3V Y D Input VIA Z 2 pF 0V VOC VOC(PP) VOC(SS) VOC A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 1 GHz. Figure 6. Test Circuit and Definitions for the Driver Common-Mode Output Voltage Y 100 Ω ±1% VOD Input Z CL (2 Places) 2V 1.4 V 0.8 V Input tPHL tPLH 100% 80% Output VOD(H) 0V VOD(L) 20% 0% tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps, pulse width = 0.5 ± 0.05 µs. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 7. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal Submit Documentation Feedback 7 SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 SN65LVDT41 (Marked as LVDT41) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 1D GND 2D VCC 3D GND 4D VCC 5R GND SN65LVDT14 (Marked as LVDT14) 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z 5A 5B 1A 1B 2A 2B 3A 3B 4A 4B 5Y 5Z 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 1R GND 2R VCC 3R GND 4R VCC 5D GND Function Tables RECEIVER DRIVER INPUTS OUTPUT INPUT OUTPUTS VID = VA – VB R D Y Z VID ≥ 100 mV H H H L –100 mV < VID < 100 mV ? L L H VID ≤ –100 mV L Open L H Open H H = high level, L = low level , ? = indeterminate H = high level, L = low level RECEIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS A 110 Ω VCC VCC B 300 kΩ 300 kΩ 5Ω A Input R Output B Input 7V 7V 8 7V Submit Documentation Feedback SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 DRIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC 50 Ω D Input 5Ω 10 kΩ 7V Y or Z Output 300 kΩ 7V TYPICAL CHARACTERISTICS RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 TA = 25°C, VCC = 3.3 V 3 2.5 2 1.5 1 0.5 0 −70 TA = 25°C, VCC = 3.3 V 4.5 VOL − Low-Level Output Voltage − V VOH − High-Level Output Voltage − V 3.5 5 4 3.5 3 2.5 2 1.5 1 0.5 −60 0 −50 −40 −30 −20 −10 0 0 10 20 30 40 50 60 IOH − High-Level Output Current − mA IOL − Low-Level Output Current − mA Figure 8. Figure 9. Submit Documentation Feedback 70 80 9 SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 RECEIVER (continued) HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 3 t PHL − High-To-Low Propagation Delay Time − ns t PLH − Low-To-High Propagation Delay Time − ns LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.9 VCC = 3 V 2.8 VCC = 3.3 V 2.7 2.6 VCC = 3.6 V 2.5 2.4 2.3 2.2 −50 −25 0 25 50 75 TA − Free-Air Temperature − °C 100 2.8 2.7 2.6 VCC = 3 V 2.5 VCC = 3.3 V 2.4 VCC = 3.6 V 2.3 2.2 2.1 2 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C Figure 10. Figure 11. LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.1 2 t PHL − High-To-Low Propagation Delay Time − ns t PLH − Low-To-High Propagation Delay Time − ns DRIVER VCC = 3 V 1.9 1.8 VCC = 3.6 V 1.7 1.6 VCC = 3.3 V 1.5 −50 −25 0 25 50 75 TA − Free-Air Temperature − °C 100 2.2 2.1 VCC = 3 V 2 VCC = 3.3 V 1.9 1.8 1.7 VCC = 3.6 V 1.6 1.5 −50 Figure 12. 10 −25 0 25 50 75 Ta − Free-Air Temperature − °C Figure 13. Submit Documentation Feedback 100 SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 APPLICATION INFORMATION EXTENDING THE MEMORY STICK INTERFACE USING LVDS SIGNALING OVER DIFFERENTIAL TRANSMISSION CABLES SN65LVDT41 1D SCLK Memory BS Stick Host SDIO Controller DIR 2D 3D 4D SN65LVDT14 1Y SCLK 1Z 2Y BS 2Z 3Y DIR 3Z 4Y 5A 5R 1R 2A 2B 3A SCLK Memory BS Stick 2R SDIO 3R 3B SD1 4A 4R 4B 4Z CBT 1A 1B SD2 5B CBT 5Y 5D 5Z Figure 14. System Level Block Diagram The Memory Stick signaling interface operates in a master-slave architecture, with three active signal lines. The host (master) supplies a clock (SCLK) and bus-state (BS) signal to control the operation of the system. The SCLK and BS signals are unidirectional (simplex) from the host to the Memory Stick. The serial data input-output (SDIO) signal is a bidirectional (half-duplex) signal used to communicate both control and data information between the host and the Memory Stick. The direction of data control is managed by the host through a combination of BS line states and control information delivered to the Memory Stick. The basic Memory Stick interface is capable of operating only over short distances due to the single-ended nature of the digital I/O signals. Such a configuration is entirely suitable for compact and portable devices where there is little if any separation between the host and the Memory Stick. In applications where a greater distance is needed between the host controller and the Memory Stick, it is necessary to utilize a different signaling method such as low voltage differential signaling, or LVDS. LVDS, as specified by the TIA/EIA-644-A standard, provides several benefits when compared to alternative long-distance signaling technologies: low radiated emissions, high noise immunity, low power consumption, inexpensive interconnect cables. This device pair provides the necessary LVDS drivers and receivers specifically targeted at implementing a Memory Stick interconnect extension. It utilizes simplex links for the SCLK and BS signals, and two simplex links for the SDIO data. The half-duplex SDIO data is split into two simplex streams under control of the host processor by means of the direction (DIR) signal. The DIR signal is also carried from the host to the Memory Stick on a simplex LVDS link. The switching of the SDIO signal flow direction in the single-ended interfaces is managed by electronic switch devices, identified by the CBT symbol in Figure 14. A suggested CBT device for this application is the SN74CBTLV1G125 from Texas Instruments Incorporated. These devices are available in space saving SOT-23 or SC-70 packages. Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 12-Sep-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVDT14PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT14PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT14PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT14PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT41PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT41PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT41PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT41PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDT14PWR PW 20 SITE 41 330 16 6.95 7.1 1.6 8 16 Q1 SN65LVDT14PWR PW 20 SITE 60 330 16 6.95 7.1 1.6 8 16 Q1 SN65LVDT41PWR PW 20 SITE 41 330 16 6.95 7.1 1.6 8 16 Q1 SN65LVDT41PWR PW 20 SITE 60 330 16 6.95 7.1 1.6 8 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) SN65LVDT14PWR PW 20 SITE 41 346.0 346.0 33.0 SN65LVDT14PWR PW 20 SITE 60 346.0 346.0 33.0 SN65LVDT41PWR PW 20 SITE 41 346.0 346.0 33.0 SN65LVDT41PWR PW 20 SITE 60 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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