SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS317A – NOVEMBER 1993 – REVISED OCTOBER 1995 D D D D D D D Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages description This 16-bit registered transceiver is designed for low-voltage (3.3-V) VCC operation. The SN74LVC16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. DGG OR DL PACKAGE (TOP VIEW) 1OEAB 1LEAB 1CEAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2CEAB 2LEAB 2OEAB 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 1OEBA 1LEBA 1CEBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2CEBA 2LEBA 2OEBA The A-to-B enable (CEAB) input must be low in 27 30 order to enter data from A or to output data from 28 29 B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74LVC16543 is characterized for operation from – 40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS317A – NOVEMBER 1993 – REVISED OCTOBER 1995 FUNCTION TABLE† (each 8-bit section) INPUTS CEAB LEAB OEAB A OUTPUT B H X X X Z X X H X Z L H L X L L L L B0‡ L L L L H H † A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. ‡ Output level before the indicated steady-state input conditions were established 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS317A – NOVEMBER 1993 – REVISED OCTOBER 1995 logic symbol† 1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 56 54 55 1 3 2 29 31 30 28 26 27 2LEAB 1A1 1EN3 G1 1C5 2EN4 G2 2C6 7EN9 G7 7C11 8EN10 G8 8C12 5 3 6D 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 6 2A3 2A4 2A5 2A6 2A7 2A8 4 52 51 8 49 9 48 10 47 12 45 13 44 14 43 15 9 12D 2A2 5D 16 11D 10 42 41 17 40 19 38 20 37 21 36 23 34 24 33 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS317A – NOVEMBER 1993 – REVISED OCTOBER 1995 logic diagram (positive logic) 1OEBA 1CEBA 1LEBA 1OEAB 56 54 55 1 3 1CEAB 1LEAB 1A1 2 C1 5 1D 52 1B1 C1 1D To Seven Other Channels 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB 2A1 29 31 30 28 26 27 C1 15 1D C1 1D To Seven Other Channels 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 42 2B1 SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS317A – NOVEMBER 1993 – REVISED OCTOBER 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W DL package . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) VCC VIH Supply voltage VIL VI Low-level input voltage VO Output voltage High-level input voltage VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V Input voltage MIN MAX 2.7 3.6 2 0 0 IOH High level output current High-level VCC = 2.7 V VCC = 3 V IOL Low level output current Low-level VCC = 2.7 V VCC = 3 V ∆t /∆v Input transition rise or fall rate TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V 0.8 V VCC VCC V – 12 12 – 24 24 V mA mA 0 10 ns / V – 40 85 °C 5 SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS317A – NOVEMBER 1993 – REVISED OCTOBER 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VCC† MIN to MAX TEST CONDITIONS IOH = – 100 µA 2.7 V IOH = – 12 mA VOH IOH = – 24 mA IOL = 100 µA VOL II Control inputs II(hold) I(h ld) A or B ports IOZ§ ICC Ci Control inputs Cio A or B ports TYP‡ MAX VCC – 0.2 2.2 3V 2.4 3V 2 MIN to MAX 0.2 2.7 V 0.4 3V 0.55 VI = VCC or GND VI = 0.8 V 3.6 V ±5 75 3V VI = 2 V VO = VCC or GND IO = 0 Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND UNIT V IOL = 12 mA IOL = 24 mA VI = VCC or GND, One input at VCC – 0.6 V, nICC MIN V µA µA –75 3.6 V ± 10 µA 3.6 V 40 µA 500 µA 3 V to 3.6 V 3.3 V 3 pF 3.3 V 7 pF † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. ‡ All typical values are at VCC = = 3.3 V, TA = 25°C. § For I/O ports, the parameter IOZ includes the input leakage current. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V MIN MAX VCC = 2.7 V MIN UNIT MAX tw Pulse duration, LE or CE low 4 4 ns tsu Setup time, Data before LE, CE 2 2 ns th Hold time, Data after LE, CE 2 2 ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A or B tpd PARAMETER VCC = 2.7 V UNIT MIN MAX MIN MAX B or A 1.5 8 1.5 9 ns LE A or B 1.5 9 1.5 10 ns ten CE A or B 1.5 9 1.5 10 ns tdis CE A or B 1.5 9 1.5 10 ns ten OE A or B 1.5 8.5 1.5 9.5 ns OE A or B 1.5 8.5 1.5 9.5 ns tdis 6 VCC = 3.3 V ± 0.3 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS317A – NOVEMBER 1993 – REVISED OCTOBER 1995 operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd d TEST CONDITIONS Outputs enabled Power dissipation capacitance per transceiver pF CL = 50 pF, Outputs disabled TYP UNIT 21 f = 10 MHz pF 3.5 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH tPHL VOH 1.5 V 2.7 V Output Control (low-level enabling) 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ 3V Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V 0V tPZL 2.7 V Output 1.5 V 0V tsu Input Input 1.5 V 1.5 V VOL + 0.3 V VOL tPHZ tPZH VOH 1.5 V VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. v POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 v v 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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