STP85NF3LL STB85NF3LL-1 N-CHANNEL 30V - 0.006Ω - 85A TO-220/I2PAK LOW GATE CHARGE STripFET™ POWER MOSFET PRELIMINARY DATA TYPE STP85NF3LL STB85NF3LL-1 ■ ■ ■ ■ VDSS RDS(on) ID 30 V 30 V < 0.008 Ω < 0.008 Ω 85 A 85 A TYPICAL RDS(on) = 0.0075 Ω (@4.5V) OPTIMAL RDS(ON) x Qg TRADE-OFF @4.5V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED 1 DESCRIPTION This application specific Power MOSFET is the third genaration of STMicroelectronics unique “ Single Feature Size” strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. 3 12 3 2 TO-220 I2PAK INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Value Unit Drain-source Voltage (VGS = 0) Parameter 30 V Drain-gate Voltage (RGS = 20 kΩ) 30 V ± 15 V 85 A Gate- source Voltage ID Drain Current (continuos) at TC = 25°C ID Drain Current (continuos) at TC = 100°C 60 A Drain Current (pulsed) 340 A Total Dissipation at TC = 25°C 110 W Derating Factor 0.73 W/°C IDM (●) PTOT Tstg Tj Storage Temperature Max. Operating Junction Temperature –65 to 175 °C 175 °C (●) Pulse width limited by safe operating area March 2001 1/9 STP85NF3LL/STB85NF3LL-1 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 1.36 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Maximum Lead Temperature For Soldering Purpose 300 °C Tl ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Min. Typ. Max. 30 Unit Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 V Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1 µA VDS = Max Rating, TC = 125 °C 10 µA Gate-body Leakage Current (VDS = 0) VGS = ± 15V ±100 nA Max. Unit ON (1) Symbol Parameter VGS(th) Gate Threshold Voltage RDS(on) Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250µA Min. Typ. 1 V VGS = 10V, ID = 40 A 0.006 0.008 Ω VGS = 4.5V, ID = 40 A 0.0075 0.0095 Ω Typ. Max. Unit DYNAMIC Symbol gfs (1) 2/9 Parameter Forward Transconductance Test Conditions VDS > ID(on) x RDS(on)max, ID = 40 A VDS = 25V, f = 1 MHz, VGS = 0 Min. 30 S 2210 pF Ciss Input Capacitance Coss Output Capacitance 635 pF Crss Reverse Transfer Capacitance 138 pF STP85NF3LL/STB85NF3LL-1 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions Min. VDD = 15V, ID = 30A RG = 4.7Ω VGS = 4.5V (see test circuit, Figure 3) VDD = 24V, ID = 60A, VGS = 4.5V Typ. Max. Unit 22 ns 130 ns 30 9 12.5 40 nC nC nC Typ. Max. Unit SWITCHING OFF Symbol td(off) tf td(off) tf tc Parameter Test Conditions Min. Turn-off-Delay Time Fall Time VDD = 15V, ID = 30A, RG = 4.7Ω, VGS = 4.5V (see test circuit, Figure 3) 36.5 36.5 ns ns Off-voltage Rise Time Fall Time Cross-over Time Vclamp =24V, ID =30A RG = 4.7Ω, VGS = 4.5V (see test circuit, Figure 5) 32 23 40 ns ns ns SOURCE DRAIN DIODE Symbol Max. Unit Source-drain Current 85 A ISDM (1) Source-drain Current (pulsed) 340 A VSD (2) Forward On Voltage ISD = 85A, VGS = 0 1.3 V Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 85A, di/dt = 100A/µs, VDD = 15V, Tj = 150°C (see test circuit, Figure 5) ISD trr Qrr IRRM Parameter Test Conditions Min. Typ. 65 105 3.4 ns nC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedence 3/9 STP85NF3LL/STB85NF3LL-1 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STP85NF3LL/STB85NF3LL-1 Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STP85NF3LL/STB85NF3LL-1 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STP85NF3LL/STB85NF3LL-1 TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L4 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/9 STP85NF3LL/STB85NF3LL-1 TO-262 (I2PAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 0.368 e 2.4 2.7 0.094 0.106 E 10 10.4 0.393 0.409 L 13.1 13.6 0.515 0.531 L1 3.48 3.78 0.137 0.149 L2 1.27 1.4 0.050 0.055 E e B B2 C2 A1 A C A L1 L2 D L P011P5/E 8/9 STP85NF3LL/STB85NF3LL-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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