SPICE Device Model SUM110N04-05H Vishay Siliconix N-Channel 40-V (D-S) 175°C MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 73146 S-60676Rev. B, 01-May-06 www.vishay.com 1 SPICE Device Model SUM110N04-05H Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Condition Simulated Data Measured Data VGS(th) VDS = VGS, ID = 250 µA 3.6 ID(on) VDS = 5 V, VGS = 10 V 704 VGS = 10 V, ID = 30 A 0.0046 VGS = 10 V, ID = 30 A, TJ = 125°C 0.0076 VGS = 10 V, ID = 30 A, TJ = 175°C 0.0084 IF = 30 A, VGS = 0 V 0.89 0.90 6400 6700 Unit Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistancea Forward Voltagea rDS(on) VSD V A 0.0044 Ω V b Dynamic Input Capacitance Ciss Output Capacitance Coss 659 600 Reverse Transfer Capacitance Crss 268 320 Total Gate Chargec Qg 99 95 c Gate-Source Charge Qgs Gate-Drain Chargec Qgd VGS = 0 V, VDS = 25 V, f = 1 MHz VDS = 20 V, VGS = 10 V, ID = 50 A 37 37 21 21 pF nC Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 73146 S-60676Rev. B, 01-May-06 SPICE Device Model SUM110N04-05H Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 73146 S-60676Rev. B, 01-May-06 www.vishay.com 3