RENESAS TBB1002BMTL-E

TBB1002
Twin Built in Biasing Circuit MOS FET IC
VHF/UHF RF Amplifier
REJ03G0841-0900
Rev.9.00
Aug 22, 2006
Features
•
•
•
•
Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space.
Suitable for World Standard Tuner RF amplifier.
Very useful for total tuner cost reduction.
Withstanding to ESD; Built in ESD absorbing diode. Withstand up to 200 V at C = 200 pF,
Rs = 0 conditions.
• Provide mini mold packages; CMPAK-6
Outline
RENESAS Package code: PTSP0006JA-A
(Package name: CMPAK-6)
6
5
4
2
3
1
Notes:
1. Marking is “BM”.
2. TBB1002 is individual type number of RENESAS TWIN BBFET.
Rev.9.00 Aug 22, 2006 page 1 of 9
1. Gate-1(1)
2. Source
3. Drain(1)
4. Drain(2)
5. Gate-2
6. Gate-1(2)
TBB1002
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate1 to source voltage
Symbol
VDS
VG1S
Ratings
6
Unit
V
+6
-0
V
Gate2 to source voltage
VG2S
+6
-0
30
250
150
–55 to +150
V
Drain current
ID
Channel power dissipation
Pch*3
Channel temperature
Tch
Storage temperature
Tstg
Notes: 3. Value on the glass epoxy board (49mm × 38mm × 1mm).
mA
mW
°C
°C
Electrical Characteristics
(Ta = 25°C)
The below specification are applicable for UHF unit (FET1)
Item
Symbol
Min
Typ
Max
Unit
V(BR)DSS
V(BR)G1SS
V(BR)G2SS
IG1SS
IG2SS
VG1S(off)
6
+6
+6
—
—
0.5
—
—
—
—
—
0.75
—
—
—
+100
+100
1.0
V
V
V
nA
nA
V
VG2S(off)
0.5
0.75
1.0
V
Drain current
ID(op)
13
17
21
mA
VDS = 5 V, VG1 = 5 V
VG2S = 4 V, RG = 100 kΩ
Forward transfer admittance
|yfs|
21
26
31
mS
Input capacitance
Output capacitance
Reverse transfer capacitance
Power gain
Noise figure
Ciss
Coss
Crss
PG
NF
1.4
1.0
—
16
—
1.8
1.4
0.02
21
1.7
2.2
1.8
0.04
—
2.5
pF
pF
pF
dB
dB
VDS = 5 V, VG1 = 5 V, VG2S = 4 V
RG = 100 kΩ, f = 1 kHz
VDS = 5 V, VG1 = 5 V
VG2S = 4 V, RG = 100 kΩ
f = 1 MHz
Drain to source breakdown voltage
Gate1 to source breakdown voltage
Gate2 to source breakdown voltage
Gate1 to source cutoff current
Gate2 to source cutoff current
Gate1 to source cutoff voltage
Gate2 to source cutoff voltage
Rev.9.00 Aug 22, 2006 page 2 of 9
Test conditions
ID = 200 µA, VG1S = VG2S = 0
IG1 = +10 µA, VG2S = VDS = 0
IG2 = +10 µA, VG1S = VDS = 0
VG1S = +5 V, VG2S = VDS = 0
VG2S = +5 V, VG1S = VDS = 0
VDS = 5 V, VG2S = 4 V
ID = 100 µA
VDS = 5 V, VG1S = 5 V
ID = 100 µA
VDS = VG1 = 5 V, VG2S = 4 V
RG = 100 kΩ, f = 900 MHz
Zi =S11*, Zo=S22*(:PG)
Zi =S11opt (:NF)
TBB1002
Electrical Characteristics (cont.)
(Ta = 25°C)
The below specification are applicable for VHF unit (FET2)
Item
Drain to source breakdown voltage
Gate1 to source breakdown voltage
Gate2 to source breakdown voltage
Gate1 to source cutoff current
Gate2 to source cutoff current
Gate1 to source cutoff voltage
Symbol
V(BR)DSS
V(BR)G1SS
V(BR)G2SS
IG1SS
IG2SS
VG1S(off)
Min
6
+6
+6
—
—
0.5
Typ
—
—
—
—
—
0.75
Max
—
—
—
+100
+100
1.0
Unit
V
V
V
nA
nA
V
VG2S(off)
0.5
0.75
1.0
V
Drain current
ID(op)
14
18
22
mA
VDS = 5V, VG1 = 5 V, VG2S = 4 V
RG = 82 kΩ
Forward transfer admittance
|yfs|
20
25
30
mS
Input capacitance
Ciss
2.2
2.6
3.0
pF
Output capacitance
Reverse transfer capacitance
Power gain
Noise figure
Coss
Crss
PG
NF
1.2
—
22
—
1.6
0.03
27
1.2
2.0
0.05
—
1.7
pF
pF
dB
dB
VDS = 5 V, VG1 = 5 V
VG2S = 4 V, RG = 82 kΩ
f = 1 kHz
VDS = 5 V, VG1 = 5 V
VG2S =4 V, RG = 82 kΩ
f = 1 MHz
Gate2 to source cutoff voltage
Rev.9.00 Aug 22, 2006 page 3 of 9
Test conditions
ID = 200 µA, VG1S = VG2S = 0
IG1 = +10 µA, VG2S = VDS = 0
IG2 = +10 µA, VG1S = VDS = 0
VG1S = +5 V, VG2S = VDS = 0
VG2S = +5 V, VG1S = VDS = 0
VDS = 5 V, VG2S = 4 V
ID = 100 µA
VDS = 5 V, VG1S = 5 V
ID = 100 µA
VDS = VG1 = 5 V, VG2S = 4 V
RG = 82 kΩ, f = 200 MHz
TBB1002
Test Circuits
• DC Biasing Circuit for Operating Characteristic Items (ID(op), |yfs|, Ciss, Coss, Crss, NF, PG)
Measurment of FET1
Gate 2
VG2
Open
Open
RG
A
Gate 1
VG1
ID
Drain
VD
Source
Measurment of FET2
VG2
Gate 2
RG
Drain
Gate 1
A
VD
VG1
Open
Open
Source
Rev.9.00 Aug 22, 2006 page 4 of 9
ID
TBB1002
• Equivalent Circuit
No.1
No.6
Gate-1(1)
Gate-1(2)
BBFET-(1)
BBFET-(2)
No.2
No.5
Source
Gate-2
No.3
No.4
Drain(1)
Drain(2)
• 200 MHz Power Gain, Noise Figure Test Circuit
1000p
1000p
47k
VT
VG2
VT
1000p
47k
1000p
47k
TWINBBFET
Output(50Ω)
1000p
L2
Input(50Ω)
L1
10p max
1000p
1000p
36p
1SV70
RG
RFC
82k
1SV70
1000p
V D = V G1
L1 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns
L2 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns
RFC : φ1mm Enameled Copper Wire,Inside dia 5mm, 2Turns
Rev.9.00 Aug 22, 2006 page 5 of 9
Unit : Resistance (Ω)
Capacitance (F)
TBB1002
Typical Output Characteristics (FET1)
25
200
100
0
50
100
150
68
kΩ
kΩ
0
15
10
kΩ
0
12
kΩ
0
15
10
18
5
0
200
kΩ
G =
20
R
300
VG2S = 4 V
VG1 = VDS
82
400
Drain Current ID (mA)
Channel Power Dissipation Pch* (mW)
Maximum Channel Power
Dissipation Curve
Ambient Temperature Ta (°C)
1
2
3
0k
Ω
4
5
Drain to Source Voltage VDS (V)
* Value on the glass epoxy board (49mm × 38mm × 1mm)
Forward Transfer Admittance
vs. Gate1 Voltage (FET1)
25
Drain Current ID (mA)
20
VDS = 5 V
RG = 120 kΩ
4V
15
3V
10
2V
5
VG2S = 1 V
0
1
2
3
4
5
Forward Transfer Admittance |yfs| (mS)
Drain Current vs.
Gate1 Voltage (FET1)
50
VG2S = 5 V
VDS = 4 V
40
30
150 kΩ
20
10
0
Gate1 Voltage VG1 (V)
2
3
4
5
Input Capacitance vs.
Gate2 to Source Voltage (FET1)
30
4
VDS = 5 V
VG1 = 5 V
VG2S = 4 V
25
20
15
10
5
20
50
100 200
500 1000
Gate Resistance RG (kΩ)
Rev.9.00 Aug 22, 2006 page 6 of 9
Input Capacitance Ciss (pF)
Drain Current ID (mA)
1
Gate1 Voltage VG1 (V)
Drain Current vs.
Gate Resistance (FET1)
0
10
RG = 68 kΩ
100 kΩ
3
2
VDS = 5 V
VG1 = 5 V
RG = 100 kΩ
f = 1 MHz
1
0
0
1
2
3
Gate2 to Source Voltage VG2S (V)
4
TBB1002
Drain Current vs.
Gate1 Voltage (FET2)
Typical Output Characteristics (FET2)
kΩ
Drain Current ID (mA)
kΩ
56
68
G =
20
25
VG2S = 4 V
VG1 = VDS
82
kΩ
R
0
kΩ
15
10
Drain Current ID (mA)
25
kΩ
0
12 Ω
k
0
15
10
5
20
VDS = 5 V
RG = 82 kΩ
4V
15
3V
10
2V
5
VG2S = 1 V
0
1
2
3
4
0
5
Drain to Source Voltage VDS (V)
50
4
5
30
VDS = 5 V
VG2S = 4 V
RG = 56 kΩ
30
82 k Ω
20
120 kΩ
10
1
VDS = 5 V
VG1 = 5 V
VG2S = 4 V
25
40
Drain Current ID (mA)
Forward Transfer Admittance |yfs| (mS)
3
Drain Current vs.
Gate Resistance (FET2)
2
3
4
20
15
10
5
0
10
5
20
50
100 200
500 1000
Gate1 Voltage VG1 (V)
Gate Resistance RG (kΩ)
Input Capacitance vs.
Gate2 to Source Voltage (FET2)
Power Gain vs.
Gate Resistance (FET2)
40
4
35
Power Gain PG (dB)
Input Capacitance Ciss (pF)
2
Gate1 Voltage VG1 (V)
Forward Transfer Admittance
vs. Gate1 Voltage (FET2)
0
1
3
2
VDS = 5 V
VG1 = 5 V
RG = 82 kΩ
f = 1 MHz
1
0
0
1
30
25
20
15
2
3
4
Gate2 to Source Voltage VG2S (V)
Rev.9.00 Aug 22, 2006 page 7 of 9
10
10
VDS = 5 V
VG1 = 5 V
VG2S = 4 V
f = 200 MHz
20
50
100 200
500 1000
Gate Resistance RG (kΩ)
TBB1002
Noise Figure vs.
Gate Resistance (FET2)
Gain Reduction vs.
Gate2 to Source Voltage (FET2)
3
0
VDS = 5 V
VG1 = 5 V
VG2S = 4 V
f = 200 MHz
Gain Reduction GR (dB)
Noise Figure NF (dB)
4
2
1
0
10
10
20
30
40
50
20
50
100 200
500 1000
Gate Resistance RG (kΩ)
Rev.9.00 Aug 22, 2006 page 8 of 9
VDS = VG1 = 5 V
RG = 82 kΩ
4
3
2
1
0
Gate2 to Source Voltage VG2S (V)
TBB1002
Package Dimensions
JEITA Package Code
SC-88
Package Name
CMPAK-6
RENESAS Code
PTSP0006JA-A
D
Previous Code
CMPAK-6 / CMPAK-6V
MASS[Typ.]
0.006g
A
e
Q
c
E
HE
LP
L
A
A
x M
L1
Reference
Symbol
A3
b
S A
e
A2
A
A1
y S
S
e1
b
b1
l1
c1
c
b2
A-A Section
Pattern of terminal position areas
A
A1
A2
A3
b
b1
c
c1
D
E
e
HE
L
L1
LP
x
y
b2
e1
l1
Q
Dimension in Millimeters
Min
0.8
0
0.8
0.15
0.1
1.8
1.15
2.0
0.3
0.1
0.2
Nom
0.9
0.25
0.22
0.2
0.13
0.11
2.0
1.25
0.65
2.1
Max
1.1
0.1
1.0
0.3
0.15
2.2
1.35
2.2
0.7
0.5
0.6
0.05
0.05
0.35
1.5
0.9
0.25
Ordering Information
Part Name
TBB1002BMTL-E
Quantity
3000
Shipping Container
φ 178 mm Reel, 8 mm Emboss Taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
Rev.9.00 Aug 22, 2006 page 9 of 9
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Colophon .6.0