TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 LOW VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS Check for Samples: TCA9554 FEATURES 1 • • • • • • • • • I2C to Parallel Port Expander Open-Drain Active-Low Interrupt Output Operating Power-Supply Voltage Range of 1.65 V to 5.5 V 5-V Tolerant I/Os 400-kHz Fast I2C Bus Three Hardware Address Pins Allow up to Eight Devices on the I2C/SMBus Input/Output Configuration Register Polarity Inversion Register Internal Power-On Reset • • • • • Power-Up With All Channels Configured as Inputs No Glitch on Power Up Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) PW PACKAGE (TOP VIEW) A0 A1 A2 P0 P1 P2 P3 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC SDA SCL INT P7 P6 P5 P4 DESCRIPTION/ORDERING INFORMATION This 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 1.65-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. The TCA9554 consists of one 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs with a weak pullup to VCC. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The system master can reset the TCA9554 in the event of a timeout or other improper operation by utilizing the power-on reset feature, which puts the registers in their default state and initializes the I2C/SMBus state machine. The TCA9554 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2012, Texas Instruments Incorporated TCA9554 SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION/ORDERING INFORMATION (CONTINUED) INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA9554 can remain a simple slave device. The device's outputs (latched) have high-current drive capability for directly driving LEDs and low current consumption. Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight devices to share the same I2C bus or SMBus. The TCA9554 is pin-to-pin and I2C address compatible with the PCF8574A. However, software changes are required, due to the enhancements in the TCA9554 over the PCF8574A. The TCA9554 and TCA9554A are identical except for their fixed I2C address. This allows for up to 16 of these devices (8 of each) on the same I2C/SMBus. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) (2) TSSOP – PW (2) ORDERABLE PART NUMBER Reel of 2000 TCA9554PWR TOP-SIDE MARKING PW554 Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Table 1. TERMINAL FUNCTIONS NO. 2 NAME DESCRIPTION TSSOP (PW) μQFN (RSV) 1 15 A0 Address input. Connect directly to VCC or ground. 2 16 A1 Address input. Connect directly to VCC or ground. 3 1 A2 Address input. Connect directly to VCC or ground. 4 2 P0 P-port input/output. Push-pull design structure. At power-on, P0 is configured as an input. 5 3 P1 P-port input/output. Push-pull design structure. At power-on, P1 is configured as an input. 6 4 P2 P-port input/output. Push-pull design structure. At power-on, P2 is configured as an input. 7 5 P3 P-port input/output. Push-pull design structure. At power-on, P3 is configured as an input. 8 6 GND 9 7 P4 P-port input/output. Push-pull design structure. At power-on, P4 is configured as an input. 10 8 P5 P-port input/output. Push-pull design structure. At power-on, P5 is configured as an input. 11 9 P6 P-port input/output. Push-pull design structure. At power-on, P6 is configured as an input. 12 10 P7 P-port input/output. Push-pull design structure. At power-on, P7 is configured as an input. 13 11 INT Interrupt output. Connect to VCC through a pullup resistor. 14 12 SCL Serial clock bus. Connect to VCC through a pullup resistor. 15 13 SDA Serial data bus. Connect to VCC through a pullup resistor. 16 14 VCC Supply voltage Ground Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 Figure 1. FUNCTIONAL BLOCK DIAGRAM INT A0 A1 A2 SCL SDA 13 Interrupt Logic LP Filter 1 2 3 14 15 P7−P0 I2C Bus Control Input Filter Shift Register I/O Port 8 Bits Write Pulse VCC GND 16 8 Power-On Reset Read Pulse A. Pin numbers shown are for the PW package. B. All I/Os are set to inputs at reset. Figure 2. SIMPLIFIED SCHEMATIC OF P0 TO P7 Data From Shift Register Data From Shift Register Output Port Register Data Configuration Register VCC Q1 Q D FF Write Configuration Pulse CK Q 100 kW D Q FF Write Pulse P0 to P7 CK Q Q2 Output Port Register Input Port Register D Q FF Read Pulse GND Input Port Register Data CK Q INT Data From Shift Register D Write Polarity Pulse CK Q Q Polarity Register Data FF Polarity Inversion Register A. At power-on reset, all registers return to default values. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 3 TCA9554 SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com I/O Port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high impedance input with a weak pullup (100 kΩ typ) to VCC. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. I2C Interface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 3). After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must not be changed between the Start and Stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 4). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 3). Any number of data bytes can be transferred from the transmitter to receiver between the Start and Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 5). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. SDA SCL S P Start Condition Stop Condition Figure 3. Definition of Start and Stop Conditions 4 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 4. Bit Transfer Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 5. Acknowledgment on the I2C Bus Table 2. Interface Definition BYTE 2 I C slave address Px I/O data bus BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) L H L L A2 A1 A0 R/W P7 P6 P5 P4 P3 P2 P1 P0 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 5 TCA9554 SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com Device Address Figure 6 shows the address byte for the TCA9554. Slave Address 0 1 0 0 A2 A1 A0 R/W Hardware Selectable Fixed Figure 6. TCA9554 Address Table 3. Address Reference INPUTS I2C BUS SLAVE ADDRESS A2 A1 A0 L L L 32 (decimal), 20 (hexadecimal) L L H 33 (decimal), 21 (hexadecimal) L H L 34 (decimal), 22 (hexadecimal) L H H 35 (decimal), 23 (hexadecimal) H L L 36 (decimal), 24 (hexadecimal) H L H 37 (decimal), 25 (hexadecimal) H H L 38 (decimal), 26 (hexadecimal) H H H 39 (decimal), 27 (hexadecimal) The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read is selected. A low (0) selects a write operation. Control Register and Command Byte Following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the TCA9554. Two bits of this command byte state the operation (read or write) and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission. Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. 0 0 0 0 0 0 B1 B0 Figure 7. Control Register Bits Table 4. Command Byte CONTROL REGISTER BITS 6 B1 B0 COMMAND BYTE (HEX) 0 0 0x00 0 1 0x01 1 0 0x02 1 1 0x03 PROTOCOL POWER-UP DEFAULT Input Port Read byte XXXX XXXX Output Port Read/write byte 1111 1111 Polarity Inversion Read/write byte 0000 0000 Configuration Read/write byte 1111 1111 REGISTER Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 Register Descriptions The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to let the I2C device know that the Input Port register will be accessed next. Table 5. Register 0 (Input Port Register) BIT I7 I6 I5 I4 I3 I2 I1 I0 DEFAULT X X X X X X X X The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 6. Register 1 (Output Port Register) BIT O7 O6 O5 O4 O3 O2 O1 O0 DEFAULT 1 1 1 1 1 1 1 1 The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin original polarity is retained. Table 7. Register 2 (Polarity Inversion Register) BIT N7 N6 N5 N4 N3 N2 N1 N0 DEFAULT 0 0 0 0 0 0 0 0 The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Table 8. Register 3 (Configuration Register) BIT C7 C6 C5 C4 C3 C2 C1 C0 DEFAULT 1 1 1 1 1 1 1 1 Power-On Reset When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9554 in a reset condition until VCC has reached VPOR. At that point, the reset condition is released and the TCA9554 registers and I2C/SMBus state machine will initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to the operating voltage for a power-reset cycle. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 7 TCA9554 SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com Interrupt Output (INT) An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting; data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. INT has an open-drain structure and requires a pullup resistor to VCC. Bus Transactions Data is exchanged between the master and TCA9554 through write and read commands. Writes Data is transmitted to the TCA9554 by sending the device address and setting the least-significant bit to a logic 0 (see Figure 6 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte (see Figure 8 and Figure 9). There is no limitation on the number of data bytes sent in one write transmission. SCL 1 2 3 4 5 6 7 8 9 Slave Address S SDA 0 1 0 Command Byte 0 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 Data 1 A A P ACK From Slave ACK From Slave R/W ACK From Slave Start Condition Data to Port Write to Port Data Out From Port Data 1 Valid t pv Figure 8. Write to Output Port Register <br/> SCL 1 2 3 4 5 6 7 8 9 Slave Address SDA S 0 1 0 Command Byte 0 A2 A1 A0 0 Start Condition R/W A 0 0 0 0 ACK From Slave 0 0 Data to Register 1 1/0 A Data ACK From Slave A P ACK From Slave Data to Register Figure 9. Write to Configuration or Polarity Inversion Registers 8 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 Reads The bus master first must send the TCA9554 address with the least significant bit (LSB) set to a logic 0 (see Figure 6 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again, but this time the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the TCA9554 (see Figure 10 and Figure 11). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. S 0 1 0 ACK From Slave ACK From Slave Slave Address 0 A2 A1 A0 0 Command Byte A A S 0 ACK From ACK From Master Slave Data From Register Slave Address 1 0 Data A Data From Register NACK From Master 0 A2 A1 A0 1 A R/W R/W Data NA P Last Byte Figure 10. Read From Register <br/> 1 SCL 2 3 4 5 6 7 8 9 Data From Port Slave Address S 0 SDA 1 Start Condition 0 0 A2 A1 A0 1 R/W Data 1 A Data From Port Data 4 A ACK From Master ACK From Slave NA P NACK From Master Stop Condition Read From Port Data Into Port Data 2 tph Data 3 Data 4 Data 5 tps INT tiv tir A. This figure assumes the command byte has previously been programmed with 00h. B. Transfer of data can be stopped at any moment by a Stop condition. C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from the P port. See Figure 10 for these details. Figure 11. Read From Input Port Register Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 9 TCA9554 SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6 V VI Input voltage range (2) –0.5 6 V VO Output voltage range (2) –0.5 6 IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IIOK Input/output clamp current VO < 0 or VO > VCC ±20 mA IOL Continuous output low current VO = 0 to VCC 50 mA IOH Continuous output high current VO = 0 to VCC –50 mA ICC Continuous current through GND –250 Continuous current through VCC 160 θJA Package thermal impedance (3) Tstg Storage temperature range (1) (2) (3) PW package –65 V mA 108 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions VCC Supply voltage VIH High-level input voltage SCL, SDA A2–A0, P7–P0 VCC = 1.65 V to 2.3 V VCC = 2.3 V to 5.5 V SCL, SDA VIL Low-level input voltage A2–A0, P7–P0 IOH High-level output current P7–P0 IOL Low-level output current P7–P0 TA Operating free-air temperature 10 MIN MAX 1.65 5.5 0.7 × VCC 5.5 0.7 × VCC 5.5 2 5.5 –0.5 0.3 × VCC VCC = 1.65 V to 2.3 V –0.5 0.3 × VCC VCC = 2.3 V to 5.5 V –0.5 0.8 –40 Submit Documentation Feedback UNIT V V V –10 mA 25 mA 85 °C Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN –1.2 VIK Input diode clamp voltage II = –18 mA 1.65 V to 5.5 V VPOR Power-on reset voltage VI = VCC or GND, IO = 0 1.65 V to 5.5 V IOH = –8 mA VOH P-port high-level output voltage (2) IOH = –10 mA SDA VOL = 0.4 V VOL = 0.5 V IOL P port (3) VOL = 0.7 V INT II SCL, SDA A2–A0 1.65 V 1.2 2.3 V 1.8 3V 2.6 4.5 V 3.1 4.75 V 4.1 1.65 V 1.1 2.3 V 1.7 3V 2.5 MAX 1.5 1.65 3 4 1.65 V to 5.5 V 3 8 1.65 V 8 10 2.3 V 8 10 3V 8 14 4.5 V 8 17 4.75 V 8 35 1.65 V 10 13 2.3 V 10 13 3V 10 19 4.5 V 10 24 4.75 V 10 45 VOL = 0.4 V 1.65 V to 5.5 V 3 10 VI = VCC or GND 1.65 V to 5.5 V VI = VCC 1.65 V to 5.5 V IIL P port VI = GND 1.65 V to 5.5 V VI = VCC, IO = 0, I/O = inputs, fscl = 400 kHz, No load Operating mode VI = VCC, IO = 0, I/O = inputs, fscl = 100 kHz, No load ICC VI = GND, IO = 0, I/O = inputs, fscl = 0 kHz, No load Standby mode VI = VCC, IO = 0, I/O = inputs, fscl = 0 kHz, No load V V 4.5 V P port UNIT V 4.75 V IIH (1) (2) (3) TYP (1) mA ±1 ±1 μA 1 μA –100 μA 5.5 V 104 175 3.6 V 50 90 65 2.7 V 20 1.95 V 40 45 5.5 V 60 150 3.6 V 15 40 20 2.7 V 8 1.95 V 20 20 5.5 V 450 700 3.6 V 300 600 2.7 V 225 500 1.95 V 225 500 5.5 V 2.8 3 3.6 V 1.6 1.8 2.7 V 1.4 1.6 1.95 V 1.4 1.6 μA All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C. The total current sourced by all I/Os must be limited to 85 mA. Each I/O must be externally limited to a maximum of 25 mA, and the P port (P0 to P7) must be limited to a maximum current of 200 mA. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 11 TCA9554 SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER ΔICC CI Additional current in standby mode SCL VCC P port MIN One input at VCC – 0.6 V, Other inputs at VCC or GND 1.65 V to 5.5 V Every LED I/O at VI = 4.3 V; fscl = 0 kHz 5.5 V TYP (1) MAX UNIT 1.5 mA VI = VCC or GND SDA Cio TEST CONDITIONS 1 1.65 V to 5.5 V VIO = VCC or GND 1.65 V to 5.5 V 4 5 5.5 6.5 8 9.5 pF pF I2C Interface Timing Requirements over operating free-air temperature range (unless otherwise noted) (see Figure 12) STANDARD MODE I2C BUS MIN MAX 100 FAST MODE I2C BUS UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 μs tscl I2C clock low time 4.7 1.3 μs 2 tsp I C spike time tsds I2C serial-data setup time tsdh I2C serial-data hold time ticr I2C input rise time 50 50 250 100 0 0 kHz ns ns ns 1000 20 + 0.1Cb (1) 300 ns 300 20 + 0.1Cb (1) 300 ns 300 20 + 0.1Cb (1) 300 2 ticf I C input fall time tocf I2C output fall time tbuf I2C bus free time between Stop and Start 4.7 1.3 μs tsts I2C Start or repeated Start condition setup 4.7 0.6 μs tsth I2C Start or repeated Start condition hold 4 0.6 μs tsps I2C Stop condition setup 4 0.6 μs 50 ns 10-pF to 400-pF bus tvd(data) Valid data time SCL low to SDA output valid 300 tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 0.3 Cb I2C bus capacitive load (1) 3.45 0.1 400 ns 0.9 μs 400 ns Cb = Total capacitive load of one bus in pF Switching Characteristics over operating free-air temperature range (unless otherwise noted) (see Figure 13 and Figure 14) PARAMETER STANDARD MODE I2C BUS FAST MODE I2C BUS FROM (INPUT) TO (OUTPUT) P port INT 4 4 μs SCL INT 4 4 μs 200 ns MIN MAX MIN UNIT MAX tiv Interrupt valid time tir Interrupt reset delay time tpv Output data valid SCL P7–P0 tps Input data setup time P port SCL 100 100 ns tph Input data hold time P port SCL 1 1 μs 12 Submit Documentation Feedback 200 Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs TEMPERATURE QUIESCENT SUPPLY CURRENT vs TEMPERATURE 35 55 50 VCC = 5 V 30 ICC – Supply Current – nA ICC – Supply Current – µA 45 40 f SCL = 400 kHz I/Os unloaded 35 30 25 20 VCC = 3.3 V 15 10 VCC = 2.5 V VCC = 5 V 25 VCC = 3.3 V 20 15 VCC = 2.5 V 10 5 5 SCL = VCC 0 -40 -15 10 35 60 0 -40 85 10 35 60 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs NUMBER OF I/Os HELD LOW 70 85 600 f SCL = 400 kHz I/Os unloaded 60 VCC = 5 V 550 500 ICC – Supply Current – µA ICC – Supply Current – µA -15 50 40 30 20 450 400 TA = –40°C 350 300 TA = 25°C 250 200 TA = 85°C 150 100 10 50 0 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 0 VCC – Supply Voltage – V 1 2 3 4 5 6 7 8 Number of I/Os Held Low Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 13 TCA9554 SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) I/O OUTPUT LOW VOLTAGE vs TEMPERATURE I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 30 300 250 VCC = 2.5 V VCC = 2.5 V, ISINK = 10 mA 25 ISINK – I/O Sink Current – mA VOL – Output Low Voltage – mV 275 225 200 175 150 VCC = 5 V, ISINK = 10 mA 125 100 VCC = 2.5 V, ISINK = 1 mA 75 50 VCC = 5 V, ISINK = 1 mA TA = –40°C 20 TA = 25°C 15 TA = 85°C 10 5 25 0 0 -40 -15 10 35 60 0.0 85 0.3 0.4 0.5 0.6 TA – Free-Air Temperature – °C I/O SINK CURRENT vs OUTPUT LOW VOLTAGE I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 0.7 60 VCC = 3.3 V VCC = 5 V 55 35 50 ISINK – I/O Sink Current – mA TA = –40°C 30 25 TA = 25°C 20 15 TA = 85°C 10 45 TA = –40°C 40 35 TA = 25°C 30 25 TA = 85°C 20 15 10 5 5 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VOL – Output Low Voltage – V VOL – Output Low Voltage – V 14 0.2 VOL – Output Low Voltage – V 40 ISINK – I/O Sink Current – mA 0.1 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) I/O OUTPUT HIGH VOLTAGE vs TEMPERATURE I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 275 35 VCC = 2.5 V VCC = 2.5 V, IOL = 10 mA ISOURCE – I/O Source Current – mA (V CC – V OH ) – Output High Voltage – mV 250 225 200 175 150 125 VCC = 5 V, IOL = 10 mA 100 75 VCC = 2.5 V, IOL = 1 mA 50 VCC = 5 V, IOL = 1 mA 25 30 TA = –40°C 25 TA = 25°C 20 15 10 TA = 85°C 5 0 0 -40 0.0 -15 10 35 60 85 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (VCC – VOH) – Output High Voltage – V TA – Free-Air Temperature – °C I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 75 70 50 ISOURCE – I/O Source Current – mA 45 40 ISOURCE – I/O Source Current – mA VCC = 3.3 V TA = –40°C 35 TA = 25°C 30 25 20 TA = 85°C 15 10 5 VCC = 5 V 65 60 55 50 TA = –40°C 45 40 35 30 TA = 25°C TA = 85°C 25 20 15 10 5 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 (VCC – VOH) – Output High Voltage – V 0.1 0.2 0.3 0.4 0.5 0.6 (VCC – VOH) – Output High Voltage – V Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 0.7 15 TCA9554 SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT HIGH VOLTAGE vs SUPPLY VOLTAGE 6 TA = 25°C VOH – Output High Voltage – V 5 4 IOH = –8 mA 3 IOH = –10 mA 2 1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VCC – Supply Voltage – V 16 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 PARAMETER MEASUREMENT INFORMATION VCC RL = 1 kΩ SDA DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Three Bytes for Complete Device Programming Stop Condition (P) Start Address Address Condition Bit 7 Bit 6 (S) (MSB) Address Bit 1 tscl R/W Bit 0 (LSB) ACK (A) Data Bit 07 (MSB) Data Bit 10 (LSB) Stop Condition (P) tsch 0.7 × VCC SCL 0.3 × VCC ticr tsts tPHL ticf tbuf tPLH tsp 0.7 × VCC SDA 0.3 × VCC ticf ticr tsth tsdh tsds tsps Repeat Start Condition Start or Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS BYTE DESCRIPTION 1 I2C address 2, 3 P-port data A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 12. I2C Interface Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 17 TCA9554 SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCC RL = 4.7 kΩ INT DUT CL = 100 pF (see Note A) INTERRUPT LOAD CONFIGURATION ACK From Slave Start Condition 8 Bits (One Data Bytes) From Port R/W Slave Address S 0 1 1 1 A2 A1 A0 1 A 1 2 3 4 A 5 6 7 8 Data 1 ACK From Slave Data From Port A Data 2 1 P A tir tir B B INT A tiv tsps A Data Into Port Address Data 1 0.7 × VCC INT 0.3 × VCC SCL Data 2 0.7 × VCC R/W tiv A 0.3 × VCC tir 0.7 × VCC Pn 0.7 × VCC 1.5 V 0.3 × VCC INT 0.3 × VCC View A−A View B−B A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 13. Interrupt Load Circuit and Voltage Waveforms 18 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 PARAMETER MEASUREMENT INFORMATION (continued) 500 W Pn DUT CL = 50 pF (see Note A) 2 × VCC 500 W P-PORT LOAD CONFIGURATION SCL 0.7 × VCC P0 A P7 0.3 × VCC Slave ACK ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ SDA Pn tpv (see Note B) Unstable Data Last Stable Bit WRITE MODE (R/W = 0) SCL 0.7 × VCC P0 A tps P7 0.3 × VCC tph 0.7 × VCC 1.5 V 0.3 × VCC Pn READ MODE (R/W = 1) A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 × VCC on SCL to 50% I/O pin output. C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 14. P-Port Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 19 TCA9554 SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCC RL = 1 kΩ DUT 500 W Pn SDA 2 × VCC DUT CL = 50 pF (see Note A) CL = 50 pF (see Note A) SDA LOAD CONFIGURATION 500 W P-PORT LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.3 y VCC tRESET RESET VCC/2 tREC tw Pn VCC/2 tRESET A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 15. Reset Load Circuits and Voltage Waveforms 20 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 APPLICATION INFORMATION Figure 16 shows an application in which the TCA9554 can be used. VCC (5 V) VCC Master Controller 10 k 10 k 2k 10 k VCC SDA SDA SCL SCL INT INT P0 Subsystem 1 (e.g., Temperature Sensor) P1 INT P2 RESET P3 GND Subsystem 2 (e.g., Counter) TCA9554A P4 A P5 A2 Controlled Device (e.g., CBT Device) P6 ENABLE A1 P7 B A0 GND ALARM Subsystem 3 (e.g., Alarm System) VCC A. Device address is configured as 0100000 for this example. B. P0, P2, and P3 are configured as outputs. C. P1, P4, and P5 are configured as inputs. D. P6 and P7 are not used and have internal 100-kΩ pullup resistors to protect them from floating. Figure 16. Typical Application Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 21 TCA9554 SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com Minimizing ICC When I/Os Control LEDs When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as shown in Figure 16. Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The supply current, ICC, increases as VIN becomes lower than VCC and is specified as ΔICC in Electrical Characteristics. For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when the LED is off to minimize current consumption. Figure 17 shows a high-value resistor in parallel with the LED. Figure 18 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevents additional supply-current consumption when the LED is off. VCC LED 100 kW VCC LEDx Figure 17. High-Value Resistor in Parallel With the LED 3.3 V VCC 5V LED LEDx Figure 18. Device Supplied by a Lower Voltage Power-On Reset Requirements In the event of a glitch or data corruption, TCA9554 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 19 and Figure 20. VCC Ramp-Up Ramp-Down Re-Ramp-Up VCC_TRR_GND Time VCC_RT VCC_FT Time to Re-Ramp VCC_RT Figure 19. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC 22 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 VCC Ramp-Up Ramp-Down VCC_TRR_VPOR50 VIN drops below POR levels Time Time to Re-Ramp VCC_FT VCC_RT Figure 20. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 9 specifies the performance of the power-on reset feature for TCA9554 for both types of power-on reset. Table 9. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES (1) MAX UNIT VCC_FT Fall rate PARAMETER See Figure 19 1 100 ms VCC_RT Rise rate See Figure 19 0.01 100 ms VCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 19 40 µs VCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 20 40 µs VCC_GH Level that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μs See Figure 21 1.2 V VCC_GW Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCx See Figure 21 10 μs VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V VPORR Voltage trip point of POR on rising VCC 1.033 1.428 V (1) MIN TYP TA = –40°C to 85°C (unless otherwise noted) Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 21 and Table 9 provide more information on how to measure these specifications. VCC VCC_GH Time VCC_GW Figure 21. Glitch Width and Glitch Height VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 22 and Table 9 provide more details on this specification. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 23 TCA9554 SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com VCC VPOR VPORF Time POR Time Figure 22. VPOR 24 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 TCA9554 www.ti.com SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012 REVISION HISTORY Changes from Original (November 2011) to Revision A • Page Updated part number in DESCRIPTION/ORDERING INFORMATION section. .................................................................. 2 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TCA9554 25 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2012 PACKAGING INFORMATION Orderable Device TCA9554PWR Status (1) ACTIVE Package Type Package Drawing TSSOP PW Pins Package Qty 16 2000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TCA9554PWR Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA9554PWR TSSOP PW 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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