SLOS320E − MAY 2000 − REVISED JANUARY 2004 features key applications D High Performance D D D D Single-Ended To Differential Conversion − 160 MHz −3 dB Bandwidth (VCC = ±15 V) D Differential ADC Driver − 450 V/µs Slew Rate D Differential Antialiasing − −79 dB, Third Harmonic Distortion at D Differential Transmitter And Receiver 1 MHz D Output Level Shifter − 6.5 nV/√Hz Input-Referred Noise Differential Input/Differential Output − Balanced Outputs Reject Common-Mode THS4140 THS4141 D, DGN, OR DGK PACKAGE D, DGN, OR DGK PACKAGE Noise (TOP VIEW) (TOP VIEW) − Reduced Second Harmonic Distortion Due to Differential Output VIN− VIN+ VIN− VIN+ 1 8 1 8 Wide Power Supply Range VOCM PD V NC 2 7 2 7 OCM − VCC = 5 V Single Supply to ±15 V Dual VCC+ V VCC− V 3 6 3 6 CC− CC+ Supply VOUT+ V V VOUT− 4 5 4 5 OUT− OUT+ ICC(SD) = 880 µA in Shutdown Mode (THS4140) HIGH-SPEED DIFFERENTIAL I/O FAMILY description The THS414x is one in a family of fully differential input/differential output devices fabricated using Texas Instruments’ state-of-the-art BiComI complementary bipolar process. The THS414x is made of a true fully-differential signal path from input to output. This design leads to an excellent common-mode noise rejection and improved total harmonic distortion. THS412x 100 MHz, 43 V/µs, 3.7 nV/√Hz THS413x 150 MHz, 51 V/µs, 1.3 nV/√Hz THS415x 150 MHz, 650 V/µs, 7.6 nV/√Hz typical A/D application circuit VDD 5V VIN VOCM + − AVDD DVDD AIN − + AIN AVSS Vref THS4140 1 X THS4141 1 − SHUTDOWN −30 THD − Total Harmonic Distortion − dB DESCRIPTION NUMBER OF CHANNELS TOTAL HARMONIC DISTORTION vs FREQUENCY RELATED DEVICES DEVICE DEVICE DIGITAL OUTPUT VO = 2 VPP −40 −50 −60 −70 VCC = 5 V to ± 15 V −80 −90 −100 100k 1M 10M f − Frequency − Hz −5 V 100M Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001 − 2004, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLOS320E − MAY 2000 − REVISED JANUARY 2004 AVAILABLE OPTIONS PACKAGED DEVICES TA MSOP PowerPAD SMALL OUTLINE (D) 0°C to 70°C −40°C to 85°C EVALUATION MODULES MSOP (DGN) SYMBOL (DGK) SYMBOL THS4140CD THS4140CDGN AOF THS4140CDGK ATR THS4140EVM THS4141CD THS4141CDGN AOI THS4141CDGK ATS THS4141EVM THS4140ID THS4140IDGN AOG THS4140IDGK ASQ − THS4141ID THS4141IDGN AOK THS4141IDGK ASR − absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC− to VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC Output current, IO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Maximum junction temperature, TJ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum junction temperature, continuous operation, long term reliability, TJ (see Note 3) . . . . . . . . 125°C Operating free-air temperature, TA:C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C ESD ratings: HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500 V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The THS414x may incorporate a PowerPad on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the PowerPad thermally enhanced package. NOTE 2: The absolute maximum temperature under any condition is limited by the constraints of the silicon process. NOTE 3: The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. DISSIPATION RATING TABLE POWER RATING§ PACKAGE θJA ‡ (°C/W) θJC (°C/W) D 97.5 38.3 TA = 25°C 1.02 W TA = 85°C 410 mW DGN 58.4 4.7 1.71 W 685 mW DGK 260 54.2 385 mW 154 mW ‡ This data was taken using the JEDEC standard High−K test PCB. § Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long term reliability. recommended operating conditions MIN Dual supply Supply voltage, VCC+ to VCC− Single supply C suffix Operating free-air temperature, TA I suffix PowerPAD is a trademark of Texas Instruments. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP MAX ± 2.5 ±15 5 30 0 70 −40 85 UNIT V °C SLOS320E − MAY 2000 − REVISED JANUARY 2004 electrical characteristics, VCC = ±5 V, RL = 800 Ω, TA = 25°C (unless otherwise noted)† dynamic performance PARAMETER TEST CONDITIONS BW Small signal bandwidth (−3 dB) VCC = ±5 VCC = ±15 SR Slew rate (see Notes 1) Gain = 1 Settling time to 0.1% Differential step voltage = 2 VPP, ts Settling time to 0.01% MIN TYP MAX UNIT Gain = 1, Rf = 390 Ω 150 MHz Gain = 1, Rf = 390 Ω 160 MHz 450 V/µs 96 Gain = 1 ns 304 NOTE 4: Slew rate is measured from an output level range of 25% to 75%. † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. distortion performance PARAMETER TEST CONDITIONS 1 MHz MIN TYP VO = 2 VPP VO = 2 VPP −85 −79 8 MHz VO = 2 VPP VO = 2 VPP Total harmonic distortion Differential input, differential output THD Gain = 1, Rf = 390 Ω, RL = 800 Ω VO = 2 VPP Spurious free dynamic range (SFDR) VCC = 5 f = 1 MHz −78 VCC = ±5 f = 1 MHz −78 VCC = ±15 f = 1 MHz −79 Intermodulation distortion 5 MHz Second harmonic distortion, differential in/differential out 8 MHz 1 MHz Third harmonic distortion, differential in/differential out MAX dB −65 dB −55.5 Third-order intercept 20 MHz † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. UNIT dB −79 dB −103 dBc 37 dB noise performance PARAMETER TEST CONDITIONS MIN Vn Input voltage noise f = 10 kHz In Input current noise f = 10 kHz † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. TYP MAX UNIT 6.5 nV/√Hz 1.25 pA/√Hz dc performance PARAMETER Open loop gain Input offset voltage, differential VOS Input offset voltage, referred to VOCM Offset drift IIB IOS TEST CONDITIONS TA = 25°C TA = full range MIN 63 TYP MAX UNIT 67 dB 60 TA = 25°C TA = full range 1 TA = 25°C TA = full range 0.5 7 8.5 mV 8 µV/°C 7 Input bias current 5.1 15 µA Input offset current 0.1 1 µA TA = full range Offset drift † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.3 nA/°C 3 SLOS320E − MAY 2000 − REVISED JANUARY 2004 electrical characteristics, VCC = ±5 V, RL = 800 Ω, TA = 25°C (unless otherwise noted) (continued)† input characteristics PARAMETER CMRR Common-mode rejection ratio VICR Common-mode input voltage range RI Input resistance, closed loop CI Input capacitance TEST CONDITIONS MIN TA = full range TYP MAX UNIT 75 84 dB −3.77 to 4.3 −4 to 4.5 V Measured into each input terminal 14.4 MΩ 3.9 pF 43 Ω ro Output resistance Open loop † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. output characteristics PARAMETER TEST CONDITIONS Output voltage swing IO Output current, RL = 7 Ω MIN TYP 1.2 to 3.8 0.9 to 4.1 VCC = 5 V TA = 25°C TA = full range VCC = ±5 V TA = 25°C TA = full range ±3.7 VCC = ±15 V TA = 25°C TA = full range ±12 TA = 25°C TA = full range 35 VCC = 5 V VCC = ±5 V TA = 25°C TA = full range 45 VCC = ±15 V TA = 25°C TA = full range 65 MAX UNIT 1.3 to 3.7 ±3.9 V ±3.6 ±12.9 ±11 45 25 60 mA 35 85 50 † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. power supply PARAMETER TEST CONDITIONS Single supply VCC ICC Supply voltage range Split supply VCC = ±5 V Quiescent current ICC(SD) Quiescent current (shutdown) (THS4140) PSRR Power supply rejection ratio (dc) VCC = ±15 V TA = 25°C TYP 4 33 ±16.5 13.2 • DALLAS, TEXAS 75265 V mA 15 0.88 TA = full range POST OFFICE BOX 655303 UNIT 16 18 TA = 25°C TA = 25°C TA = full range MAX ±2 TA = 25°C TA = full range † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. 4 MIN 1.2 1.4 70 65 90 mA dB SLOS320E − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS Table of Graphs FIGURE PSRR Power supply rejection ratio vs Frequency (differential out) Small signal frequency response 2 Large signal frequency response CMMR 3 Common-mode rejection ratio vs Frequency 4 Small signal frequency response SR 5 Slew rate 6 vs Frequency Second harmonic distortion 7 vs Output voltage Third harmonic distortion 8, 9 vs Frequency 10, 11 vs Output voltage 12, 13 Settling time VO zo 14 Voltage noise vs Frequency 15 Single-ended output voltage vs Common-mode output voltage 16 Output voltage vs Differential load resistance 17 Output impedance vs Frequency 18 Input bias current vs Supply voltage 19 Output current range vs Supply voltage 20 POWER SUPPLY REJECTION RATIO vs FREQUENCY (DIFFERENTIAL OUT) −20 PSRR − Power Supply Rejection Ratio − dB Vn 1 VCC = 5 V to ±15 V −30 −40 VCC− −50 −60 VCC −70 −80 100 k 1M 10 M f − Frequency (Differential Out) − Hz 100 M Figure 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLOS320E − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS SMALL SIGNAL FREQUENCY RESPONSE LARGE SIGNAL FREQUENCY RESPONSE 45 5 RL = 800 Ω, VCC = ±5 V, VI = 45 mVPP 40 35 30 Rf = 24 kΩ VI = 0.4 VPP 0 −5 20 15 10 5 0 −5 Output − dB Output − dB 25 Rf = 2.4 kΩ Rf = 1.2 kΩ Rf = 470 Ω Rf = 240 Ω −15 −30 −15 −20 100 k 1M 10 M 100 M f − Frequency − Hz VI = 40 m VPP −20 −25 −10 VI = 0.126 VPP −10 Rf = 330 Ω, RL = 800 Ω, VCC = ±5 V, G=1 −35 100 k 1G 1M Figure 2 SMALL SIGNAL FREQUENCY RESPONSE −40 1 VCC = 5 V VI = 0.8 mVPP −50 0 VCC = 5 V −60 Output − dB CMRR − Common-Mode Rejection Ratio − dB 1G Figure 3 COMMON-MODE REJECTION RATIO vs FREQUENCY VCC = ±15 V −70 VCC = ±5 V VCC = ±15 V −1 −80 VCC = ±5 V −2 −90 −100 1M 10 M 100 M f − Frequency − Hz 1G Rf = 390 Ω, RL = 800 Ω, VI = 45 mV RMS G=1 −3 100 k 1M 10 M f − Frequency − Hz Figure 5 Figure 4 6 10 M 100 M f − Frequency − Hz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 M 1G SLOS320E − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS SECOND HARMONIC DISTORTION vs FREQUENCY SLEW RATE 1.25 VO − Output Voltage − V 0.75 VCC = ±15 V 0.5 0.25 0 VCC = 5 V −0.25 −0.5 G = 1, Rf = 330 Ω, RL = 800 Ω, CF = 1 pF, CI = 0 −0.75 −1 −1.25 116 118 VO = 4 VPP, RL = 800 Ω, Rf = 330 Ω, G=1 −55 Second Harmonic Distortion − dBc 1 −50 VI Peak = 1, TA = 25 °C 120 122 124 t − Time − ns 126 −60 −65 VCC = ±15 V −70 −75 −80 −85 −90 −95 −100 100 k 128 1M 10 M 100 M f − Frequency − Hz Figure 6 Figure 7 SECOND HARMONIC DISTORTION vs OUTPUT VOLTAGE SECOND HARMONIC DISTORTION vs OUTPUT VOLTAGE −57 −80 f = 1 MHz, RL = 800 Ω, Rf = 330 Ω, G=1 −82 VCC = ±15 V −84 −58 Second Harmonic Distortion − dBc Second Harmonic Distortion − dBc VCC = ±5 V VCC = ±5 V −86 VCC = 5 V −88 −90 VCC = 5 V −59 VCC = ±15 V −60 −61 −62 VCC = ±5 V −63 f = 16 MHz, RL = 800 Ω, Rf = 330 Ω, G=1 −64 −65 −92 −66 1 2 3 4 VO − Output Voltage − V 5 6 1 Figure 8 2 3 4 VO − Output Voltage − V 5 6 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLOS320E − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS THIRD HARMONIC DISTORTION vs FREQUENCY THIRD HARMONIC DISTORTION vs FREQUENCY −30 −30 VO = 2 VPP, RL = 800 Ω, Rf = 330 Ω, G=1 −40 Third Harmonic Distortion − dBc Third Harmonic Distortion − dBc −40 VO = 4 VPP, RL = 800 Ω, Rf = 330 Ω, G=1 −50 −60 −70 VCC = 5 V VCC = ±15 V −80 −90 −100 −50 −60 VCC = ±5 V −70 VCC = ±15 V −80 −90 −100 VCC = ±5 V −110 100 k 1M 10 M −110 100 k 100 M 1M f − Frequency − Hz Figure 10 THIRD HARMONIC DISTORTION vs OUTPUT VOLTAGE −71 VCC = ±5 V −43 Third Harmonic Distortion − dBc Third Harmonic Distortion − dBc −41 f = 1 MHz RL = 800 Ω, Rf = 330 Ω, G=1 −75 −77 −79 −81 VCC = 5 V −83 VCC = ±15 V −85 −87 −89 −45 f = 16 MHz RL = 800 Ω, Rf = 330 Ω, G=1 VCC = ±5 V −47 −49 −51 VCC = ±15 V −53 −55 −57 VCC = 5 V −59 1 1.5 2 2.5 3 3.5 4 4.5 5 VO − Output Voltage − V −61 1 Figure 12 8 100 M Figure 11 THIRD HARMONIC DISTORTION vs OUTPUT VOLTAGE −73 10 M f − Frequency − Hz 2 3 4 VO − Output Voltage − V Figure 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 6 SLOS320E − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS VOLTAGE NOISE vs FREQUENCY SETTLING TIME 2.40 100 VO − Output Voltage − V 2.30 2.20 Vn − Voltage Noise − nV/ Hz Rf = 510 Ω, CF = 1 pF, VO(PP) = 4 V, VCC = 5 V, Small Scale 2.10 2 19 ns to 1% 96 ns to 0.1% 304 ns to 0.01% 1.90 1.80 1.70 10 1.60 1 10 1.50 0 50 100 150 200 250 300 100 t − Time − ns Figure 14 OUTPUT VOLTAGE vs DIFFERENTIAL LOAD RESISTANCE 3 15 Rf = 1 kΩ, RL = 800 Ω, G=1 Rf = 1 kΩ G=2 VCC = ±5 V VCC = ±2.5 V 2 1.5 VCC = ±15 V 1 VCC = ±15 V VOUT+ 10 VO − Output Voltage − V VOS − Single-Ended Input Offset Voltage − mV 100 K Figure 15 SINGLE-ENDED INPUT OFFSET VOLTAGE vs COMMON-MODE OUTPUT VOLTAGE 2.5 1K 10 K f − Frequency − Hz VOUT+ 5 VCC = ±5 V 0 VOUT− −5 VCC = − ±5 V VVOUT− OUT− 0.5 −10 VCC = − ±15 V 0 −12 −9 −6 −3 0 3 6 9 12 VOCM − Common-Mode Output Voltage − V −15 100 1k 10 k RL − Differential Load Resistance − Ω Figure 16 100 k Figure 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLOS320E − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS OUTPUT IMPEDANCE vs FREQUENCY 100 VCC = ±5 V Output Impedance − Ω 10 1 0.1 0.01 100 k 1M 10 M 100 M f − Frequency − Hz 1G Figure 18 INPUT BIAS CURRENT vs SUPPLY VOLTAGE OUTPUT CURRENT RANGE vs SUPPLY VOLTAGE 90 6.50 I O − Output Current Range − mA I IB− Input Bias Current − µ A 80 TA = −40°C 6 5.50 5 TA = 85°C TA = 25°C 4.50 4 3.50 TA = −40°C TA = 25°C 70 60 TA = 85°C 50 40 30 20 10 3 1 3 11 7 9 VCC − Supply Voltage − ±V 5 13 15 0 1 2 Figure 19 10 3 4 5 6 7 8 9 10 11 12 13 14 15 VCC − Supply Voltage − ±V Figure 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLOS320E − MAY 2000 − REVISED JANUARY 2004 APPLICATION INFORMATION resistor matching Resistor matching is important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortion will diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. VOCM sets the dc level of the output signals. If no voltage is applied to the VOCM pin, it will be set to the midrail voltage internally defined as: ǒVCC)Ǔ ǒ ) V Ǔ CC– 2 In the differential mode, the VOCM on the two outputs cancel each other. Therefore, the output in the differential mode is the same as the input in the gain of 1. VOCM has a high bandwidth capability up to the typical operation range of the amplifier. For the prevention of noise going through the device, use a 0.1 µF capacitor on the VOCM pin as a bypass capacitor. The following graph shows the simplified diagram of the THS414x. VCC+ Output Buffer VIN− x1 VOUT+ C VIN+ R Vcm Error Amplifier + _ C x1 R VOUT− Output Buffer VCC+ 30 kΩ 30 kΩ VCC− VCC− VOCM Figure 21. THS414x Simplified Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLOS320E − MAY 2000 − REVISED JANUARY 2004 APPLICATION INFORMATION data converters Data converters are one of the most popular applications for the fully differential amplifiers. The following schematic shows a typical configuration of a fully differential amplifier attached to a differential ADC. VDD VCC 5V VIN + − AVDD AIN1 − + AIN2 AVSS VOCM 0.1 µF DVDD Vref −5 V VCC− Figure 22. Fully Differential Amplifier Attached to a Differential ADC Fully differential amplifiers can operate with a single supply. VOCM defaults to the midrail voltage, VCC/2. The differential output may be fed into a data converter. This method eliminates the use of a transformer in the circuit. If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the VOCM of the amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to the input terminal of the amplifier should not exceed the common-mode input voltage range. VDD VCC 5V VIN + − AVDD AIN1 − + AIN2 AVSS VOCM 0.1 µF DVDD Vref Figure 23. Fully Differential Amplifier Using a Single Supply 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLOS320E − MAY 2000 − REVISED JANUARY 2004 APPLICATION INFORMATION data converters (continued) Some single supply applications may require the input voltage to exceed the common-mode input voltage range. In such cases, the following circuit configuration is suggested to bring the common-mode input voltage within the specifications of the amplifier. VDD VCC Rf VCC RPU Rg VIN 5V VP V OCM 0.1 µF VOUT + − − + AIN AIN VOUT Rg RPU VCC AVDD DVDD AVSS Vref Rf Figure 24. Circuit With Improved Common-Mode Input Voltage The following equation is used to calculate RPU: R PU + V –V P CC 1 1 V –V ) V –V IN P RG P RF OUT ǒ Ǔ ǒ Ǔ driving a capacitive load Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS414x has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device’s phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 25. A minimum value of 20 Ω should work well for most applications. For example, in 50-Ω transmission systems, setting the series resistor value to 50 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end. 390 Ω 20 Ω 390 Ω Output THS414x 20 Ω 390 Ω Output 390 Ω Figure 25. Driving a Capacitive Load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SLOS320E − MAY 2000 − REVISED JANUARY 2004 APPLICATION INFORMATION Active antialias filtering For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass filters can prevent the aliasing of the high frequency noise with the frequency of operation. The following figure presents a method by which the noise may be filtered in the THS414x. R2 C1 VCC R4 + R1 − VIN− + VIN+ R(t) THS414x − + C2 Vs C3 R3 VIN+ R1 THS1050 VIN− VOCM VOCM R3 C3 VIC R4 VCC− + C1 R2 Figure 26. Antialias Filtering The transfer function for this filter circuit is: ȡ ȣȡ Rt ȣ 2R4 ) Rt K ȧ ȧ xȧ H (f) + d ȧ f 2 1 jf ȧ 1 ) j2πfR4RtC3ȧ 2R4 ) Rt Ȥ Ȣ–ǒFSF x fcǓ ) Q FSF x fc ) 1Ȥ Ȣ FSF x fc + Where K + R2 R1 Ǹ2 x R2R3C1C2 1 and Q + Ǹ R3C1 ) R2C1 ) KR3C1 2π 2 x R2R3C1C2 K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency-scaling factor, and Q is the quality factor. FSF + ǸRe 2 ) |Im| 2 and Q + ǸRe 2 ) |Im| 2 2Re Where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 = C, and C2 = nC results in: FSF x fc + Ǹ2 x mn 1 and Q + Ǹ 1 ) m(1 ) K) 2πRC 2 x mn Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select C and calculate R for the desired fc. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLOS320E − MAY 2000 − REVISED JANUARY 2004 PRINCIPLES OF OPERATION theory of operation The THS414x is a fully differential amplifier. Differential amplifiers are typically differential in/single out, whereas fully differential amplifiers are differential in/differential out. THS414x Fully differential Amplifier VCC+ Differential Amplifier Rf R(g) _ VIN+ + R(g) _ VIN− + Rf VO+ + _ VO− VOCM VCC− Figure 27. Differential Amplifier Versus a Fully Differential Amplifier To understand the THS414x fully differential amplifiers, the definition for the pinouts of the amplifier are provided. Input voltage definition V Output voltage definition V Transfer function V ǒ + V ID Ǔ – ǒVI–Ǔ I) ǒ OD + V OD + V Output common mode voltage V OC V Ǔ – ǒVO–Ǔ O) ID IC V + OC ǒVI)Ǔ ) ǒVI–Ǔ 2 + ǒVO)Ǔ ) ǒVO–Ǔ 2 x Aǒ Ǔ f + V OCM Differential Structure Rejects Coupled Noise at the Input Differential Structure Rejects Coupled Noise at the Output VCC+ VIN− VIN+ Differential Structure Rejects Coupled Noise at the Power Supply _ + VO+ + _ VO− VOCM VCC− Figure 28. Definition of the Fully Differential Amplifier POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SLOS320E − MAY 2000 − REVISED JANUARY 2004 PRINCIPLES OF OPERATION theory of operation (continued) The following schematics depict the differences between the operation of the THS414x, fully differential amplifier, in two different modes. Fully differential amplifiers can work with differential input or can be implemented as single in/differential out. Rf VIN− R(g) VCC+ −+ Vs VO+ +− VIN+ VO− VOCM R(g) Note: For proper operation, maintain symmetry by setting Rf1 = Rf2 = Rf and R(g)1 = R(g)2 = R(g) ⇒ A = Rf/R(g) VCC− Rf Figure 29. Amplifying Differential Signals Rf VIN− R(g) VCC+ RECOMMENDED RESISTOR VALUES VO+ −+ +− VIN+ Vs VO− VOCM R(g) GAIN R(g) Ω Rf Ω 1 2 5 10 390 374 402 402 390 750 2010 4020 VCC− Rf Figure 30. Single In With Differential Out If each output is measured independently, each output is one-half of the input signal when gain is 1. The following equations express the transfer function for each output: V O + 1 V 2 I The second output is equal and opposite in sign: V O + –1 V 2 I Fully differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an inverting amplifier holds true for gain calculations. One advantage of fully differential amplifiers is that they offer twice as much dynamic range compared to single-ended amplifiers. For example, a 1-VPP ADC can only support an input signal of 1 VPP. If the output of the amplifier is 2 VPP, then it will not be practical to feed a 2-VPP signal into the targeted ADC. Using a fully differential amplifier enables the user to break down the output into two 1-VPP signals with opposite signs and feed them into the differential input nodes of the ADC. In practice, the designer has been able to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully differential amplifier. The final result indicates twice as much dynamic range. Figure 31 illustrates the increase in dynamic range. The gain factor should be considered in this scenario. The THS414x fully differential amplifier offers an improved CMRR and PSRR due to its symmetrical input and output. Furthermore, second harmonic distortion is improved. Second harmonics tend to cancel because of the symmetrical output. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLOS320E − MAY 2000 − REVISED JANUARY 2004 PRINCIPLES OF OPERATION theory of operation (continued) a VOD= 1−0 = 1 VCC+ VIN− VIN+ +1 _ + + _ VO+ 0 VO− +1 0 VOCM VCC− VOD = 0−1 = −1 b Figure 31. Fully Differential Amplifier With Two 1-VPP Signals Similar to the standard inverting amplifier configuration, input impedance of a fully differential amplifier is selected by the input resistor, R(g). If input impedance is a constraint in design, the designer may choose to implement the differential amplifier as an instrumentation amplifier. This configuration improves the input impedance of the fully differential amplifier. The following schematic depicts the general format of instrumentation amplifiers. The general transfer function for this circuit is: V ǒ Ǔ R OD f 1 ) 2R2 + R R1 V –V (g) IN1 IN2 THS4012 VIN1 R(g) + _ Rf R2 _ R1 THS414x + R2 _ VIN2 + THS4012 R(g) Rf Figure 32. Instrumentation Amplifier POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SLOS320E − MAY 2000 − REVISED JANUARY 2004 PRINCIPLES OF OPERATION circuit layout considerations To achieve the levels of high frequency performance of the THS414x, follow proper printed-circuit board high frequency design techniques. A general set of guidelines is given below. In addition, a THS414x evaluation board is available to use as a guide for layout or for evaluating the device performance. D Ground planes—It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. D Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. D Sockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. D Short trace runs/compact part placements—Optimum high frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. D Surface-mount passive components—Using surface-mount passive components is recommended for high frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLOS320E − MAY 2000 − REVISED JANUARY 2004 PRINCIPLES OF OPERATION power-down mode The power-down mode is used when power saving is required. The power-down terminal (PD) found on the THS414x is an active low terminal. If it is left as a no-connect terminal, the device will always stay on due to an internal 50 kΩ resistor to VCC. The threshold voltage for this terminal is approximately 1.4 V above VCC−. This means that if the PD terminal is 1.4 V above VCC −, the device is active. If the PD terminal is less than 1.4 V above VCC −, the device is off. For example, if VCC − = −5 V, then the device is on when PD reaches 3.6 V, (-5 V + 1.4 V = −3.6 V). By the same calculation, the device is off below −3.6 V. It is recommended to pull the terminal to VCC − in order to turn the device off. The following graph shows the simplified version of the power-down circuit. While in the power-down state, the amplifier goes into a high-impedance state. The amplifier output impedance is typically greater than 1 MΩ in the power-down state. VCC 50 kΩ To Internal Bias Circuitry Control PD VCC− Figure 33. Simplified Power-Down Circuit Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be very low while in the power-down state. This is because the feedback resistor (Rf) and the gain resistor (R(g)) are still connected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output of the amplifier. An example of the closed-loop output impedance is shown in Figure 34. THS4141 OUTPUT IMPEDANCE (IN SHUTDOWN) vs FREQUENCY 2200 Output Impedance − Ω VCC = ±5 V, VI = 0.8 VPP RMS PD = VCC− 1200 200 10 k 100 k 1M 10 M f − Frequency − Hz 100 M Figure 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SLOS320E − MAY 2000 − REVISED JANUARY 2004 PRINCIPLES OF OPERATION general PowerPAD design considerations The THS414x is available packaged in a thermally-enhanced DGN package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is mounted [see Figure 35(a) and Figure 35(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 35(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the surface mount with the, heretofore, awkward mechanical methods of heatsinking. More complete details of the PowerPAD installation process and thermal management techniques can be found in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package (SLMA002). This document can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 35. Views of Thermally Enhanced DGN Package 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated