TI THS4631DGNG4

D−8
DDA−8
THS4631
DGN−8
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
HIGH-VOLTAGE, HIGH SLEW RATE, WIDEBAND
FET-INPUT OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
High Bandwidth:
– 325 MHz in Unity Gain
– 210 MHz Gain Bandwidth Product
High Slew Rate:
– 900 V/µs (G = 2)
– 1000 V/µs (G = 5)
Low Distortion of –76 dB, SFDR at 5 MHz
Maximum Input Bias Current: 100 pA
Input Voltage Noise: 7 nV/√Hz
Maximum Input Offset Voltage: 500 µV at 25°C
Low Offset Drift: 2.5 µV/°C
Input Impedance: 109 || 3.9 pF
Wide Supply Range: ± 5 V to ± 15 V
High Output Current: 95 mA
APPLICATIONS
•
•
•
•
•
•
•
Wideband Photodiode Amplifier
High-Speed Transimpedance Gain Stage
Test and Measurement Systems
Current-DAC Output Buffer
Active Filtering
High-Speed Signal Integrator
High-Impedance Buffer
Photodiode Circuit
CF
The THS4631 is a high-speed, FET-input operational
amplifier designed for applications requiring wideband
operation, high-input impedance, and high-power
supply voltages. By providing a 210-MHz gain
bandwidth product, ±15-V supply operation, and
100-pA input bias current, the THS4631 is capable of
simultaneous wideband transimpedance gain and
large output signal swing. The fast 1000 V/µs slew
rate allows for fast settling times and good harmonic
distortion at high frequencies. Low current and voltage noise allow amplification of extremely low-level
input signals while still maintaining a large signal-to-noise ratio.
The characteristics of the THS4631 make it ideally
suited for use as a wideband photodiode amplifier.
Photodiode output current is a prime candidate for
transimpedance amplification as shown below. Other
potential applications include test and measurement
systems requiring high-input impedance, ADC and
DAC buffering, high-speed integration, and active
filtering.
The THS4631 is offered in an 8-pin SOIC (D), and
the 8-pin SOIC (DDA) and MSOP (DGN) with
PowerPAD™ package.
Related FET Input Amplifier Products
GBWP
(MHz)
SLEW
RATE
(V/µS)
±5
230
±5
1600
OPA627
±15
THS4601
±15
DEVICE
VS
(V)
OPA656
OPA657
VOLTAGE
NOISE
(nV/√Hz)
MINIMUM
GAIN
290
7
1
700
4.8
7
16
55
4.5
1
180
100
5.4
1
RF
_
λ
+
RL
−V(Bias)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
THS4631
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNITS
VS
Supply voltage, VS– to VS+
33 V
VI
Input voltage
±VS
IO
(2)
Output current
150 mA
Continuous power dissipation
See Dissipation Rating Table
Maximum junction temperature (2)
TJ
150°C
TA
Operating free-air temperature, continues operation, long-term
Tstg
Storage temperature range
Lead temperature
ESD ratings:
(1)
(2)
reliability (2)
125°C
65°C to 150°C
1,6 mm (1/16 inch) from case for 10 seconds
300°C
HBM
1000 V
CDM
1500 V
MM
100 V
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
PACKAGE DISSIPATION RATINGS
PACKAGE
(2)
θJA (°C/W)
POWER RATING (1) (TJ =125°C)
TA ≤ 25°C
TA = 85°C
95
1.1 W
0.47 W
45.8
2.3 W
0.98 W
2.14 W
1.11 W
(8) (2)
38.3
DDA (8)
9.2
DGN (8)
4.7
58.4
D
(1)
θJC (°C/W)
Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance.
This data was taken using the JEDEC standard High-K test PCB.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Dual Supply
±5
±15
Single Supply
10
30
-40
85
VS
Supply Voltage
TA
Operating free-air temperature
2
UNITS
V
°C
THS4631
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
PACKAGE / ORDERING INFORMATION
PACKAGE DEVICES (1)
PACKAGE TYPE SOIC – 8
THS4631D
SOIC – 8
THS4631DR
THS4631DDA
SOIC-PP – 8 (2)
THS4631DDAR
THS4631DGN
MSOP-PP – 8 (2)
THS4631DGNR
(1)
(2)
TRANSPORT MEDIA, QUANTITY
Rails, 75
Tape and Reel, 2500
Rails, 75
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
PowerPad™ is electrically isolated from all other pins. Connection of the PowerPAD to the PCB ground plane is recommended because
the ground plane is typically the largest copper area on a PCB. However, connection of the PowerPAD to VS- up to VS+ is allowed if
desired.
PIN ASSIGNMENTS
THS4631
D, DDA, AND DGN
TOP VIEW
NC
VIN−
VIN+
VS−
1
8
2
7
3
6
4
5
NC
VS+
VOUT −
NC
NC = No Internal Connection
3
THS4631
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS
VS = ±15 V, RF = 499 Ω, RL = 1 kΩ, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
–40°C to
85°C
UNITS
MIN/
MAX
AC PERFORMANCE
Small signal bandwidth, -3 dB
G = 1, RF = 0 Ω, VO = 200 mVPP
325
G = 2, RF = 499 Ω, VO = 200 mVPP
105
G = 5, RF = 499 Ω, VO = 200 mVPP
55
MHz
G = 10, RF = 499 Ω, VO = 200 mVPP
25
Gain bandwidth product
G > 20
210
MHz
0.1 dB bandwidth flatness
G = 2, RF = 499 Ω, CF = 8.2 pF
38
MHz
Large-signal bandwidth
G = 2, RF = 499 Ω, VO = 2 VPP
105
MHz
G = 2, RF = 499 Ω, VO = 2-V step
550
Slew rate
Rise and fall time
Settling time
G = 2, RF = 499 Ω, VO = 10-V step
900
G = 5, RF = 499 Ω, VO = 10-V step
1000
2-V step
5
0.1%, G = -1, VO = 2-V step, CF = 4.7 pF
40
0.01%, G = -1, VO = 2-V step, CF = 4.7 pF
190
V/µs
ns
ns
HARMONIC DISTORTION
Second harmonic distortion
Third harmonic distortion
G = 2,
VO = 2 VPP,
f = 5 MHz
RL = 100 Ω
-65
RL = 1 k Ω
-76
RL = 100 Ω
-62
RL = 1 kΩ
-94
dBc
dBc
Input voltage noise
f > 10 kHz
7
nV/√Hz
Input current noise
f > 10 kHz
20
fA/√Hz
DC PERFORMANCE
Open-loop gain
Input offset voltage (1)
Average offset voltage drift (1)
Input bias current
Input offset current
RL = 1 kΩ
VCM = 0 V
25°C to 85°C
VCM = 0 V
80
70
65
65
dB
Min
260
500
1600
2000
µV
Max
±2.5
±10
±12
±12
µV/°C
Max
50
100
1500
2000
pA
Max
25
100
700
1000
pA
Max
-13 to 12
-12.5 to
11.5
-12 to 11
-9 to 11
V
Min
95
86
80
80
dB
Min
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
VCM = 10 V
Differential input resistance
109 || 3.9
Ω || pF
Common-mode input resistance
109 || 3.9
Ω || pF
OUTPUT CHARACTERISTICS
RL = 100 Ω
±11
±10
±9.5
±9.5
RL = 1 kΩ
±13.5
±13
±12.8
±12.8
Static output current (sourcing)
RL = 20 Ω
98
90
85
Static output current (sinking)
RL = 20 Ω
95
85
80
Closed loop output impedance
G = 1, f = 1 MHz
0.1
Output voltage swing
V
Min
80
mA
Min
80
mA
Min
Ω
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
±15
±16.5
±16.5
±16.5
V
±5
±4
±4
±4
V
Max
Min
11.5
13
14
14
mA
Max
11.5
10
9
9
mA
Min
Power supply rejection (PSRR +)
VS+ = 15.5 V to 14.5 V, VS– = 15 V
95
85
80
80
dB
Min
Power supply rejection (PSRR –)
VS+ = 15 V, VS– = -15.5 V to -14..5 V
95
85
80
80
dB
Min
(1)
4
Input offset voltage is 100% tested at 25°C. It is specified by characterization and simulation over the listed temperature range.
THS4631
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS (±15 V GRAPHS)
TA = 25°C, G = 2, RF = 499 Ω, RL = 1 kΩ, Unless otherwise noted.
+15 V
Test Data
Mesurement Point
50 Ω Source
+
49.9 Ω
953 Ω
50 Ω Test
Equipment
THS4631
_
49.9 Ω
−15 V
RF
RG
499 Ω
499 Ω
CF
SMALL SIGNAL FREQUENCY
RESPONSE
SMALL SIGNAL FREQUENCY
RESPONSE
6.3
VO = 200 mVPP
0
G = 5, RF = 499 Ω,
RG = 124 Ω
105 MHz
G = 2, RF = 499 Ω,
RG = 499 Ω
7
6
5
CF = 8.2 pF
3
0
10 M
100 M
1G
G = 2, RF = 499 Ω,
RG = 499 Ω
100 k
10 M
100 M
5.6
100 k
1G
1M
10 M
LARGE SIGNAL FREQUENCY
RESPONSE
FREQUENCY RESPONSE
vs
CAPACiTIVE LOAD
4
8
VO = 200 mVPP
VO = 5 VPP
7
CF = 0 pF
0
102 MHz
CF = 5.2 pF
Signal Gain − dB
1
−1
2
6
CF = 2.2 pF
VO = 0.5 VPP
5
105 MHz
4
VO = 2 VPP
3
−2
100 k
1M
10 M
100 M
f − Frequency − Hz
Figure 4.
1G
0
100 k
RISO = 30 Ω,
CL = 56 pF
−2
RISO = 20 Ω,
CL = 100 pF
−4
50 Ω +15 V
Source
RISO
THS4631
−8
1
1M
10 M
100 M
f − Frequency − Hz
Figure 5.
1G
RISO = 50 Ω,
CL = 10 pF
G = 1,
RF = 0 Ω,
RL = 1 kΩ
0
−6
2
G = −1, RF = 499 Ω,
RG = 499 Ω
100 M
f − Frequency − Hz
SMALL SIGNAL FREQUENCY
RESPONSE
Signal Gain − dB
Signal Gain − dB
1M
5.7
Figure 3.
2
−5
38 MHz
Figure 2.
3
−4
5.9
Figure 1.
4
−3
CF = 8.2 pF
6
f − Frequency − Hz
f − Frequency − Hz
5
6.1
5.8
1
1M
105 MHz
4
2
G = 1, RF = 0 Ω
−10
100 k
6.2
Signal Gain − dB
10
G = 10, RF = 499 Ω,
RG = 54.9 Ω
CF = 0 pF
CF = 5.6 pF
8
30
20
VO = 200 mVPP
9
G = 100, RF = 11.3 kΩ, RG = 115 Ω
Signal Gain − dB
Signal Gain − dB
40
0.1-dB FLATNESS
10
50
−10
100 k
RL
−15 V
0Ω
1M
CL
10 M
100 M
1G
f − Frequency − Hz
Figure 6.
5
THS4631
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)
TA = 25°C, G = 2, RF = 499 Ω, RL = 1 kΩ, Unless otherwise noted.
SECOND ORDER
HARMONIC DISTORTION
vs
FREQUENCY
THIRD ORDER
HARMONIC DISTORTION
vs
FREQUENCY
-50
-30
−50
RL = 100 Ω
−60
−70
RL = 1 kΩ
−80
−90
1M
10 M
-40
-50
-70
-80
-90
RL = 1 kW
1M
100 M
10 M
HD2, RL = 1 kW
-80
-85
HD3, RL = 1 kW
-90
-95
100 M
0
f - Frequency - Hz
0.5
1
1.5
2 2.5
3
3.5
VO - Output Voltage Swing - VPP
Figure 7.
Figure 8.
Figure 9.
SLEW RATE
vs
OUTPUT VOLTAGE
OPEN-LOOP GAIN
vs
TEMPERATURE
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
800
600
400
4
82
90
50
81
80
25
80
70
0
60
−25
50
−50
40
−75
30
−100
20
−125
10
−150
0
−175
Open−Loop Gain − dB
G = 5,
RF = 499 Ω,
RG = 124 Ω
Open-Loop Gain − dB
SR − Slew Rate − V/ µs
-75
-100
79
78
77
76
75
74
200
73
0
2
4
6
8
10
−10
1k
72
−40 −30−20 −10 0 10 20 30 40 50 60 70 80 90
12
10 k
100 k
1M
10 M 100 M
−200
1G
f − Frequency − Hz
TC − Case Temperature − °C
VO − Output Voltage − VPP
Figure 10.
Figure 11.
Figure 12.
INPUT VOLTAGE
vs
FREQUENCY
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
INPUT BIAS CURRENT
vs
TEMPERATURE
12
Hz
I Q − Quiescent Current − mA
100
10
800
TA = 85°C
11.5
I IB − Input Bias Current − pA
0
Input Voltage Noise − nV/
-70
-1 10
1200
11
TA = 25°C
10.5
TA = −40°C
10
700
600
500
400
300
200
9.5
100
1
10
100
1k
10 k
f − Frequency − Hz
Figure 13.
6
-65
-100
f − Frequency − Hz
1000
-60
RL = 100 W
-60
G = 2,
HD2, RL = 100 W
RF = 499 W,
CF = 8.2 pF,
f = 4 MHz
HD3, RL = 100 W
-55
Phase − −40
Gain = 2
RF = 499 W
CF = 8.2 pF
VO = 2 V PP
Harmonic Distortion - dB
Gain = 2
RF = 499 Ω,
CF = 8.2 pF
VO = 2 VPP
3rd Order Harmonic Distortion - dB
2nd Order Harmonic Distortion − dB
−30
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
100 k
9
0
2
4
6
8
10
12
VS − Supply Voltage − V
Figure 14.
14
16
0
−40 −30 −20−10 0 10 20 30 40 50 60 70 80 90
TA − Free-Air Temperature − °C
Figure 15.
THS4631
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)
TA = 25°C, G = 2, RF = 499 Ω, RL = 1 kΩ, Unless otherwise noted.
INPUT OFFSET CURRENT
vs
TEMPERATURE
INPUT OFFSET VOLTAGE
vs
TEMPERATURE
OUTPUT VOLTAGE
vs
TEMPERATURE
300
250
13.55
150
125
100
75
DDA Package
13.45
100
D Package
0
50
−200
13.3
VO−
13.25
DGN Package
−300
25
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
35
45
55
65
75
13.2
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
85
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
TC − Case Temperature − °C
Figure 16.
Figure 17.
Figure 18.
STATIC OUTPUT DRIVE CURRENT
vs
TEMPERATURE
SMALL SIGNAL TRANSIENT
RESPONSE
LARGE SIGNAL TRANSIENT
RESPONSE
125
100
Source
98
1
Sink
92
90
88
0.8
75
V O − Output Voltage − V
96
94
1.2
100
V O − Output Voltage − mV
50
25
0
−25
Gain = 2,
CF = 8.2 pF,
VI = 100 mVPP,
RL = 1 kΩ
−50
−75
0.6
0.4
0.2
0
−0.2
−0.4
−0.8
−100
−1
84
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−125
−1.2
0
10
TC − Case Temperature − °C
20
30
40
Gain = 2,
CF = 8.2 pF,
VI = 1 VPP,
RL = 1 kΩ
−0.6
86
50
60
70
80
0
10
20
30
40
50
60
70
t − Time− ns
t − Time − ns
Figure 19.
Figure 20.
Figure 21.
LARGE SIGNAL TRANSIENT
RESPONSE
LARGE SIGNAL TRANSIENT
RESPONSE
LARGE SIGNAL TRANSIENT
RESPONSE
10 VPP
2
V O - Output Voltage - V
1
0.5
0
−0.5
−1
Gain =
= 2,
2,
Gain
CF =
= 8.2 pF,
pF,
C
F= 28.2
V
V
I
PP,
VI = 2 VPP,
R
=
1
kΩ
RLL = 1 kΩ
−1.5
−2
8
3
1
-1
Gain = 5,
RF = 499 W,
-3
R L = 1 kW
-5
-7
−2.5
0
25
50
75
t − Time− ns
Figure 22.
100
125
150
20 VPP
10
5
1.5
80
12
7
2.5
0
20 40 60
80 100 120 140 160 180
t - Time - ns
Figure 23.
V O - Output Voltage - V
I O − Output Drive Current − |mA|
13.4
13.35
−100
25
V O − Output Voltage − V
VO − Output Voltage − |V|
175
VO+
13.5
200
200
Input Offset Voltage − V
I IO − Input Offset Current − pA
Referred to 25°C
225
6
4
2
0
-2
-4
Gain = 5,
RF = 499 W,
-6
-8
-10
-12
RL = 1 kW
0
20 40 60
80 100 120 140 160 180
t - Time - ns
Figure 24.
7
THS4631
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)
TA = 25°C, G = 2, RF = 499 Ω, RL = 1 kΩ, Unless otherwise noted.
SETTLING TIME
1.25
G = −1,
CF = 4.7 pF
0
−0.25
−0.5
−0.75
Falling
1
G = −1,
CF = 4.7 pF
0
−0.5
−1
−1.5
−1
−2
−1.25
−2.5
Falling
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
−1
−5
Output
−10
−2
−15
−3
40
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
OVERDRIVE RECOVERY
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
REJECTION RATIO
vs
FREQUENCY
5
1
0
0
−5
−1
Gain = 5,
RF = 499 Ω,
RG = 124 Ω
0.05 0.1
−2
−3
−4
0.15 0.2 0.25 0.3 0.35
100
100
90
90
80
80
Rejection Ratio − dB
2
V I − Input Voltage − V
Output
70
60
50
40
30
60
50
PSRR+
40
PSRR−
30
20
10
10
0
−10
−5
0
5
10
15
VICR − Input Common-Mode Range − V
Figure 28.
100
10
1
0.1
0.01
1M
10 M
100 M
f − Frequency − Hz
Figure 31.
100 k
1M
Figure 30.
OUTPUT IMPEDANCE
vs
FREQUENCY
100 k
10 k
f − Frequency − Hz
Figure 29.
Z o − Output Impedance − Ω
CMRR
70
20
0
−15
−4
t − Time − s
Figure 27.
t − Time − s
8
0
Figure 26.
3
0
1
Figure 25.
15
−15
5
t − Time − ns
4
−10
2
t − Time − ns
Input
10
0
40
3
10
−20
−3
0
20
V O − Output Voltage − V
1.5
0.5
Gain = 5,
RF = 499 Ω,
RG = 124 Ω
15
V O − Output Voltage − V
V O− Output Voltage − V
0.25
CMRR − Common-Mode Rejection Ratio − dB
V O− Output Voltage − V
0.5
−20
−0.05
Input
Rising
2
0.75
4
20
2.5
Rising
1
−1.5
OVERDRIVE RECOVERY
3
V I − Input Voltage − V
SETTLING TIME
1.5
1G
10 M
100 M
THS4631
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
APPLICATION INFORMATION
INTRODUCTION
The THS4631 is a high-speed, FET-input operational
amplifier. The combination of: high gain bandwidth
product of 210 MHz, high slew rate of 1000 V/µs, and
trimmed dc precision makes the device an excellent
design option for a wide variety of applications,
including test and measurement, optical monitoring,
transimpedance gain circuits, and high-impedance
buffers. The applications section of the data sheet
discusses these particular applications in addition to
general information about the device and its features
The large gain-bandwidth product of the THS4631
provides the capability for simultaneously achieving
both high-transimpedance gain, wide bandwidth, high
slw rate, and low noise. In addition, the high-power
supply rails provide the potential for a very wide
dynamic range at the output, allowing for the use of
input sources which possess wide dynamic range.
The combination of these characteristics makes the
THS4631 a design option for systems that require
transimpedance amplification of wideband, low-level
input signals. A standard transimpedance circuit is
shown in Figure 32.
Photodiode Circuit
TRANSIMPEDANCE FUNDAMENTALS
FET-input
amplifiers
are
often
used
in
transimpedance applications because of their extremely high input impedance. A transimpedance
block accepts a current as an input and converts this
current to a voltage at the output. The high-input
impedance associated with FET-input amplifiers
minimizes errors in this process caused by the input
bias currents, IIB, of the amplifier.
CF
RF
_
λ
+
RL
−V(Bias)
DESIGNING THE TRANSIMPEDANCE
CIRCUIT
Typically, design of a transimpedance circuit is driven
by the characteristics of the current source that
provides the input to the gain block. A photodiode is
the most common example of a capacitive current
source that interfaces with a transimpedance gain
block. Continuing with the photodiode example, the
system designer traditionally chooses a photodiode
based on two opposing criteria: speed and sensitivity.
Faster photodiodes cause a need for faster gain
stages, and more sensitive photodiodes require
higher gains in order to develop appreciable signal
levels at the output of the gain stage.
These parameters affect the design of the
transimpedance circuit in a few ways. First, the speed
of the photodiode signal determines the required
bandwidth of the gain circuit. Second, the required
gain, based on the sensitivity of the photodiode, limits
the bandwidth of the circuit. Third, the larger capacitance associated with a more sensitive signal source
also detracts from the achievable speed of the gain
block. The dynamic range of the input signal also
places requirements on the amplifier dynamic range.
Knowledge of the source output current levels,
coupled with a desired voltage swing on the output,
dictates the value of the feedback resistor, RF. The
transfer function from input to output is VOUT = IINRF.
Figure 32. Wideband Photodiode Transimpedance
Amplifier
As indicated, the current source typically sets the
requirements for gain, speed, and dynamic range of
the amplifier. For a given amplifier and source combination, achievable performance is dictated by the
following parameters: the amplifier gain-bandwidth
product, the amplifier input capacitance, the source
capacitance, the transimpedance gain, the amplifier
slew rate, and the amplifier output swing. From this
information, the optimal performance of a
transimpedance circuit using a given amplifier is
determined. Optimal is defined here as providing the
required transimpedance gain with a maximized flat
frequency response.
For the circuit shown in Figure 32, all but one of the
design parameters is known; the feedback capacitor
(CF) must be determined. Proper selection of the
feedback capacitor prevents an unstable design,
controls pulse response characteristics, provides
maximized flat transimpedance bandwidth, and limits
broadband integrated noise. The maximized flat frequency response results with CF calculated as shown
in Equation 1, where CF is the feedback capacitor, RF
is the feedback resistor, CS is the total source
capacitance (including amplifier input capacitance
and parasitic capacitance at the inverting node), and
GBP is the gain-bandwidth product of the amplifier in
hertz.
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SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
1
RF G B P
C F
1
RF G B P
2
4C S
Gain
RF G B P
2
−20 dB/
Decade
(1)
Once the optimal feedback capacitor has been selected, the transimpedance bandwidth can be calculated
with Equation 2.
F
3dB
AOL
20 dB/Decade
Rate-of-Closure
Noise Gain
GBP
2 RF C S
GBP
CF
20 dB/
Decade
(2)
0
f
CI(CM)
+
CI(DIFF)
CD
RF
CF
CS = CI(CM) + CI(DIFF) + CP + CD
A.
The total source capacitance is the sum of
several distinct capacitances.
Figure 33. Transimpedance Analysis Circuit
Where:
CI(CM) is the common-mode input capacitance.
CI(DIFF) is the differential input capacitance.
CD is the diode capacitance.
CP is the parasitic capacitance at the inverting
node.
The feedback capacitor provides a pole in the noise
gain of the circuit, counteracting the zero in the noise
gain caused by the source capacitance. The pole is
set such that the noise gain achieves a 20-dB per
decade rate-of-closure with the open-loop gain response of the amplifier, resulting in a stable circuit.
As indicated, the formula given provides the feedback
capacitance for maximized flat bandwidth. Reduction
in the value of the feedback capacitor can increase
the signal bandwidth, but this occurs at the expense
of peaking in the ac response.
10
Pole
_
CP
I(DIODE)
Zero
Figure 34. Transimpedance Circuit Bode Plot
The performance of the THS4631 has been
measured for a variety of transimpedance gains with
a variety of source capacitances. The achievable
bandwidths of the various circuit configurations are
summarized numerically in Table 1. The frequency
responses are presented in Figure 35, Figure 36, and
Figure 37.
Note that the feedback capacitances do not correspond exactly with the values predicted by the
equation. They have been tuned to account for the
parasitic capacitance of the feedback resistor
(typically 0.2 pF for 0805 surface mount devices) as
well as the additional capacitance associated with the
PC board. The equation should be used as a starting
point for the design, with final values for CF optimized
in the laboratory.
Table 1. Transimpedance Performance Summary
for Various Configurations
SOURCE
CAPACITANCE
(PF)
TRANSIMPEDANCE
GAIN (Ω)
FEEDBACK
CAPACITANCE
(PF)
-3 dB
FREQUENCY
(MHZ)
15.8
18
10 k
2
18
100 k
0.5
3
18
1M
0
1.2
47
10 k
2.2
8.4
47
100 k
0.7
2.1
47
1M
0.2
0.52
100
10 k
3
5.5
100
100 k
1
1.4
100
1M
0.2
0.37
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SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
10-kΩ TRANSIMPEDANCE RESPONSES
Transimpedance Gain − dB
85
CS = 18 PF
CF = 2 PF
80
CS = 47 PF
CF = 2.2 PF
75
CS = 100 PF
CF = 3 PF
70
65
current as an input rather than a voltage. Also, the
capacitance of the current source has a direct effect
on the frequency response. A simple interface circuit
can be used to emulate a capacitive current source
with a network analyzer. With this circuit,
transimpedance bandwidth measurements are simplified, making amplifier evaluation easier and faster.
50 VS = ±15 V
RL = 1 k
RF = 10 k
10 k
IO
Network Analizer
RS
100 k
1M
10 M
1G
IO
(s) VS
2R
C2
50 C1
VS
1
S
1 C1
C2
(Above the Pole Frequency)
f − Frequency − Hz
Figure 35.
A.
The interface network creates a capacitive,
constant current source from a network
analyzer and properly terminates the network analyzer at high frequencies.
100-kΩ TRANSIMPEDANCE RESPONSES
Transimpedance Gain − dB
105
CS = 18 PF
CF = 0.5 PF
100
Figure 38. Emulating a Capacitive Current Source
With a Network Analyzer
CS = 47 PF
CF = 0.7 PF
95
The transconductance
interface circuit is:
CS = 100 PF
CF = 1 PF
90
85
100 k
function
of
the
s
2 RS 1C1
C2
VS = ±15 V
RL = 1 k
RF = 100 k
10 k
transfer
1M
10 M
1G
IO
(s) VS
s
1
2 R S C1C2
(3)
f − Frequency − Hz
The transfer function contains a zero at dc and a pole
Figure 36.
1-MΩ TRANSIMPEDANCE RESPONSES
Transimpedance Gain − dB
125
CS = 18 PF
CF = 0 PF
120
CS = 47 PF
CF = 0.2 PF
110
100
95
CS = 100 PF
CF = 0.2 PF
VS = ±15 V
RL = 1 k
RF = 1 M
10 k
100 k
ing a controllable ac-current source. This circuit also
properly terminates the network analyzer with 50 Ω at
high frequencies. The second requirement for this
current source is to provide the desired output impedance, emulating the output impedance of a
photodiode or other current source. The output impedance of this circuit is given by:
115
105
1
(
2
R
C1
C2) . The transconductance is constant
S
at:
1
C1
2 RS 1 C2 , above the pole frequency, providat:
1M
10 M
f − Frequency − Hz
Figure 37.
MEASURING TRANSIMPEDANCE
BANDWIDTH
While there is no substitute for measuring the performance of a particular circuit under the exact
conditions that are used in the application, the complete system environment often makes measurements harder. For transimpedance circuits, it is difficult to measure the frequency response with traditional laboratory equipment because the circuit requires a
1
s 2 R C1C2
ss Z O(s) C1 C2
C1 C2
S
1
2 R S C1
(4)
Assuming C1 >> C2, the equation reduces to:
ZO 1
s C2 , giving the appearance of a capacitive
source at a higher frequency.
Capacitor values should be chosen to satisfy two
requirements. First, C2 represents the anticipated
capacitance of the true source. Second C1 is chosen
such
that
the
corner
frequency
of
the
transconductance network is much less than the
transimpedance bandwidth of the circuit. Choosing
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SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
this corner frequency properly leads to more accurate
measurements of the transimpedance bandwidth. If
the interface circuit corner frequency is too close to
the bandwidth of the circuit, determining the power
level in the flatband is difficult. A decade or more of
flat bandwidth provides a good basis for determining
the proper transimpedance bandwidth.
R E Q RF 1
1
RF 2
RF 3
(5)
CF
RF3
RF2
RF1
ALTERNATIVE TRANSIMPEDANCE
CONFIGURATIONS
_
λ
Other transimpedance configurations are possible.
Three possibilities are shown below.
The first configuration is a slight modification of the
basic transimpedance circuit. By splitting the
feedback resistor, the feedback capacitor value becomes more manageable and easier to control. This
type of compensation scheme is useful when the
feedback capacitor required in the basic configuration
becomes so small that the parasitic effects of the
board and components begin to dominate the total
feedback capacitance. By reducing the resistance
across the capacitor, the capacitor value can be
increased. This mitigates the dominance of the parasitic effects.
CF
RF2
RF1
+
A.
A resistive T-network enables high
transimpedance gain with reasonable resistor values.
Figure 40. Alternative Transimpedance
Configuration 2
The third configuration uses a capacitive T-network to
achieve fine control of the compensation capacitance.
The capacitor CF3 can be used to tune the total
effective feedback capacitance to a fine degree. This
circuit behaves
the
same
as the
basic
transimpedance configuration, with the effective CF
given by Equation 6.
CF E Q
1
CF 1
1
RL
CF 3
CF 2
(6)
CF3
−V(Bias)
A.
CF1
Splitting the feedback resistor enables use
of a larger, more manageable feedback
capacitor.
CF2
RF
Figure 39. Alternative Transimpedance
Configuration 1
_
λ
+
The second configuration uses a resistive T-network
to achieve high transimpedance gains using relatively
small resistor values. This topology can be useful
when the desired transimpedance gain exceeds the
value of available resistors. The transimpedance gain
is given by Equation 5.
RL
−V(Bias)
1
_
λ
+
RL
−V(Bias)
A.
A capacitive T-network enables fine control
of the effective feedback capacitance using
relatively large capacitor values.
Figure 41. Alternative Transimpedance
Configuration 3
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SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
SUMMARY OF KEY DECISIONS IN
TRANSIMPEDANCE DESIGN
The following is a simplified process for basic
transimpedance circuit design. This process gives a
start to the design process, though it does ignore
some aspects that may be critical to the circuit.
STEP 1:
Determine
source.
STEP 2:
Calculate the total source capacitance,
including the amplifier input capacitance, CI(CM) and CI(DIFF).
STEP 3:
Determine the magnitude of the possible current output from the source,
including the minimum signal current
anticipated and maximum signal current
anticipated.
STEP 4:
Choose a feedback resistor value such
that the input current levels create the
desired output signal voltages, and
ensure that the output voltages can
accommodate the dynamic range of the
input signal.
STEP 5:
STEP 6:
STEP 7:
the
capacitance
of
the
Calculate the optimum feedback capacitance using Equation 1.
Calculate the bandwidth given
resulting component values.
feedback resistors this large or anticipate using an
external compensation scheme to stabilize the circuit.
Using a simple capacitor in parallel with the feedback
resistor makes the amplifier more stable as shown in
the Typical Characteristics graphs.
NOISE ANALYSIS
High slew rate, unity gain stable, voltage-feedback
operational amplifiers usually achieve their slew rate
at the expense of a higher input noise voltage. The
7 nV/√Hz input voltage noise for the THS4631 is,
however, much lower than comparable amplifiers
while achieving high slew rates. The input-referred
voltage noise, and the input-referred current noise
term, combine to give low output noise under a wide
variety of operating conditions. Figure 42 shows the
amplifier noise analysis model with all the noise terms
included. In this model, all noise terms are taken to
be noise voltage or current density terms in either
nV/√Hz or fA/√Hz.
ENI
+
RS
IBN
ERS
EO
_
4kTRS
ERF
Rf
the
Evaluate the circuit to determine if all
design goals are satisfied.
4kTRf
IBI
4kT = 1.6E−20J
at 290K
SELECTION OF FEEDBACK RESISTORS
Feedback resistor selection can have a significant
effect on the performance of the THS4631 in a given
application, especially in configurations with low
closed-loop gain. If the amplifier is configured for
unity gain, the output should be directly connected to
the inverting input. Any resistance between these two
points interacts with the input capacitance of the
amplifier and causes an additional pole in the frequency response. For nonunity gain configurations,
low resistances are desirable for flat frequency response. However, care must be taken not to load the
amplifier too heavily with the feedback network if
large output signals are expected. In most cases, a
trade off is made between the frequency response
characteristics and the loading of the amplifier. For a
gain of 2, a 499-Ωfeedback resistor is a suitable
operating point from both perspectives. If resistor
values are chosen too large, the THS4631 is subject
to oscillation problems. For example, an inverting
amplifier configuration with a 5-kΩ gain resistor and a
5-kΩ feedback resistor develops an oscillation due to
the interaction of the large resistors with the input
capacitance. In low gain configurations, avoid
Rg
4kT
Rg
Figure 42. Noise Analysis Model
The total output noise voltage can be computed as
the square root of all square output noise voltage
contributors. Equation 7 shows the general form for
the output noise voltage using the terms shown in
Figure 42.
EO 2
2
ENI 2 IBNRS 4kTR S NG 2 IBIRf 4kTRfNG
(7)
Dividing this expression by the noise gain [NG = (1+
Rf/Rg)] gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Equation 8:
EN 2
2
E NI 2 I BNRS 4kTR S INGR 4kTR
NG
BI
f
f
(8)
Using high resistor values can dominate the total
equivalent input-referred noise. Using a 3-kΩ
source-resistance (RS) value adds a voltage noise
term of approximately 7 nV/√Hz. This is equivalent to
the amplifier voltage noise term. Using higher resistor
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THS4631
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SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
values dominate the noise of the system. Although
the THS4631 JFET input stage is ideal for
high-source impedance because of the low-bias currents, the system noise and bandwidth is limited by a
high-source (RS) impedance.
SLEW RATE PERFORMANCE WITH VARYING
INPUT STEP AMPLITUDE AND RISE/FALL
TIME
Some FET input amplifiers exhibit the peculiar
behavior of having a larger slew rate when presented
with smaller input voltage steps and slower edge
rates due to a change in bias conditions in the input
stage of the amplifier under these circumstances.
This phenomena is most commonly seen when FET
input amplifiers are used as voltage followers. As this
behavior is typically undesirable, the THS4631 has
been designed to avoid these issues. Larger amplitudes lead to higher slew rates, as would be anticipated, and fast edges do not degrade the slew rate of
the device. The high slew rate of the THS4631 allows
improved SFDR and THD performance, especially
noticeable above 5 MHz.
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with high frequency
amplifier-like devices in the THS4631 requires careful
attention to board layout parasitic and external
component types.
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
• Minimize the distance (< 0.25”) from the power
supply pins to high frequency 0.1-µF and 100-pF
de-coupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the de-coupling
capacitors. The power supply connections should
always be de-coupled with these capacitors.
Larger (6.8 µF or more) tantalum de-coupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board.
• Careful selection and placement of external
components preserve the high frequency per14
•
formance of the THS4631. Resistors should be a
very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout.
Again, keep their leads and PC board trace
length as short as possible. Never use wirebound
type resistors in a high frequency application.
Since the output pin and inverting input pins are
the most sensitive to parasitic capacitance,
always position the feedback and series output
resistors, if any, as close as possible to the
inverting input pins and output pins. Other network components, such as input termination resistors, should be placed close to the gain-setting
resistors. Even with a low parasitic capacitance
shunting the external resistors, excessively high
resistor values can create significant time constants that can degrade performance. Good axial
metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For
resistor values > 2.0 kΩ, this parasitic capacitance can add a pole and/or a zero that can
effect circuit operation. Keep resistor values as
low as possible, consistent with load driving
considerations.
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and determine if isolation
resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need
an RS since the THS4631 is nominally compensated to operate with a 2-pF parasitic load.
Higher parasitic capacitive loads without an RS
are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long
trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A
50-Ω environment is not necessary onboard, and
in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace
impedance based on board material and trace
dimensions, a matching series resistor into the
trace from the output of the THS4631 is used as
well as a terminating shunt resistor at the input of
the destination device. Remember also that the
terminating impedance is the parallel combination
of the shunt resistor and the input impedance of
the destination device: this total effective impedance should be set to match the trace im-
THS4631
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•
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
pedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a
long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in
this case. This does not preserve signal integrity
or a doubly-terminated line. If the input impedance of the destination device is low, there is
some signal attenuation due to the voltage divider
formed by the series output into the terminating
impedance.
Socketing a high-speed part like the THS4631 is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket
creates a troublesome parasitic network which
makes it almost impossible to achieve a smooth,
stable frequency response. Best results are obtained by soldering the THS4631 part directly
onto the board.
0.205
0.060
0.017
Pin 1
0.013
0.030
0.075
0.025 0.094
0.010
vias
0.035
0.040
Top View
Figure 44. DGN PowerPAD PCB Etch and Via
Pattern
PowerPAD DESIGN CONSIDERATIONS
The THS4631 is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which
the die is mounted [see Figure 43 (a) and Figure 43
(b)]. This arrangement results in the lead frame being
exposed as a thermal pad on the underside of the
package [see Figure 43 (c)]. Because this thermal
pad has direct thermal contact with the die, excellent
thermal performance can be achieved by providing a
good thermal path away from the thermal pad
The PowerPAD package allows for both assembly
and thermal management in one manufacturing operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the mechanical methods of
heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 43. Views of Thermally Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
0.300
0.100
0.035
Pin 1
0.026
0.010
0.030
0.060
0.140
0.050
0.176
0.060
0.035
0.010
vias
0.080
All Units in Inches
Top View
Figure 45. DDA PowerPAD PCB Etch and Via
Pattern
PowerPAD PCB LAYOUT CONSIDERATIONS
1. PCB with a top side etch pattern is shown in
Figure 44 and Figure 45. There should be etch
for the leads and for the thermal pad.
2. Place the recommended number of holes in the
area of the thermal pad. These holes should be
10 mils in diameter. Keep them small so that
solder wicking through the holes is not a problem
during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
the THS4631 IC. These additional vias may be
larger than the 10-mil diameter vias directly under
the thermal pad. They can be larger because
15
THS4631
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SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
5.
6.
7.
8.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
To maintain maximum output capabilities, the
THS4631 does not incorporate automatic thermal
shutoff protection. The designer must take care to
ensure that the design does not violate the absolute
maximum junction temperature of the device. Failure
may result if the absolute maximum junction temperature of 150°C is exceeded. For best performance,
design for a maximum junction temperature of 125°C.
Between 125°C and 150°C, damage does not occur,
but the performance of the amplifier begins to degrade. The thermal characteristics of the device are
dictated by the package and the PC board. Maximum
power dissipation for a given package can be calculated using Equation 9.
16
P D max T max T A
J A
(9)
where:
PDmax is the maximum power dissipation in the
amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon
junctions to the case (°C/W).
θCA is the thermal coefficient from the case to
ambient air (°C/W).
NOTE:
For systems where heat dissipation is more
critical, the THS4631 is offered in an 8-pin MSOP
with PowerPAD package and an 8-pin SOIC with
PowerPAD package with better thermal performance. The thermal coefficient for the PowerPAD
packages are substantially improved over the
traditional SOIC. Maximum power dissipation
levels are depicted in Figure 46 for the available
packages. The data for the PowerPAD packages
assume a board layout that follows the
PowerPAD layout guidelines referenced above
and detailed in the PowerPAD application note
number SLMA002. Figure 46 also illustrates the
effect of not soldering the PowerPAD to a PCB.
The thermal impedance increases substantially
which may cause serious heat and performance
issues. Be sure to always solder the PowerPAD
to the PCB for optimum performance.
4
PD − Maximum Power Dissipation − W
4.
they are not in the thermal pad area to be
soldered so that wicking is not a problem.
Connect all holes to the internal ground plane.
Although the PowerPAD is electrically isolated
from all pins and the active circuitry, connection
to the ground plane is recommended. This is due
to the fact that ground planes on most PCBs are
typically the targets copper area. Offering the
best thermal path heat to flow out of the device.
When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer. Therefore, the holes under the THS4631 PowerPAD
package should make their connection to the
internal ground plane with a complete connection
around the entire circumference of the
plated-through hole.
The top-side solder mask should leave the terminals of the package and the thermal pad area
with its via holes exposed. The bottom-side
solder mask should cover the via holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that
is properly installed.
TJ = 125°C
3.5
3
θJA = 58.4°C/W
2.5
θJA = 98°C/W
2
1.5
1
0.5
θJA = 158°C/W
0
−40
−20
0
20
40
60
80
100
TA − Free-Air Temperature − °C
Figure 46. Maximum Power Dissipation
vs. Ambient Temperature
THS4631
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
Results are with no air flow and PCB size = 3" x 3 "
θJA = 58.4°C/W for the 8-pin MSOP with
PowerPAD (DGN).
θJA = 98°C/W for the 8-pin SOIC high-K test PCB
(D).
θJA = 158°C/W for the 8-pin MSOP with
PowerPAD, without solder.
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power dissipation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem
DESIGN TOOLS EVALUATION FIXTURE,
SPICE MODELS, AND APPLICATIONS
SUPPORT
Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal an evaluation board has
been developed for the THS4631 operational amplifier. The board is easy to use, allowing for straightforward evaluation of the device. The evaluation board
can be ordered through the Texas Instruments web
site, www.ti.com, or through your local Texas Instruments sales representative. The board layers are
provided in Figure 47, Figure 48, and Figure 49. The
bill of materials for the evaluation board is provided in
Table 2.
Figure 48. EVM Layers 2 and 3, Ground
Figure 49. EVM Bottom Layer
Figure 47. EVM Top Layer
17
THS4631
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
BILL OF MATERIALS
Table 2. THS4631DDA EVM
ITEM
DESCRIPTION
SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QUANTITY
C3, C6
2
(AVX) 12063D225KAT2A
(AVX) 08055C104KAT2A
1
CAP, 2.2 µF, CERAMIC, X5R, 25 V
1206
4
CAP, 0.1µF, CERAMIC, X7R, 50 V
0805
C1, C2
2
OPEN
0805
R4, Z4, Z6
3
6
RESISTOR, 0 OHM, 1/8 W
0805
Z2
1
(KOA) RK73Z2ATTD
7
RESISTOR, 499 OHM, 1/8 W, 1%
0805
R3, Z5
2
(KOA) RK73H2ATTD4990F
8
OPEN
1206
R8, Z9
2
9
RESISTOR, 0 OHM, 1/4 W
1206
R1
1
(KOA) RK73Z2BLTD
10
RESISTOR, 49.9 OHM, 1/4 W, 1%
1206
R2
1
(KOA) RK73H2BLTD49R9F
11
RESISTOR, 953 OHM, 1/4 W, 1%
1206
Z3
1
(KOA) RK73H2BLTD9530F
13
CONNECTOR, SMA PCB JACK
J1, J2, J3
3
(JOHNSON) 142-0701-801
14
JACK, BANANA RECEPTANCE, 0.25"
DIA. HOLE
J4, J5, J6
3
(SPC) 813
15
TEST POINT, BLACK
TP1, TP2
2
(KEYSTONE) 5001
TP3
1
(KEYSTONE) 5000
4
(KEYSTONE) 1808
4
SHR-0440-016-SN
1
(TI) THS4631DDA
1
(TI) EDGE # 6467873 Rev.A
TEST POINT, RED
(1)
MANUFACTURER'S
PART NUMBER (1)
16
STANDOFF, 4-40 HEX, 0.625" LENGTH
17
SCREW, PHILLIPS, 4-40, .250"
18
IC, THS4631
19
BOARD, PRINTED CIRCUIT
U1
The manufacturer's part numbers are used for test purposes only.
EVM
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. This is particularly true for video and RF-amplifier circuits where parasitic
capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS4631 is
available through either the Texas Instruments web site (www.ti.com). These models help in predicting
small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to
model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types
in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the
model file itself.
18
THS4631
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
Figure 50. THS4631 EVM Schematic
19
THS4631
www.ti.com
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
ADDITIONAL REFERENCE MATERIAL
•
•
•
•
•
•
•
PowerPAD Made Easy, application brief (SLMA004)
PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
Noise Analysis of FET Transimpedance Amplifiers, application bulletin, Texas Instruments Literature Number
SBOA060.
Tame Photodiodes With Op Amp Bootstrap, application bulletin, Texas Instruments Literature Number
SBBA002.
Designing Photodiode Amplifier Circuits With OPA128, application bulletin, Texas Instruments Literature
Number SBOA061.
Photodiode Monitoring With Op Amps, application bulletin, Texas Instruments Literature Number SBOA035.
Comparison of Noise Performance Between a FET Transimpedance Amplifier and a Switched Integrator,
Application Bulletin, Texas Instruments Literature Number SBOA034.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input and output voltage ranges as specified in the table provided
below.
Input Range, VS+ to VS–
10 V to 30 V
Input Range, VI
10 V to 30 V NOT TO EXCEED VS+ or VS–
Output Range, VO
10 V to 30 V NOT TO EXCEED VS+ or VS–
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the product data sheet or EVM user's guide (if user's guide is
available) prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30°C. The EVM is
designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the material provided. When placing measurement probes near these devices during operation, please
be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
20
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS4631D
ACTIVE
SOIC
D
8
75
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
THS4631DDA
ACTIVE
SO
Power
PAD
DDA
8
75
TBD
CU SNPB
Level-1-235C-UNLIM
THS4631DDAR
ACTIVE
SO
Power
PAD
DDA
8
2500
TBD
CU SNPB
Level-1-235C-UNLIM
THS4631DGN
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4631DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4631DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4631DGNRG4
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4631DR
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
THS4631DRG4
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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