Dynamic Differential Hall Effect Sensor TLE4926C-HTN E6747 Data Sheet Version 3.0 (valid for 8” product) Features • High sensitivity • Single chip solution • Symmetrical thresholds • High resistance to Piezo effects • Advanced performance by dynamic self calibration principle • South and north pole pre-induction possible • 1Hz low cut-off frequency • Digital output signal • Two-wire and three-wire configuration possible • Wide operating temperature range • Fast start-up time • Large operating airgaps • Reverse voltage protection at Vs- PIN • Short- circuit and over temperature protection of output • No external filter capacitor required • Digital output signal (voltage interface) • Module style package with two integrated capacitors: PG-SSO-3-91 • 4.7nF between Q and GND • 47nF1 between VS and GND: Needed for micro cuts in power suply • High temperature profile • Package: PG-SSO-3-91 with nickel plating instead of standard 100% Sn plating 1 Type Marking Ordering Code Package TLE4926C-HTN E6747 26C8 SP000269347 PG-SSO-3-91 value of capacitor: 47nF±10%; (excluded drift due to temperature and over lifetime); ceramic: X7R; maximum voltage: 50V. TLE4926C-HTN E6747 General Information TLE4926C is an active Hall sensor suited to detect the motion and position of ferromagnetic and permanent magnet structures. An additional self-calibration module has been implemented to achieve optimum accuracy during normal running operation. It comes in a three-pin package for the supply voltage and an open drain output. VS GND 47nF Q 4.7nF Figure 1: Pin configuration in PG-SSO-3-91 Pin No. 1 Symbol VS Function Supply Voltage 2 3 GND Q Ground Open Drain Output Functional Description The differential Hall sensor IC detects the motion and position of ferromagnetic and permanent magnet structures by measuring the differential flux density of the magnetic field. To detect ferromagnetic objects the magnetic field must be provided by a back biasing permanent magnet (south or north pole of the magnet attached to the rear unmarked side of the IC package). Offset cancellation is achieved by advanced digital signal processing. Immediately after power-on motion is detected (start-up mode). After a few transitions the sensor has finished self-calibration and switches to a high-accuracy mode (running mode). In running mode switching occurs at signal zero-crossing of the arithmetic mean of max and min value of magnetic differential signal. ∆B is defined as difference between hall plate 1 and hall plate 2. Data Sheet Page 2 of 27 TLE4926C-HTN E6747 Q clamping & reverse voltage protection VS overtemperature & short-circuit protection hyst comp power supply regulator analog supply main comp digital supply clamping n-channel open drain enable interface Hall probes ++ + amplifier - - Tracking ADC filter digital min max algorithm Offset DAC actual switching level bias for temperature & technology compensation GND oscillator reset Figure 2: Block Diagram of TLE4926C Basics of self-calibration A magnetic signal generated by a typical toothed wheel looks somewhat like a sinusoid. Optimum switching points lie near the zero crossings of the curve. Due to backbiasing conditions and imperfections in the IC the signal is superposed by an offset. Therefore the main task to accomplish is to remove this offset. This is done by measuring the minimum and maximum values of the curve and by calculating the resulting offset. By subtracting this offset from the original signal, the signal is centered on its zero crossings and these can be detected by a normal comparator. The detection of the minimum and maximum values as well as the complete signal correction strategy is implemented in a digital way. Therefore first the signal has to be digitized. Digitizing the signal A tracking A/D converter basically does signal conversion from analog into digital domain. The converter has a resolution of 6 bits. This (including some averaging calculation described later on) is sufficient for characterizing the signal if the signal is not too small. Therefore, a programmable gain amplifier (PGA) enhances the A/D converter. Its amplification can be modified by powers of two. 7 different positions are possible; the amplification range lies between ½ and 32 (Full scale A/D converter range referred to full-scale range of the offset- Dac). The gain of the PGA tracks the amplitude of the signal so that sufficient resolution of the converter is ensured. The gain of the PGA is decreased by 1 step (a factor of 2) whenever a signal overrun in the tracking converter is detected. On the other hand, the gain of the PGA is increased by 1 step, when during an offset update low signal amplitude is detected. This means, that the actual minimum value is larger or equal 50H (on an 8 bit base referred to the averaged Gain- Dac) and the actual maximum value is smaller than Data Sheet Page 3 of 27 TLE4926C-HTN E6747 B0H. This procedure ensures a sufficient resolution for each signal amplitude. After doing the 6 bit A/D conversion running at system clock speed (1.455MHz), the values are put into a simple decimation filter, which sums up 8 consecutive values and, by truncating the least significant bit, delivers an 8 bit output signal at 1/8 system speed (182kHz). The rest of the digital calibration process now refers to this 8 bit data (MinMax finding, offset calculation). The tracking converter as well as the PGA is protected against overflow or underflow, so no wrap-around or undefined condition can occurs. Instead the signal is clipped to a maximum or minimum value. Finding the minimum and maximum values During operation a dedicated logic block looks for the smallest numerical input value. If the signal is falling, this block permanently stores new input values. If the signal is larger than the stored value, the stored value remains memorized. If, after a minimum value, the signal increases for a certain amount (digital noise constant) this memorized value is called a minimum and propagated to another register (minimum register). The same procedure (with opposite sign) applies to maximum values. The digital noise constant has a value 30H with one exception: If the PGA is in maximum amplification the digital noise constant is 48H. The noise constant is referred to the 8 bit Gain- Dac value. Each newly identified maximum starts another search for a new minimum. Each newly identified minimum starts another search for a new maximum. In this way alternating new minimum and maximum values can be identified. This ensures, that “all time high” or –low values do not remain in memory. Instead, only recent minimum and maximum values are obtainable. Valid and invalid min/max values After initialization, new calibration and PGA-changes the circuit starts a new search for minimum and maximum values. Assuming the process starts at a rising signal slope, then the initial point may become to a minimum since it is the lowest observed value so far. This occurrence is memorized, but the minimum is called an invalid minimum. The same can occur if the search starts at a falling edge for a maximum. A minimum is called a valid minimum if it is preceded by any (valid or invalid) maximum. The same is true for maximum values. Any minimum or maximum value is discarded immediately, if there is a new initialization, new calibration or a PGAchange. Startup of the device After power on or an internal reset a new calibration procedure is started. First, the external comparator output is locked. Second, the offset-DAC is set in that way, that it compensates the incoming signal. This is done by a successive approximation search. For a steady state input signal the offset DAC therefore gets the value of this input signal and the digital inputs are the digital representation of this value. For a varying signal the approximation search ends up in a value which is somewhere near the input signal during the duration of the successive approximation search. This is the initial calibration value. Of course the remaining offset value may still be quite large. Then the minimum and maximum search is started. After having found the first minimum or maximum the output switches according to the definition (low output Data Sheet Page 4 of 27 TLE4926C-HTN E6747 stage for maximum because of falling edge and high output stage for minimum because of rising edge). This behaviour continues until the first valid minimum and maximum values are found. With this pair of values there is sufficient information for getting a quite accurate new calibration result, so that the output can switch with the result given by the internal comparator. The average of the minimum and maximum value gives a representation of the offset. More precisely, the minimum and maximum value (8 bit values respectively) is summed up, the result is subtracted by 256 (=100H), this result is shifted to the correct position taking into account the current setting of the PGA, and finally this value is added to the current offset value. The whole procedure can be repeated for many times and converges to an offset value which compensates for the signal offset. In other words, if the minimum and the maximum have equal magnitude, their sum will be 100H (80H is the mid-value) and after subtraction of 100H a correction value of zero will appear. The shifter, which multiplies the sum off minimum a maximum in corresponding to the PGA position, calculates the offset- update. In PGA = 3 no shift is applied and the sum is added (or subtracted) directly from the offset. In PGA = 2 the sum is divided by 2, in PGA = 4 the sum is multiplied by 2 and so on. But the so calculated update is not applied every time; in fact there is a nonlinear filter that avoids small offsetcorrection in order to improve jitter. Continuous calibration Once the device has finished its first calibration it enters a continuous calibration mode. Basically this means that after each edge transition going out of the circuit a new offset value can be adjusted. To avoid a offset- jumping due to a unregular wheel or noise there is implemented a fincal state and a update filter. The algorithm enter in the fincal state if the difference between the maximum and minimum is less then 8 Lsb, and the finecal state will be left if the difference is more then 16 Lsb. Below the 8 Lsb value the offset is not changed, between 16 Lsb and 8 Lsb only 1 Lsb steps are done, and over the 16 Lsb threshold value full adjustment is possible. The update- filter lets perform the calculated update- step only if the last and the current update are over the 8 Lsb threshold an if the update- directions are the same. This avoids unwanted offset- updates due to long notches or teeth (long notches generate higher amplitudes). The offset calculation unit is protected against overrun errors so it will clip the values at zero and full scale (3FFH). A set of rules apply to the calibration process which regulate under which condition and to what amount an offset calibration is done. Mathematical relation between max, min, PGA and offset: Offset(mT)=Offset(Lsb) * Fullscale/1023(Lsb) – Fullscale/2; 120mT = Full-scale of the Offsetdac with 1023 Bit; Max(mT)=Offset(mT) + (Max(Lsb) – 128)*2^(PGA –3) * Fullscale/1023(Lsb); Min(mT)= Offset(mT) - (128 - Min(Lsb))*2^(PGA –3) * Fullscale/1023(Lsb); Data Sheet Page 5 of 27 TLE4926C-HTN E6747 Trigger rules for offset update in running mode As already mentioned, at either a positive or negative comparator edge the offset may be updated. At this time, several circuit conditions are checked. The following rules apply: After a modification of the PGA setting the update capability is disabled. With the 3rd following comparator edge the update capability is enabled again. After an offset update the update capability is disabled. With the 2nd following comparator edge the update capability is enabled again. At any offset update the circuit checks if there has been a larger signal value than that which is stored in the maximum register. In this case, the larger value will be taken. The same (with opposite sign) is true for minimum values. If a valid minimum or a valid maximum has been found and none of the above rules is against it, a calibration may occur. This must not be the first calibration after the initial calibration. Any calibration may occur only at the correct comparator edge. This means that a negative signal shift due to offset correction may occur only during the negative going signal slope. The same is true for positive signal shift and the rising signal slope. Watchdog operation If for a certain time (2^20 clock pulses – 0.7 s) there is no switching at the output the watchdog will start a new observation period. It is responsible for a new initialization by issuing a system reset. So a new selfcalibration (successive approximation of offset) is started and the PGA and GainDac are reseted (PGA=0, GainDac=100000 binary). During the selfcalibration the output is held to the old value, afterwards it is switched according to the edge-detection. The second check that is implemented is the PGA decrement: if no max or min is found during 16 output- switching events the PGA is decremented by 1. No other actions are performed if such a situation is detected. Digital main-comparator The digital main-comparator receives the output of the three threshold comparators hypcomp_low, main_comp and hypcomp_high. This inputs are used in an asynchronous way, so that no clock-delay is introduced. The function of the digital main-comparator is to implement a hidden hysteresis; that means, that the ouput switches accordingly to the main_comp threshold and the upper and lower hysteresis limits are used to lock the output. In this way no hysteresis is visible in the switching behavior and we have a high noise rejection. Summary The IC monitors the positive and negative peak values of the signal to adjust its offset properly. For large deviations the actual offset correction value is calculated as accurate as possible, for smaller deviations also a slow calibration mode by only incrementing and decrementing or by not changing the offset value can be entered. The device is monitored by a watchdog, which starts a new initialization if there is no input signal. Data Sheet Page 6 of 27 TLE4926C-HTN E6747 peak detection offset= (max + min) / 2 offset correction offset running-mode startup-mode Figure 3: Startup of the device At transition from startup-mode to running mode switching timing is moving from low-accuracy to high accuracy zero-crossing. Data Sheet Page 7 of 27 TLE4926C-HTN E6747 1.1 Absolute Maximum Ratings No. 1.1.1 Parameter Symbol min Supply voltage VS typ max Unit Remarks -18 18 V - -24 24 V 1h with RSeries ≥ 200Ω2 -26 26 V 5min with RSeries ≥ 200Ω1 -28 28 V 1min with RSeries ≥ 200Ω1 1.1.2 Supply current IS -10 25 mA - 1.1.3 Output OFF voltage VQ -0.3 18 V - -18 24 V 1h with RLoad ≥ 500Ω -18 26 V 5min with RLoad ≥ 500Ω -1.0 - V 1h (protected by internal series resistor) 1.1.4 Output ON voltage VQ - 16 V Current internal limited by Short circuit protection (72h @ TA < 40°C). - 18 V Current internal limited by short circuit protection (1h @ TA < 40°C). - 24 V Current internal limited by short circuit protection (1min @ TA < 40°C). 1.1.5 Continuous output IQ -50 Tj -40 50 mA - °C - 155 °C 5000 h (not additive) 165 °C 2500 h (not additive) 175 °C 500 h (not additive) 195 °C 10x1 h (additive to the current 1.1.6 Junction temperature other life times). 1.1.7 Storage temperature TS 1.1.8 Thermal resistance Rth JA -40 150 °C 190 K/W junction-air Lower values are possible with overmolded device. Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Accumulated life time Data Sheet Page 8 of 27 TLE4926C-HTN E6747 1.2 Electro Magnetic Compatibility - (values depend on RSeries!) Ref. ISO 7637-2; see test circuit of figure 4; ∆BPP = 10mT (ideal sinusoidal signal); VS=13.5V ± 0.5V, fB= 1000Hz; T= 25°C; RSeries ≥ 200Ω; No. Parameter Symbol Level/typ Status 1.2.1 Testpulse 1 VEMC III / -90V C Testpulse 2 III / 40V A3 Testpulse 3a IV / -150V A Testpulse 3b IV / 100V A Testpulse 4 IV / -7V A Testpulse 5 III / 66.5V C Note: Test criteria for status A: No missing pulse no additional pulse on the IC output signal plus duty cycle and jitter are in the specification limits. Test criteria for status B: No missing pulse no additional pulse on the IC output signal. (Output signal “OFF” means switching to the voltage of the pull-up resistor). Test criteria for status C: One or more parameter can be out of specification during the exposure but returns automatically to normal operation after exposure is removed. Test criteria for status E: IC destroyed. Ref. ISO 7637-3; TP 1 and TP 2 ref. DIN 40839-3; see test circuit of figure 4; ∆BPP = 10mT (ideal sinusoidal signal); VS=13.5V ± 0.5V, fB= 1000Hz; T= 25°C; RSeries ≥ 200Ω; No. Parameter Symbol Level/typ Status 1.2.2 Testpulse 1 VEMC IV / -30V A Testpulse 2 IV / 30V A Testpulse 3a IV / -60V A Testpulse 3b IV / 40V A Ref. ISO 11452-3; see test circuit of figure 4; measured in TEM-cell ∆BPP = 4mT (ideal sinusoidal signal); VS=13.5V ± 0,5V, fB= 200Hz; T= 25°C; RSeries ≥ 200Ω; No. 1.2.3 Parameter Symbol Level/max EMC field strength ETEM-Cell IV / 200V/m Remarks AM=80%, f=1kHz; Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Test condition for the trigger window: fB-field=200Hz, Bpp=4mT, vertical limits are ±200mV and horizontal limits are ±200µs. 3 Valid for general function, current consumption and jitter may be out of spec during test pulse 2. Data Sheet Page 9 of 27 TLE4926C-HTN E6747 1.3 ESD Protection No. 1.3.1 Parameter Symbol max Unit ESD – protection VESD ±4 kV Remarks According to standard EIA/JESD22-A114-B Human Body Model (HBM). 5V RSeries 200Ω VEMC CInt-package RLoad 47nF VS Q 4.7nF CLoad GND CInt-package Figure 4: Test circuit for EMC-tests Data Sheet 4.7kΩ Page 10 of 27 50pF TLE4926C-HTN E6747 2.1 Operating Range No. 2.1.1 Parameter Symbol Min Supply voltage VS 3.3 typ max Unit Remarks 18 V Continuous 24 V 1h with RSeries ≥ 200Ω; 26 V 5min with RSeries ≥ 200Ω. Extended limits for parameters in characteristics. 3 2.1.2 Supply voltage ripple VSAC 2.1.3 Continuous output OFF VQ voltage 2.1.4 Continuous output ON IQ V During test pulse 4 RSeries=200Ω; Ta=25°C Limited performance possible (jitter) 6 Vpp VS=13V; 0 < f < 50kHz 0 18 V Continuous 0 24 V 1h with RLoad ≥ 500Ω 0 20 mA VQmax=0.6V 1 ms Time to achieve specified accuracy current 2.1.5 Power on time ton After power on the output of the IC is always in high-state. After internal resets output is locked4. 2.1.6 Operating junction temperature Tj -40 °C - 155 °C 5000 h (not additive) 165 °C 2500 h (not additive) 175 °C 500 h (not additive) reduced signal quality permittable (e.g. jitter). Note: Unless otherwise noted, all temperatures refer to junction temperature. For the supply voltage lower than 28V (RSeries ≥ 200Ω) and junction temperature lower than 195°C the magnetic and AC/DC characteristics can exceed the specification limits. 4 Output of the IC is locked in present state (high-state or low-state) after an internal reset is launched. This reset happens typically every 780ms when there is no output switching in either case. See also 2.2.14. A voltage reset causes a release of the output and output is in high state after power on again. Data Sheet Page 11 of 27 TLE4926C-HTN E6747 2.2 AC/DC Characteristics Over operating range, unless otherwise specified. Typical values correspond to VS=12V and TA=25°C No. Parameter Symbol min typ max Unit Remarks 2.2.1 supply current IS 3 6.8 9 mA - 2.2.2 supply current @ 3.3V ISVmin 3 6.7 8 mA VS=3.3V 2.2.3 supply current @ 24V ISmax 3 7 9.5 mA VS=24V RSeries ≥ 200Ω 2.2.4 Output saturation VQsat 0.25 0.6 V IQ= 20mA 0.1 10 µA VQ= 18V voltage 2.2.5 Output leakage current IQleak 2.2.6 Current limit for short- IQshort 30 60 80 mA - Tprot 195 210 230 °C - 4 12 20 µs VLoad = 4.5 to 24V circuit protection 2.2.7 Junction temperature limit for output protection 2.2.8 Output rise time tr5 RLoad = 1.2kΩ; CLoad = 4.7nF included in package 2.2.9 Output fall time tf6 0.5 0.9 1.3 µs VLoad = 5V 0.65 1.15 1.65 µs VLoad = 12V RLoad = 1.2kΩ; CLoad = 4.7nF included in package 2.2.10 2.2.11 5 7 µs Only valid for Tj=25°C. Falling edge 20 µs Tj=-40°C -Tj=175°C Rising edge 8 µs Tj=-40°C -Tj=175°C Higher magnetic slopes and over -shoots reduce td, because the signal is filtered internal.9 µs Time over specified Delay time Temperature drift of td 7 12.5 18 25 ∆td -6 310 6 delay time of output to temperature range; magnetic edge not additional to td. value of capacitor: 4.7nF±10% (excluded drift due to temperature); ceramic: X7R; maximum voltage: 100V. The rise time is defined as the time between the 10 and 90% value. 6 see footnote 3. 7 Only valid for the falling edge 8 Not subject to production test-verified by design/characterisation 9 measured with a sinusoidal-field with 10mTpp and a frequency of 1kHz. 10 related to Tj=175°C. Data Sheet Page 12 of 27 TLE4926C-HTN E6747 2.2.12 Frequency range f 0.001 8 kHz Operation below 1Hz11 2.2.13 Oscillator frequency fOSC 1.08 1.34 1.68 MHz - treset 625 780 970 ms VSclamp 24 27.5 V IS = 20mA < 5min. 2.2.16 Clamping voltage Q- Pin VQclamp 24 27.5 V IQ = 20mA < 5min. 2.2.17 VsReset V - 2.2.14 Offset recalibration time after last output change 2.2.15 Clamping voltage Output locked to state before recalibration VS-Pin Note: Analog reset voltage 2.35 2.9 The listed AC/DC and magnetic characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not other specified, typical characteristics apply at Tj = 25 °C and VS = 12 V. 2.3 Magnetic Characteristics in Running Mode No. Parameter Symbol min 2.3.1 Bias preinduction B0 2.3.2 Differential bias induction 2.3.3 Minimum signal typ max Unit Remarks -500 500 mT - ∆B0 -30 30 mT - ∆Bmin 0.55 1.5 mT 100 mT Additional to B0 12. 0.2 mT F= 2N amplitude 2.3.4 Maximum signal ∆Bmax amplitude 2.3.5 Resistivity against ∆Bmin -0.2 mechanical stress (piezo) Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at Tj=25°C and the given supply voltage. 3.1 Self-calibration Characteristics No. Parameter Symbol 3.1.1 No. of magnetic edges for first output switching 3.1.2 No. of magnetic edges to enter calibrated mode 11 min typ max Unit Remarks nStart 2 - latest 2nd magnetic edge will cause output switching nCalib 613 - Low phase accuracy permitted. See 3.1.7 7th edge with high accuracy (calibrated) Output will switch if magnetic signal is changing more that 2x∆Bmin within offset recalibration time even below 1Hz once per magnetic edge, increased phase error is possible. 12 Exceeding this limit might result in decreased duty cycle performance. With higher values the internal measured signal will be clipped. This will decrease the phase accuracy. 13 Valid for sinusoidal signal without noise influence Data Sheet Page 13 of 27 TLE4926C-HTN E6747 3.1.3 Duty cycle in running Dty 45 50 55 % mode ∆BPP = 10mT ideal sinusoidal input signal (Tj=25°C) 40 50 60 % ∆BPP = 10mT ideal sinusoidal input signal (-40°C ≤ Tj < 175°C) 3.1.4 Signal jitter in running σ1 ≤ ±0.1114 % 5 mode; 1 sigma value ∆BPP = 10mT ideal sinusoidal input signal; Tj<150°C σ2 ≤ ±0.16 % ∆BPP = 10mT ideal sinusoidal input signal; 150°C ≤ Tj < 175°C 3.1.5 Signal Jitter in running σ3 ≤ ±0.11 % mode at Vs=13V and ripple ±3V 1 sigma value* 3.1.6 Effective noise value of sinusoidal input signal; Tj<150°C Bneff 25 the magnetic switching 70 points, 1 sigma value 3.1.7 After 3rdedge ≤ ±90 Magnetic edge 1-3 ≤ ±55 ≤ ±90 Frequency distribution of signal jitter µT Tj = 25°C; 15 µT The max value corresponds to the rms-values in the full temperature range and includes technological spreads. Related to calibrated switching behaviour. ∆BPP = 10mT ideal sinusoidal input signal ° Uncalibrated phase error Magnetic edge 1-2 3.1.8 ∆BPP = 10mT ideal Jitter shall be distributed 16 Magnetic fields close to 2x∆Bmin - like white noise 14 depends largely on∆Bmin, magnetic signal steepness and also on frequency. The magnetic noise is normal distributed, nearly independent to frequency and without sampling noise or digital noise effects. The typical value represents the rms-value here and corresponds therefore to 1σ probability of normal distribution. Consequently a 3σ value corresponds to 0.3% probability of appearance. 16 smaller phase errors are possible at higher signal amplitudes, because sinus signal changes to a more rectangle signal. 15 Data Sheet Page 14 of 27 TLE4926C-HTN E6747 B Bmax ∆B 50% ∆BPP Bmin ∆BPP = 2 x ∆B ∆B=B1-B2 (signal amplitude) t UQ tr VQ-High tf 90% td VQ-Low 50% 10% t1 T t Figure 5 Switching direction Signal T ∆T t σ 1...σ 3 = 1 1 ⋅ ⋅ ∑ (∆T ) 2 T (n − 1) measurement condition: n ≥ 1000 Figure 6 Data Sheet Definition of signal jitter Page 15 of 27 TLE4926C-HTN E6747 Application Configurations Two possible applications are shown in Figure 7 and Figure 8 (Toothed and Magnet Wheel). The difference between two-wire and three-wire application is shown in Figure 11 for the TLE 4926C. Gear Tooth Sensing In the case of ferromagnetic toothed wheel application the IC has to be biased by the south or north pole of a permanent magnet (e.g. SmCO5 (Vacuumschmelze VX145)) with the dimensions 8 mm × 5 mm × 3 mm) which should cover both Hall probes. The maximum air gap depends on − the magnetic field strength (magnet used; pre-induction) and − the toothed wheel that is used (dimensions, material, etc.; resulting differential field). a centered distance of Hall probes b Hall probes to IC surface L IC surface to tooth wheel a = 2.5 mm b = 0.3 mm S N N S b L a AEA01259 Figure 7 Sensor Spacing T d AEA01260 DIN d z m T diameter (mm) number of teeth module m = d/z (mm) pitch T = π × m (mm) Figure 8 Data Sheet Conversion DIN – ASA m = 25.4 mm/p T = 25.4 mm CP ASA p diameter pitch p = z/d (inch) PD pitch diameter PD = z/p (inch) CP circular pitch CP = 1 inch × π/p Toothed Wheel Dimensions Page 16 of 27 TLE4926C-HTN E6747 Gear Wheel Hall Sensor Hall Sensor 11 Signal Processing Hall Sensor 2 S (N) N (S) Circuitry Permanent Magnet N (N) (S) S Figure 9 AEA01261 TLE 4926C, with Ferromagnetic Toothed Wheel Magnet Wheel S S N Hall Sensor 1 Hall Sensor 2 Signal Processing AEA01262 Circuitry Figure 10 Data Sheet TLE4926C, with Magnet Wheel Page 17 of 27 TLE4926C-HTN E6747 1 3 2 for example: RL=1,2kΩ RS=120Ω 1 3 2 for example: RP≥200Ω RL=1,2kΩ Figure 11 Data Sheet Application Circuits TLE4926C Page 18 of 27 TLE4926C-HTN E6747 S (N) N (S) Pin 3 (Q) Pin 1 (Vs) B2 B1 Branded Side Crankshaft Wheel Profile Magnetic Field Difference ∆B=B1-B2 Large airgap Small airgap ∆BENOP=1mT Hidden Hysteresis ∆BHYS=2mT ∆BENRP=-1mT Output Signal VQ Enabling point for releasing output: B1-B2<∆BENRP switches the output OFF (VQ=HIGH) Enabling point for operate point: B1-B2>∆BENOP switches the output ON (VQ=LOW) ∆BHYS=|∆BENOP-∆BENRP| Outside of a permanent magnet the magnetic induction (=flux density) points from north to the south pole. It is common to define positive flux if the south pole of a magnet is on the branded side of the IC. This is equivalent to the north pole of the magnet on the rear side of the IC. Figure 12 Data Sheet System Operation with hidden hysteresis Page 19 of 27 TLE4926C-HTN E6747 PG-SSO-3-91 (Plastic Single Small Outline) Figure 13 Data Sheet Package Dimensions (PG-SSO-3-91) Page 20 of 27 TLE4926C-HTN E6747 Figure 14 Data Sheet Hall probe spacing in the PG-SSO-3-91 package Page 21 of 27 TLE4926C-HTN E6747 Figure 15 Data Sheet Tape Loading Orientation in the PG-SSO-3-91 package Page 22 of 27 TLE4926C-HTN E6747 Appendix: Calculation of mechanical errors: Magnetic Signal Output Signal ϕ ∆ϕ ∆ϕ Figure 16: Systematic Errorϕ and Stochastic Error ∆ϕ Systematic Phase Error ϕ The systematic error comes in because of the delay-time between the threshold point and the time when the output is switching. It can be calculated as follows: ϕ= ϕ n td 360° • n • td 60 ... systematic phase error in ° -1 ... speed of the camshaft-wheel in min ... delay time (see specification) in sec Systematic Phase Error ∆ϕ The systematic phase error includes the error due to the variation of the delay time with temperature and the error caused by the resolution of the threshold. It can be calculated in the following way: Data Sheet Page 23 of 27 TLE4926C-HTN E6747 ∆ϕd = ∆ϕd n ∆td 360° • n • ∆td 60 ... systematic phase error due to the variation of the delay time over temperature in ° … speed of the camshaft wheel in min-1 … variation of delay time over temperature in sec Jitter (Repeatability) The phase jitter is normally caused by the analogue system noise. If there is an update of the offset-DAC due to the algorithm, what could happen after each tooth, then an additional step in the phase occurs (see description of the algorithm). This is not included in the following calculations. The noise is transformed through the slope of the magnetic edge into a phase error. The phase jitter is determined by the two formulas: B ∂B ∂ϕ Bdiff_max Bdiff_typ 1σ 3σ Noise ϕ Phase-Jitter Figure17: Phase-Jitter ϕJitter_typ ϕJitter_max ∂ϕ ∂B Bneff_typ Bneff_max Data Sheet ϕ Jitter _ typ = ∂ϕ • (Bneff _ typ ) ∂B ϕ Jitter _ max = ∂ϕ • (Bneff _ max ) ∂B ... ... ... typical phase jitter at Tj=25°C in ° (1Sigma) maximum phase jitter at Tj=175°C in ° (3Sigma) inverse of the magnetic slope of the edge in °/T ... ... typical value of Bdiff in T (1σ-value at Tj=25°C) maximum value of Bdiff in T (3σ-value at Tj=175°C) Page 24 of 27 TLE4926C-HTN E6747 Example: Assumption: n = 4500 min-1 td = 14 µs ∆td = ±3 µs ∂B ∂ϕ = 3 mT/° Bneff_typ = ±40 µT (1σ-value at Tj=25°C) Bneff_max = ±210 µT (3σ-value at Tj=175°C) Calculation: Data Sheet ϕ = 0.378° ∆ϕd = ±0.081° ϕJitter_typ = ±0.013° ϕJitter_max = ±0.07° ... ... ... ... systematic phase error systematic phase error due to delay time variation typical phase jitter (1σ-value at Tj=25°C) maximum phase jitter (3σ-value at Tj=175°C) Page 25 of 27 TLE4926C-HTN E6747 Appendix A: Marking & data matrix code information: Product is RoHS (restriction of hadzardous substances) compliant when marked with letter “G” in front or after the date code marking. As mentioned in information note N° 136/03 a data matrix code with 8x18 fields according to the ECC200 standard may be used for sensor production. Furthermore the marking technique on the front side of the device may be changed from a mask to a writing laser equipment. The information content (date code and device type) will hereby not be changed. Please refer to your Key account team or regional sales responsible if you need further information. Example for data matrix code (rear side of sensor): Data Sheet Page 26 of 27 TLE4926C-HTN E6747 Revision History: April 2007 Version 3.0 Previous Version: 2.1 Page 1 1 6 8, 11 9 10 11 Subjects (major changes since last revision) Data sheet is valid for 8” products Ordering code updated Watchdog reset condition updated Output OFF voltage typing error corrected EMC performance conducted pulses ISO7637-1 TP1 and TP5 updated ESD performance updated Footnote 2: Watchdog reset condition updated Infineon Technologies AG © Infineon Technologies AIM SC All Rights Reserved. http://www.infineon.com/products/sensors We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Data Sheet Page 27 of 27