TI TMS626812B

TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
D
D
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D
D
D
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D
Organization
1048576 by 8 Bits by 2 Banks
3.3-V Power Supply (± 10% Tolerance)
Two Banks for On-Chip Interleaving
(Gapless Accesses)
High Bandwidth – Up to 125-MHz Data
Rates
CAS Latency (CL) Programmable to
2 or 3 Cycles From Column-Address Entry
Burst Sequence Programmable to Serial or
Interleave
Burst Length Programmable to 1, 2, 4, or 8
Chip Select and Clock Enable for Enhanced
System Interfacing
Cycle-by-Cycle DQ Bus Mask Capability
Auto-Refresh and Self-Refresh Capabilities
4K Refresh (Total for Both Banks)
High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
Power-Down Mode
Compatible With JEDEC Standards
Pipeline Architecture
Temperature Ranges
Operating, 0°C to 70°C
Storage, – 55°C to 150°C
Intel PC100 Compliant (-8A, -8, and
-10 Devices)
Performance Ranges:
SYNCHRONOUS
CLOCK
CYCLE TIME
tCK3
tCK2
(CL† = 3) (CL = 2)
ACCESS TIME
(CLOCK TO
OUTPUT)
tAC3
tAC2
(CL = 3)
(CL = 2)
TMS626812B
DGE PACKAGE
( TOP VIEW )
VCC
DQ0
VSSQ
DQ1
VCCQ
DQ2
VSSQ
DQ3
VCCQ
NC
NC
W
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
8 ns
10 ns
6 ns
6 ns
’626812B-8A
8 ns
15 ns
6 ns
7 ns
64 ms
64 ms
’626812B-10
10 ns
15 ns
7.5 ns
7.5 ns
64 ms
† CL = CAS latency
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
VSS
DQ7
VSSQ
DQ6
VCCQ
DQ5
VSSQ
DQ4
VCCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
PIN NOMENCLATURE
REFRESH
TIME
INTERVAL
’626812B-8
1
A0 – A10 Address Inputs
A0 – A10 Row Addresses
A0 – A8 Column Addresses (for TMS626812B)
A10 Automatic-Precharge Select
A11
Bank Select
CAS
Column-Address Strobe
CKE
Clock Enable
CLK
System Clock
Chip Select
CS
DQ[0 :7] SDRAM Data Input / Output (TMS626812B)
DQM
Data-Input / Data-Output Mask Enable
NC
No External Connect
RAS
Row-Address Strobe
VCC
Power Supply (3.3-V Typical)
VCCQ
Power Supply for Output Drivers
(3.3-V Typical)
VSS
Ground
VSSQ
Ground for Output Drivers
W
Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
description
The TMS626812B is a high-speed, 16 777 216-bit synchronous dynamic random-access memory (SDRAM)
device organized as follows:
D
Two banks of 1 048 576 words with 8 bits per word (TMS626812B)
All inputs and outputs of the TMS626812B series are compatible with the LVTTL interface.
The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and
outputs are synchronized with the CLK input to simplify system design and enhance the use with high-speed
microprocessors and caches.
The TMS626812B SDRAM is available in a 400-mil, 44-pin surface-mount thin small–outine package (TSOP)
(DGE suffix).
functional block diagram
CLK
CKE
Array Bank T
CS
DQM
RAS
CAS
W
A0 – A11
DQ
Buffer
Control
8
DQ0 – DQ7
Array Bank B
12
Mode Register
operation
All inputs of the ’626812B SDRAM are latched on the rising edge of the system (synchronous) clock. The
outputs, DQx, also are referenced to the rising edge of CLK. The ’626812B has two banks that are accessed
independently. A bank must be activated before it can be accessed (read from or written to). Refresh cycles
refresh both banks alternately.
Six basic commands or functions control most operations of the ’626812B:
D
D
D
D
D
D
2
Bank activate / row-address entry
Column-address entry / write operation
Column-address entry / read operation
Bank deactivate
Auto-refresh
Self-refresh
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TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
operation (continued)
Additionally, operations can be controlled by three methods: using chip select (CS) to select / deselect the
devices, using DQM to enable / mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend the
CLK input. The device contains a mode register that must be programmed for proper operation.
Table 1, Table 2, and Table 3 show the various operations that are available on the ’626812B. These function
tables identify the command and / or operations and their respective mnemonics. Each table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any read or write command in
progress at cycle n. Access operations include the cycle upon which the read or write command is entered and
all subsequent cycles through the completion of the access burst.
Table 1. Basic Command Function Table†
COMMAND‡
Mode register set
Bank deactivate (precharge)
Deactivate all banks
STATE OF
BANK(S)
CS
RAS
CAS
W
A11
A10
A0 – A9
MNEMONIC
T = deac
B = deac
L
L
L
L
X
X
A0 – A6 = V
A7 – A8 = 0
A9 = V
MRS
X
L
L
H
L
BS
L
X
DEAC
X
L
L
H
L
X
H
X
DCAB
Bank activate / row-address entry
SB = deac
L
L
H
H
BS
V
V
ACTV
Column-address entry / write operation
SB = actv
L
H
L
L
BS
L
V
WRT
Column-address entry / write operation
with automatic deactivate
SB = actv
L
H
L
L
BS
H
V
WRT-P
Column-address entry / read operation
SB = actv
L
H
L
H
BS
L
V
READ
Column-address entry / read operation
with automatic deactivate
SB = actv
L
H
L
H
BS
H
V
READ-P
X
L
H
H
H
X
X
X
NOOP
X
H
X
X
X
X
X
X
DESL
T = deac
B = deac
L
L
L
H
X
X
X
REFR
No operation
Control-input inhibit / no operation
Auto-refresh§
† For exception of these commands on cycle n, one of the following must be true:
– CKE(n–1) must be high.
– tCESP must be satisfied for power-down exit.
– tCESP and tRC must be satisfied for self-refresh exit.
– tIS and nCLE must be satisfied for clock-suspend exit.
DQM(n) is a don’t care.
‡ All other unlisted commands are considered vendor-reserved commands or illegal commands.
§ Auto-refresh or self-refresh entry requires that all banks be deactivated or be in an idle state prior to the command entry.
Legend:
n
= CLK cycle number
L
= Logic low
H
= Logic high
X
= Don’t care, either logic low or logic high
V
= Valid
T
= Bank T
B
= Bank B
actv = Activated
deac = Deactivated
BS
= Logic high to select bank T; logic low to select bank B
SB
= Bank selected by A11 at cycle n
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TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
operation (continued)
Table 2. Clock-Enable (CKE) Command Function Table†
COMMAND‡
Self-refresh entry
Power-down entry on cycle (n+1)§
STATE OF BANK(S)
CKE
(n – 1)
CKE
(n)
CS
(n)
RAS
(n)
CAS
(n)
W
(n)
MNEMONIC
T = deac
B = deac
H
L
L
L
L
H
SLFR
T = no access operation¶
B = no access operation¶
H
L
X
X
X
X
PDE
L
H
L
H
H
H
—
Self refresh exit
Self-refresh
T = self-refresh
B = self-refresh
L
H
H
X
X
X
—
Power-down exit#
T = power down
B = power down
L
H
X
X
X
X
—
CLK suspend on cycle (n+1)
T = access operation¶
B = access operation¶
H
L
X
X
X
X
HOLD
CLK suspend exit on cycle (n+1)
T = access operation¶
B = access operation¶
L
H
X
X
X
X
—
† For execution of these commands, A0 – A11(n) and DQM(n) are don’t care entries.
‡ All other unlisted commands are considered as vendor-reserved or illegal commands.
§ On cycle n, the device executes the respective command (listed in Table 1). On cycle (n+1), the device enters power-down mode.
¶ A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
# If setup time from CKE high to the next CLK high satisfies tCESP , the device executes the respective command (listed in Table 1). Otherwise,
either the DESL or the NOOP command must be applied before any other command.
Legend:
n
= CLK cycle number
L
= Logic low
H
= Logic high
X
= Don’t care, either logic low or logic high
T
= Bank T
B
= Bank B
deac = Deactivated
4
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TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
operation (continued)
Table 3. Data-Mask (DQM) Command Function Table†
STATE OF BANK(S)
DQM
(n)
DATA IN
(n)
DATA OUT
(n+2)
MNEMONIC
—
T = deac
and
B = deac
X
N/A
Hi-Z
—
—
T = actv
and
B = actv
( no access operation )§
X
N/A
Hi-Z
—
Data-in enable
T = write
or
B = write
L
V
N /A
ENBL
Data-in mask
T = write
or
B = write
H
M
N /A
MASK
Data-out enable
T = read
or
B = read
L
N /A
V
ENBL
Data-out mask
T = read
or
B = read
H
N /A
Hi-Z
MASK
COMMAND‡
† For exception of these commands on cycle n, one of the following must be true:
– CKE(n–1) must be high.
– tCESP must be satisfied for power-down exit.
– tCESP and tRC must be satisfied for self-refresh exit.
– tIS and nCLE must be satisfied for clock-suspend exit.
CS(n), RAS(n), CAS(n), W(n), and A0 – A11(n) are don’t care except for interrupt conditions.
‡ All other unlisted commands are considered vendor-reserved commands or illegal commands.
§ A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
Legend:
n
= CLK cycle number
L
= Logic low
H
= Logic high
Hi-Z = High-impedance state
X
= Don’t care, either logic low or logic high
V
= Valid
M
= Masked input data
N /A = Not applicable
T
= Bank T
B
= Bank B
actv = Activated
deac = Deactivated
write = Activated and accepting data inputs on cycle n
read = Activated and delivering data outputs on cycle (n + 2)
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TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
burst sequence
All data for the ’626812B are written or read in a burst fashion — that is, a single starting address is entered
into the device and the ’626812B internally accesses a sequence of locations based on that starting address.
After the first access, some subsequent accesses can be at preceding, as well as succeeding, column
addresses, depending on the starting address entered. This sequence can be programmed to follow either a
serial burst or an interleave burst (see Table 4, Table 5, and Table 6). The length of the burst can be programmed
to be 1, 2, 4, or 8 accesses (see the section on setting the mode register). After a read burst is complete (as
determined by the programmed burst length), the outputs are in the high-impedance state until the next read
access is initiated.
Table 4. 2-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A0
DECIMAL
BINARY
START
2ND
START
2ND
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
Serial
Interleave
Table 5. 4-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A0 – A1
DECIMAL
Serial
Interleave
6
BINARY
START
2ND
3RD
4TH
START
2ND
3RD
0
1
2
3
00
01
10
11
1
2
3
0
01
10
11
00
2
3
0
1
10
11
00
01
3
0
1
2
11
00
01
10
0
1
2
3
00
01
10
11
1
0
3
2
01
00
11
10
2
3
0
1
10
11
00
01
3
2
1
0
11
10
01
00
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4TH
TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
burst sequence (continued)
Table 6. 8-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A0 – A2
DECIMAL
BINARY
START
2ND
3RD
4TH
5TH
6TH
7TH
8TH
START
2ND
3RD
4TH
5TH
6TH
7TH
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
1
2
3
4
5
6
7
0
001
010
011
100
101
110
111
000
2
3
4
5
6
7
0
1
010
011
100
101
110
111
000
001
3
4
5
6
7
0
1
2
011
100
101
110
111
000
001
010
4
5
6
7
0
1
2
3
100
101
110
111
000
001
010
011
5
6
7
0
1
2
3
4
101
110
111
000
001
010
011
100
6
7
0
1
2
3
4
5
110
111
000
001
010
011
100
101
7
0
1
2
3
4
5
6
111
000
001
010
011
100
101
110
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
1
0
3
2
5
4
7
6
001
000
011
010
101
100
111
110
2
3
0
1
6
7
4
5
010
011
000
001
110
111
100
101
3
2
1
0
7
6
5
4
011
010
001
000
111
110
101
100
4
5
6
7
0
1
2
3
100
101
110
111
000
001
010
011
5
4
7
6
1
0
3
2
101
100
111
110
001
000
011
010
6
7
4
5
2
3
0
1
110
111
100
101
010
011
000
001
7
6
5
4
3
2
1
0
111
110
101
100
011
010
001
000
Serial
Interleave
8TH
latency
The beginning data-out cycle of a read burst can be programmed to occur two or three CLK cycles after the read
command (see the section on setting the mode register). This feature allows adjustment of the device so that
it operates using the capability to latch the data output from the ’626812B. The delay between the READ
command and the beginning of the output burst is known as CAS latency. After the initial output cycle begins,
the data burst occurs at the CLK frequency without any intervening gaps. Use of minimum read latencies is
restricted, based on the maximum frequency rating of the ’626812B.
There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same
rising edge of CLK that the WRT command is entered. The write latency is fixed and is not determined by the
contents of the mode register.
two-bank operation
The ’626812B contains two independent banks that can be accessed individually or in an interleaved fashion.
Each bank must be activated with a row address before it can be accessed. Each bank must then be deactivated
before it can be activated again with a new row address. The bank-activate / row-address-entry command
(ACTV) is entered by holding RAS low, CAS high, W high, and A11 valid on the rising edge of CLK. A bank can
be deactivated either automatically during a READ-P or a WRT-P command or by using the bank-deactivate
command (DEAC). Both banks can be deactivated at once by using the DCAB command (see Table 1 and the
section on bank deactivation).
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TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
two-bank row-access operation
The two-bank feature allows access of information on random rows at a higher rate of operation than is possible
with a standard DRAM by activating one bank with a row address and, while the data stream is being accessed
to / from that bank, activating the second bank with another row address. When the data stream to or from the
first bank is completed, the data stream to or from the second bank can begin without interruption. After the
second bank is activated, the first bank can be deactivated to allow the entry of a new row address for the next
round of accesses. In this manner, operation can continue in an interleaved fashion. Figure 24 shows an
example of two-bank row-interleaving read bursts with automatic deactivate for a CAS latency of three and a
burst length of eight.
two-bank column-access operation
The availability of two banks allows the access of data from random starting columns between banks at a higher
rate of operation. After activating each bank with a row address (ACTV command), A11 can be used to alternate
READ or WRT commands between the banks to provide gapless accesses at the CLK frequency, provided all
specified timing requirements are met. Figure 25 is an example of two-bank column-interleaving read bursts
for a CAS latency of three and a burst length of two.
bank deactivation (precharge)
Both banks can be simultaneously deactivated (placed in precharge) by using the DCAB command. A single
bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB
command except that A10 must be low and A11 is used to select the bank to be precharged (see Table 1).
A bank can also be deactivated automatically by using A10 during a read or write command. If A10 is held high
during the entry of a read or write command, the accessed bank (selected by A11) is automatically deactivated
upon completion of the access burst. If A10 is held low during the entry of a read or write command, that bank
remains active following the burst. The read and write commands with automatic deactivation are signified as
READ-P and WRT-P, respectively.
chip select (CS)
CS can be used to select or deselect the ’626812B for command entry, which can be required for multiple
memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device does not
respond to RAS, CAS, or W until the device is selected again by holding CS low on the rising edge of CLK. Any
other valid command can be entered simultaneously on the same rising CLK edge of the select operation. The
device can be selected / deselected on a cycle-by-cycle basis (see Table 1 and Table 2). The use of CS does
not affect an access burst that is in progress; the DESL command can restrict only RAS, CAS, and W inputs
to the ’626812B.
data mask
The MASK command or its opposite, the data-in enable (ENBL) command (see Table 3), is performed on a
cycle-by-cycle basis to gate any data cycle within a read burst or a write burst. The application of DQM to a write
burst has no latency (nDID = 0 cycle), but the application of DQM to a read burst has a latency of nDOD = 2 cycles.
During a write burst, if DQM is held high on the rising edge of CLK, the data input is ignored on that cycle. When
DQM is held high nDOD cycles after the rising edge of the CLK during a read burst, the data output goes to the
high-impedance state. Figure 16 and Figure 28 show examples of data-mask operations.
CLK suspend/power-down mode
For normal device operation, CKE should be held high to enable CLK. If CKE goes low during the execution
of a READ (READ-P) or WRT (WRT-P) operation, the state of the DQ bus at the immediate next rising edge
of CLK is frozen at its current state, and no further inputs are accepted until CKE returns high. This is known
8
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TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
CLK suspend/power-down mode (continued)
as a CLK-suspend operation and its execution indicates a HOLD command. The device resumes operation from
the point where it was placed in suspension, beginning with the second rising edge of CLK after CKE returns
high.
If CKE is brought low when no read or write command is in progress, the device enters power-down mode. If
both banks are deactivated when power-down mode is entered, power consumption is reduced to a minimum.
Power-down mode can be used during row-active or auto-refresh periods to reduce input buffer power. After
power-down mode is entered, no further inputs are accepted until CKE returns high. To ensure that data in the
device remains valid during the power-down mode, the self-refresh command ( SLFR) must be executed
concurrently with the power-down entry ( PDE) command. When exiting power-down mode, new commands
can be entered on the first CLK edge after CKE returns high, provided that the setup time (tCESP) is satisfied.
Table 2 shows the command configuration for a CLK suspend / power-down operation. Figure 17, Figure 18,
and Figure 31 show examples of the procedure.
setting the mode register
The ’626812B contains a mode register that must be programmed with the CAS latency, the burst type, and the
burst length. This is accomplished by executing a mode-register set (MRS) command with the information
entered on address lines A0 – A9. A logic 0 must be entered on A7 and A8, but A10 and A11 are don’t-care entries
for the ’626812B. When A9 = 1, the write-burst length is always 1. When A9 = 0, the write-burst length is defined
by A0 – A2. Figure 1 shows the valid combinations for a successful MRS command. Only valid addresses allow
the mode register to be changed. If the addresses are not valid, the previous contents of the mode register
remain unaffected. The MRS command is executed by holding RAS, CAS, and W low, and the input-mode word
valid on A0 – A9 on the rising edge of CLK (see Table 1). The MRS command can be executed only when both
banks are deactivated.
A11
A10
Reserved
A9
A8
A7
0
0
A6
A5
A4
A3
A2
A1
A0
0 = Serial
1 = Interleave
(burst type)
REGISTER BITS†
REGISTER BIT
A9
WRITE BURST
WRITE-BURST
LENGTH
A6
A5
A4
CAS
LATENCY‡
0
1
A2 – A0
1
0
0
1
1
0
1
2
3
REGISTER BITS§
A2
A1
A0
BURST
LENGTH
0
0
0
0
0
0
1
1
0
1
0
1
1
2
4
8
† All other combinations are reserved.
‡ Refer to timing requirements for minimum valid-read latencies based on maximum frequency rating.
§ All other combinations are reserved.
Figure 1. Mode-Register Programming
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TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
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refresh
The ’626812B must be refreshed such that all 4 096 rows are accessed within tREF (see timing requirements)
or data cannot be retained. Refresh can be accomplished by performing a series of ACTV and DEAC commands
to every row in both banks, by performing 4 096 auto-refresh (REFR) commands, or by placing the device in
self-refresh mode. Regardless of the method used, all rows must be refreshed before tREF has expired.
auto-refresh (REFR)
Before performing a REFR command, both banks must be deactivated (placed in precharge). To enter a REFR
command, RAS and CAS must be low and W must be high on the rising edge of CLK (see Table 1). The refresh
address is generated internally such that after 4 096 REFR commands, both banks of the ’626812B have been
refreshed. The external address and bank select (A11) are ignored. The execution of a REFR command
automatically deactivates both banks upon completion of the internal auto-refresh cycle, allowing consecutive
REFR-only commands to be executed, if desired, without any intervening DEAC commands. The REFR
commands do not necessarily have to be consecutive, but all 4 096 must be completed before tREF expires.
self refresh (SLFR)
To enter self refresh, both banks of the ’626812B must first be deactivated and a SLFR command must be
executed (see Table 2). The SLFR command is identical to the REFR command except that CKE is low. For
proper entry of the SLFR command, CKE is brought low for the same rising edge of CLK that RAS and CAS
are low and W is high. CKE must be held low to stay in self-refresh mode. In the self-refresh mode, all refreshing
signals are generated internally for both banks with all external signals (except CKE) being ignored. Data is
retained by the device automatically for an indefinite period when power is maintained and power consumption
is reduced to a minimum. To exit self-refresh mode, CKE must be brought high. New commands may be issued
only after tRC has expired. If CLK is made inactive during self refresh, it must be returned to an active and stable
condition before CKE is brought high to exit self refresh (see Figure 19).
Upon exiting self refresh, 4 096 REFR commands must be executed before continuing with normal device
operations. This ensures that the SDRAM is fully refreshed.
interrupted bursts
A read burst or write burst can be interrupted before the burst sequence has been completed with no adverse
effects to the operation, by entering certain superseding commands (see Table 7 and Table 8), provided that
all timing requirements are met. A DEAC command is considered an interrupt only if it is issued to the same
bank as the preceding READ or WRT command. The interruption of READ-P or WRT-P operations is not
supported.
10
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interrupted bursts (continued)
Table 7. Read-Burst Interruption
INTERRUPTING
COMMAND
READ, READ-P
WRT, WRT-P
DEAC, DCAB
EFFECT OR NOTE ON USE DURING READ BURST
Current output cycles continue until the programmed latency from the superseding READ (READ-P) command is
met and new output cycles begin (see Figure 2).
The WRT (WRT-P) command immediately supersedes the read burst in progress. To avoid data contention, DQM
must be high before the WRT (WRT-P) command to mask output of the read burst on cycles (nCCD–1), nCCD, and
(nCCD+1), assuming that there is any output on these cycles (see Figure 3).
The DQ bus is in the high-impedance state when nHZP cycles are satisfied or when the read burst completes,
whichever occurs first (see Figure 4).
nCCD = 1 Cycle
CLK
Output Burst for the
Interrupting READ
Command Begins Here
READ Command
at Column Address C0
Interrupting
READ Command
at Column Address C1
C0
DQ
C1
C1 + 1
C1 + 2
NOTE A: For these examples, assume CAS latency = 3 and burst length = 4.
Figure 2. Read Burst Interrupted by Read Command
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interrupted bursts (continued)
nCCD = 5 Cycles
CLK
Interrupting
WRT Command
READ Command
DQ
Q
D
See Note B
DQM
NOTES: A. For this example, assume CAS latency = 3 and burst length = 4.
B. DQM must be high to mask output of the read burst on cycles (nCCD – 1), nCCD, and (nCCD + 1).
Figure 3. Read Burst Interrupted by Write Command
nCCD = 2 Cycles
nHZP3
CLK
READ Command
Interrupting
DEAC/DCAB
Command
Q
DQ
Q
NOTE A: For this example, assume CAS latency = 3 and burst length = 4.
Figure 4. Read Burst Interrupted by DEAC Command
12
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TMS626812B
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interrupted bursts (continued)
Table 8. Write-Burst Interruption
INTERRUPTING
COMMAND
EFFECT OR NOTE ON USE DURING WRITE BURST
READ, READ-P
Data in on the previous cycle is written; however, no further data in is accepted (see Figure 5).
WRT, WRT-P
The new WRT (WRT-P) command and data in immediately supersede the write burst in progress (see Figure 6).
DEAC, DCAB
The DEAC / DCAB command immediately supersedes the write burst in progress. DQM must be used to mask the
DQ bus such that the write recovery specification (tWR ) is not violated by the interrupt (see Figure 7).
nCCD = 1 Cycle
CLK
WRT
Command
DQ
READ
Command
D
Q
Q
Q
NOTE A: For these examples, assume CAS latency = 3 and burst length = 4.
Figure 5. Write Burst Interrupted by Read Command
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interrupted bursts (continued)
nCCD = 2 Cycles
CLK
WRT Command at
Column Address C0
C0
DQ
Interrupting
WRT Command
at Column Address C1
C0 + 1
C1
C1 + 1
C1 + 2
C1 + 3
NOTE A: For this example, assume burst length = 4.
Figure 6. Write Burst Interrupted by Write Command
nCCD = 3 Cycles
CLK
WRT Command
DQ
D
Interrupting
DEAC or DCAB
Command
D
Ignored
Ignored
tWR
DQM
NOTE A: For this example, assume burst length = 4.
Figure 7. Write Burst Interrupted by DEAC/DCAB Command
power-up sequence
Device initialization must be performed after a power up to the full VCC level. After power is established, a 200-µs
interval is required (with no inputs other than CLK). After this interval, both banks of the device must be
deactivated. Eight REFR commands must be performed and the mode register must be set to complete the
device initialization.
14
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absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Supply voltage range for output drivers, VCCQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions (see Notes 2 and 3)
MIN
NOM
MAX
UNIT
VCC
VCCQ
Supply voltage
3
3.3
3.6
V
Supply voltage for output drivers
3
3.3
3.6
V
VSS
VSSQ
Supply voltage
VIH
VIL
High-level input voltage
2
Low-level input voltage
0
Supply voltage for output drivers
0
TA
Ambient temperature
NOTES: 2. VIL MIN = – 1.5 V ac (pulse width
3. VCCQ
VCC + 0.3 V
v
V
v 5 ns)
V
V
– 0.3
VCC + 0.3
0.8
0
70
°C
V
maximum ac operating conditions (see Notes 4 and 5)
VIH
VIL
High-level input voltage
Low-level input voltage
MIN
MAX
UNIT
2
VCCQ + 2.0
0.8
V
VSSQ – 2.0
v
V
NOTES: 4. The overshoot and undershoot voltage duration
3 ns with no input clamp diode.
5. The VCCQ and VSSQ are the operating parameters (not absolute maximum parameters).
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VOH
VOL
High-level output voltage
Low-level output voltage
IOH = –4 mA
IOL = 4 mA
II
IO
Input current (leakage)
0 V ≤ VI ≤ VCC + 0.3 V,
Output current (leakage)
0 V ≤ VO ≤ VCC + 0.3 V,
ICC1
Operating current
Burst length = 1, tRC
tRC MIN
IOH/IOL = 0 mA,
mA 1 bank activated
(see Notes 7, 8, and 9)
ICC2P
ICC2PS
Precharge
g standbyy current
in power-down mode
CKE
Precharge
g standby
y current
in non-power-down mode
CKE
ICC2N
ICC2NS
ICC3P
ICC3PS
Active standby
y current in
power-down mode
ICC3N
ICC3NS
Active standbyy current in
non-power-down mode
ICC4
Burst current
ICC5
Auto refresh current
Auto-refresh
’626812B-8
TEST CONDITIONS
’626812B-8A
MAX
2.4
w
v
MIN
MIN
MAX
2.4
’626812B-10
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
All other pins = 0 V to VCC
±10
±10
±10
µA
Output disabled
±10
±10
±10
µA
CAS latency = 2
95
95
85
mA
CAS latency = 3
100
100
90
mA
1
1
1
mA
1
1
1
mA
30
30
30
mA
2
2
2
mA
3
3
3
mA
3
3
3
mA
40
40
40
mA
10
10
10
mA
VIL MAX, tCK = 15 ns (see Note 10)
CKE and CLK
VIL MAX, tCK = ∞ (see Note 11)
v
w VIH MIN, tCK = 15 ns (see Note 10)
CKE w VIH MIN, CLK v VIL MAX, tCK = ∞ (see Note 11)
CKE v VIL MAX, tCK = 15 ns (see Notes 7 and 10)
CKE and CLK v VIL MAX, tCK = ∞ (see Notes 7 and 11)
CKE w VIH MIN, tCK = 15 ns (see Notes 7 and 10)
CKE w VIH MIN, CLK v VIL MAX, tCK = ∞ (see Notes 7 and 11)
Page burst, IOH/IOL = 0 mA
All banks activated
activated, nCCD = 1 cycle
(see Notes 12 and 13)
CAS latency = 2
140
140
130
mA
CAS latency = 3
150
150
140
mA
v tRC MIN (see Note 11)
CKE v VIL MAX
CAS latency = 2
90
90
80
mA
CAS latency = 3
95
95
85
mA
0.400
0.400
mA
tRC
ICC6
Self-refresh current
0.400
NOTES: 6. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
7. Only one bank is activated.
8. tRC = MIN
9. Control, DQ, and address inputs change state only twice during tRC.
10. Control, DQ, and address inputs change state only once every 30 ns.
11. Control, DQ, and address inputs do not change (stable).
12. Control, DQ, and address inputs change state only once every cycle.
13. Continuous burst access, nCCD = 1 cycle.
TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
PARAMETER
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
16
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted)
(see Note 6)
TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 14)
MIN
MAX
Ci(S)
Input capacitance, CLK
PARAMETER
2.5
4
pF
Ci(AC)
Input capacitance, A0 – A11, CS, DQM, RAS, CAS, W
2.5
5
pF
Ci(E)
Input capacitance, CKE
5
pF
Co
Output capacitance
6.5
pF
4
UNIT
NOTE 14: VCC = 3.3 ± 0.3 V and bias on pins under test is 0 V.
ac timing requirements† ‡
’626812B-8
MIN
’626812B-8A
MAX
MIN
MAX
’626812B-10
MIN
MAX
UNIT
tCK2
tCK3
Cycle time, CLK, CAS latency = 2
10
15
15
ns
Cycle time, CLK, CAS latency = 3
8
8
10
ns
tCH
tCL
Pulse duration, CLK high
3
3
3
ns
Pulse duration, CLK low
3
3
3
ns
tAC2
Access time, CLK high to data out, CAS latency = 2
(see Note 15)
6
7
7.5
ns
tAC3
Access time, CLK high to data out, CAS latency = 3
(see Note 15)
6
6
7.5
ns
tOH
Hold time, CLK high to data out (with 50-pF load)
3
3
3
ns
tLZ
Delay time, CLK high to DQ in low-impedance state
(see Note 16)
1
1
2
ns
tHZ
Delay time, CLK high to DQ in high-impedance state
(see Note 17)
8
8
tIS
tIH
Setup time, address, control, and data input
2
2
Hold time, address, control, and data input
1
tCESP
tRAS
Power-down/self-refresh exit time (see Note 18)
8
100 000
8
ns
2
ns
1
1
ns
8
10
48
100 000
50
ns
Delay time, ACTV command to DEAC or DCAB command
48
100 000
ns
tRC
Delay time, ACTV, REFR, or SLFR exit to ACTV, MRS, REFR,
or SLFR command
68
68
80
ns
tRCD
Delay time, ACTV command to READ, READ-P, WRT, or
WRT-P command
(see Note 19)
20
20
30
ns
tRP
Delay time, DEAC or DCAB command to ACTV, MRS, REFR,
or SLFR command
20
20
30
ns
tRRD
Delay time, ACTV command in one bank to ACTV command
in the other bank
16
16
20
ns
† See Parameter Measurement Information for load circuits.
‡ All references are made to the rising transition of CLK, unless otherwise noted.
NOTES: 15. tAC is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data-out tAC is referenced
from the rising transition of CLK0 that is CAS latency minus one cycle after the READ command. Access time is measured at output
reference level 1.4 V.
16. tLZ is measured from the rising transition of CLK that is CAS latency minus one cycle after the READ command.
17. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
18. See Figure 18 and Figure 19.
19. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
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ac timing requirements† ‡ (continued)
’626812B-8
MIN
’626812B-8A
MAX
MIN
’626812B-10
MAX
MIN
MAX
UNIT
tRSA
Delay time, MRS command to ACTV, MRS, REFR, or SLFR
command
tAPR
Final data out of READ-P operation to ACTV, MRS, SLFR, or
REFR command
tRP – (CL –1) * tCK
ns
tAPW
Final data in of WRT-P operation to ACTV, MRS, SLFR, or
REFR command
tRP + 1 tCK
ns
tT
tREF
Transition time (see Note 20)
16
1
Refresh interval
16
5
1
64
20
5
1
64
ns
5
ns
64
ms
nWR
Delay time, final data in of WRT operation to DEAC or DCAB
command
1
1
1
cycle
nCCD
Delay time, READ or WRT command to an interrupting
command
1
1
1
cycle
Delay time, CS low or high to input enabled or disabled
0
0
0
0
0
0
cycle
Delay time, CKE high or low to CLK enabled or disabled
1
1
1
1
1
1
cycle
nCWL
Delay time, final data in of WRT operation to READ, READ-P,
WRT, WRT-P
1
nDID
Delay time, ENBL or MASK command to enabled or masked
data in
0
0
0
0
0
0
cycle
nDOD
Delay time, ENBL or MASK command to enabled or masked
data out
2
2
2
2
2
2
cycle
nHZP2
Delay time, DEAC or DCAB command to DQ in
high-impedance state, CAS latency = 2
2
2
2
cycle
nHZP3
Delay time, DEAC or DCAB command to DQ in
high-impedance state, CAS latency = 3
3
3
3
cycle
0
cycle
nCDD
nCLE
nWCD Delay time, WRT command to first data in
0
† See Parameter Measurement Information for load circuits.
‡ All references are made to the rising transition of CLK, unless otherwise noted.
NOTE 20: Transition time, tT, is measured between VIH and VIL.
18
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0
1
0
0
cycle
TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
general information for ac timing measurements
The ac timing measurements are based on signal rise and fall times equal to 1 ns (tT = 1 ns) and a midpoint
reference level of 1.5 V (INPUT = 2.8 V, 0 V) for LVTTL. For signal rise and fall times greater than 1 ns, the
reference level should be changed to VIH MIN and VIL MAX instead of the midpoint level. All specifications
referring to READ commands are valid for READ-P commands unless otherwise noted. All specifications
referring to WRT commands are also valid for WRT-P commands unless otherwise noted. All specifications
referring to consecutive commands are specified as consecutive commands for the same bank unless
otherwise noted.
Z = 50 Ω
Output
Under
Test
CL = 50 pF
Circuit for ac Measurements
Figure 8. LVTTL-Load Circuits
tCK
tCH
CLK
tT
tCL
tIS
tT
tIH
DQ, A0 – A11, CS, RAS,
CAS, W, DQM, CKE
tT
tIH
tIS, tCESP
DQ, A0 – A11, CS, RAS,
CAS, W, DQM, CKE
tT
Figure 9. Input-Attribute Parameters
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TMS626812B
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
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PARAMETER MEASUREMENT INFORMATION
CAS Latency
CLK
ACTV
Command
tAC
READ
Command
tHZ
tLZ
tOH
DQ
Figure 10. Output Parameters
READ, WRT
nCCD
READ, READ-P, WRT, WRT-P, DEAC, DCAB
DESL
nCDD
Command Disable
ACTV
tRAS
DEAC, DCAB
ACTV, REFR, SELF-REFRESH EXIT
ACTV
DEAC, DCAB
tRC
tRCD
tRP
ACTV, MRS, REFR, SLFR
READ, READ-P, WRT, WRT-P
ACTV, MRS, REFR, SLFR
ACTV
tRRD
ACTV (different bank)
MRS
tRSA
ACTV, MRS, REFR, SLFR
Figure 11. Command-to-Command Parameters
20
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1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
nHZP3
CLK
DEAC or
DCAB
Command
READ
Command
DQ
Q
tHZ
Q
Q
NOTE A: For this example, assume CAS latency = 3 and burst length = 4.
Figure 12. Read Followed by Deactivate
tAPR
CLK
READ-P
Command
ACTV, MRS,
REFR, or SLFR
Command
Final Data Out
DQ
Q
NOTE A: For this example, assume CAS latency = 3 and burst length = 1.
Figure 13. Read With Auto-Deactivate
nCWL
tWR
CLK
DQ
WRT
Command
WRT
Command
D
D
DEAC or DCAB
Command
NOTE A: For this example, assume burst length = 1.
Figure 14. Write Followed By Deactivate
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PARAMETER MEASUREMENT INFORMATION
nCWL
tAPW
CLK
WRT
Command
WRT-P
Command
D
D
ACTV, MRS,
REFR, or SLFR
Command
tRP
DQ
Figure 15. Write With Auto-Deactivate
nDOD
tWR
nDOD
CLK
DQ
Q
ENBL
Command
MASK
Command
MASK
Command
MASK
Command
D
Ignored
Ignored
ENBL
Command
MASK
Command
MASK
Command
DQM
NOTE A: For this example, assume CAS latency = 3 and burst length = 4.
Figure 16. DQ Masking
22
DEAC or
DCAB
Command
WRT
Command
READ
Command
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Ignored
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1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
nCLE
nCLE
CLK
DQ
DQ
DQ
DQ
DQ
tIS
tIS
tIH
tIH
CKE
Figure 17. CLK-Suspend Operation
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TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
CLK
Last Data-In
WRT
(WRT-P)
Operation
Last
Data-Out
READ
(READ-P)
Operation
Enter
Power-Down
Mode
Exit
Power-Down
Mode If tCESP
Is Satisfied
(New
Command)
CLK Is
Don’t Care,
But Must Be
Stable
Before CKE
High
CKE
tCESP
tIH
tIS
CLK
Last Data-In
WRT
(WRT-P)
Operation
Last
Data-Out
READ
(READ-P)
Operation
Enter
Power-Down
Mode
CLK Is
Don’t Care,
But Must Be
Stable
Before CKE
High
DESL or
NOOP
Command
Only If tCESP
Is Not
Satisfied
Exit Power-Down
Mode (New
Command)
CKE
tIH
tCESP
tIS
Figure 18. Power-Down Operation
24
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PARAMETER MEASUREMENT INFORMATION
CLK
SLFR
Command
Both Banks
Deactivated
CLK Is
Don’t Care,
But Must
Be Stable
Before
CKE High
Exit SLFR
If tCESP is
Satisfied
ACTV,
MRS, or
REFR
Command
DESL or
NOOP
Command
Only Until tRC
Is Satisfied
CKE
tRC
tIH
tIS
tCESP
CLK
SLFR
Command
Both Banks
Deactivated
CLK Is
Don’t Care,
But Must
Be Stable
Before
CKE High
NOOP or
DESL if
tCESP Not
Yet
Satisfied
Exit SLFR
ACTV, MRS, or
REFR Command
DESL or
NOOP
Command
Only Until tRC
Is Satisfied
CKE
tRC
tIH
tIS
tCESP
Figure 19. Self-Refresh Operation
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25
DEAC T
CLK
DQ
a
b
c
d
DQM
RAS
PARAMETER MEASUREMENT INFORMATION
CAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
A10
R0
A11
A0 – A9
R0
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B / T )
ADDR
a
b
c
d
Q
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTE A: This example illustrates minimum tRCD for the ’626812B-10 at 100 MHz.
Figure 20. Read Burst (CAS latency = 3, burst length = 4)
TMS626812B
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READ T
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
26
ACTV T
ACTV T
WRT T
DEAC T
CLK
a
DQ
b
c
d
e
f
g
h
DQM
RAS
R0
A10
A11
R0
A0 – A9
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
e
f
g
h
D
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
C0 + 4
C0 + 5
C0 + 6
C0 + 7
BURST CYCLE†
† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 6).
NOTE A: This example illustrates minimum tRCD for the ’626812B-10 at 100 MHz.
Figure 21. Write Burst (burst length = 8)
27
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
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TMS626812B
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PARAMETER MEASUREMENT INFORMATION
CAS
WRT B
READ B
DEAC B
CLK
DQ
a
c
b
d
DQM
RAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
A10
R0
A11
A0 – A9
R0
C1
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
D
Q
B
B
R0
R0
C0
C0 + 1
BURST CYCLE†
c
d
C1
C1 + 1
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).
NOTE A: This example illustrates minimum tRCD and nCWL for the ’626812B-10 at 100 MHz.
Figure 22. Write-Read Burst (CAS latency = 3, burst length = 2)
PARAMETER MEASUREMENT INFORMATION
CAS
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ACTV B
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
28
3
ACTV T
READ T
WRT-P T
CLK
DQ
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
DQM
RAS
CAS
W
R0
A11
R0
C0
C1
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
e
f
g
h
Q
D
T
T
R0
R0
C0
C0 + 1
C0 + 2
C0 + 3
C0 + 4
C0 + 5
C0 + 6
C0 + 7
BURST CYCLE†
i
j
k
C1
C1 + 1 C1 + 2
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6).
NOTE A: This example illustrates minimum tRCD for the ’626812B-10 at 100 MHz.
l
m
n
o
p
C1 + 3
C1 + 4
C1 + 5
C1 + 6
C1 + 7
Figure 23. Read-Write Burst With Automatic Deactivate (CAS latency = 3, burst length = 8)
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
29
TMS626812B
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A0 – A9
PARAMETER MEASUREMENT INFORMATION
A10
ACTV T
ACTV B
READ- P B
CLK
DQ
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
DQM
RAS
CAS
W
A10
R1
R0
R2
R3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
A0 – A9
R0
R1
C0
C1
R2
C2
R3
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
Q
Q
Q
B
T
B
R0
R1
R2
C0
BURST CYCLE†
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
.
.
C2 + 1 C2 + 2 .
.
C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7
C1
C1 + 1 C1 + 2 C1 + 3 C1 + 4 C1 + 5 C1 + 6 C1 + 7
C2
† Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 6).
NOTE A: This example illustrates minimum tRCD for the ’626812B-10 at 100 MHz.
Figure 24. Two-Bank Row-Interleaving Read Bursts With Automatic Deactivate (CAS latency = 3, burst length = 8)
PARAMETER MEASUREMENT INFORMATION
A11
TMS626812B
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READ- P T
READ- P B
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
30
ACTV T
ACTV B
ACTV T
ACTV B
READ T
READ T
READ B
READ B
READ B
CLK
DQ
a
b
c
d
e
f
DQM
RAS
A10
R0
R1
R0
R1
A11
A0 – A9
C0
C1
C2
C3
C4
CS
CKE
BANK
ROW
(D/Q)
(B / T )
ADDR
a
b
Q
Q
Q
.
B
T
B
...
R0
R1
R0
...
C0
C0 + 1
BURST CYCLE†
c
d
C1
C1 + 1
e
f
C2
C2 + 1
...
...
...
...
† Column-address sequence depends on programmed burst type and starting column addresses C0, C1 and C2 (see Table 4).
Figure 25. Two-Bank Column-Interleaving Read Bursts (CAS latency = 3, burst length = 2)
31
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
BURST
TYPE
TMS626812B
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
PARAMETER MEASUREMENT INFORMATION
CAS
DEAC T
DEAC B
READ B
CLK
DQ
a
b
c
d
e
f
g
h
DQM
RAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
A10
R0
R1
A11
C0
R0
A0 – A9
R1
C1
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B / T )
ADDR
a
b
c
d
Q
D
B
T
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column addresses C0 and C1 (see Table 5).
NOTE A: This example illustrates a minimum tRCD for the ’626812B-10 at 100 MHz.
Figure 26. Read-Burst Bank B, Write-Burst Bank T (CAS latency = 3, burst length = 4)
PARAMETER MEASUREMENT INFORMATION
CAS
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ACTV B
WRT T
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
32
ACTV T
ACTV T
WRT- P T
ACTV B
READ- P B
CLK
DQ
a
b
c
d
e
f
g
DQM
RAS
A10
R0
R1
R0
R1
A11
A0 – A9
C0
C1
CS
CKE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
D
Q
T
B
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE †
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum nCWL for the ’626812B-10 at 100 MHz.
Figure 27. Write-Burst Bank T, Read-Burst Bank B With Automatic Deactivate (CAS latency = 3, burst length = 4)
33
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
BURST
TYPE
TMS626812B
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
PARAMETER MEASUREMENT INFORMATION
CAS
DCAB
CLK
a
b
c
e
d
f
g
h
DQ
DQM
RAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
R0
A10
A11
C0
R0
A0 – A9
C1
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
D
T
T
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum tRCD for the ’626812B-10 at 100 MHz.
Figure 28. Data Mask (CAS latency = 3, burst length = 4)
PARAMETER MEASUREMENT INFORMATION
CAS
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WRT T
READ T
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
34
ACTV T
REFR
ACTV T
READ T
DEAC T
REFR
CLK
DQ
a
b
c
d
DQM
RAS
CAS
R0
A10
R0
A0 – A9
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
Figure 29. Refresh Cycles (CAS latency = 3, burst length = 4)
35
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTE A: This example illustrates minimuim tRC and tRCD for the ’626812B-10 at 100 MHz.
TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
A11
PARAMETER MEASUREMENT INFORMATION
W
WRT-P B
CLK
DQ
a
b
c
d
DQM
RAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
R0
A10
See Note B
A11
See Note B
A0 – A9
R0
C0
See Note B
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B / T )
ADDR
a
b
c
d
D
B
R0
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTES: A. This example illustrates minimum tRP, tRSA, and tRCD for the ’626812B-10 at 100 MHz.
B. See Figure 1
Figure 30. Set Mode Register (deactivate all, set mode register, write burst with automatic deactivate)
(burst length = 4)
PARAMETER MEASUREMENT INFORMATION
CAS
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ACTV B
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
36
MRS
DCAB
ACTV T
READ T
WRT-P T
HOLD
HOLD
PDE
CLK
a
DQ0
b
d
c
e
f
g
h
DQM
RAS
CAS
A11
R0
A0 – A9
C1
C0
CS
CKE
BURSTBANK
TYPE
BURST CYCLE†
ROW
(B/ T )
ADDR
a
b
c
d
Q
D
T
T
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
Figure 31. CLK Suspend (HOLD) During Read Burst and Write Burst (CAS latency = 3, burst length = 4)
37
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
(D/Q)
TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
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R0
A10
PARAMETER MEASUREMENT INFORMATION
W
TMS626812B
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SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
device symbolization
TI
-SS
Speed Code (-8, -8A, -10)
TMS626812B DGE
Package Code
W
B
Y
M
LLLL P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
38
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SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
MECHANICAL DATA
DGE (R-PDSO-G44)
PLASTIC SMALL-OUTLINE PACKAGE
0.018 (0,45)
0.012 (0,30)
0.031 (0,80)
44
0.006 (0,16) M
23
0.471 (11,96)
0.455 (11,56)
0.404 (10,26)
0.396 (10,06)
0.006 (0,15) NOM
Gage Plane
1
0.010 (0,25)
22
0°– 5°
0.729 (18,51)
0.721 (18,31)
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.047 (1,20) MAX
0.004 (0,10)
0.002 (0,05) MIN
4040070-3 / C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
39
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