TPS2115A-Q1 www.ti.com........................................................................................................................................................................................... SBVS124 – NOVEMBER 2008 AUTO-SWITCHING POWER MULTIPLEXER FEATURES APPLICATIONS • • • • • • • • • 1 • • • • • • • • • • Qualified for Automotive Applications Two-Input One-Output Power Multiplexer With Low rDS(on) Switch...84 mΩ (Typ) Reverse and Cross-Conduction Blocking Wide Operating Voltage Range...2.8 V to 5.5 V Low Standby Current...0.5 µA (Typ) Low Operating Current...55 µA (Typ) Adjustable Current Limit Controlled Output Voltage Transition Times Limit Inrush Current and Minimize Output Voltage Hold-Up Capacitance CMOS- and TTL-Compatible Control Inputs Manual and Auto-Switching Operating Modes Thermal Shutdown Available in TSSOP-8 (PW) Package PCs PDAs Digital Cameras Modems Cell Phones Digital Radios MP3 Players PW PACKAGE (TOP VIEW) STAT 1 8 IN1 D0 2 7 OUT D1 3 6 IN2 ILIM 4 5 GND DESCRIPTION/ORDERING INFORMATION The TPS2115A power multiplexer enables seamless transition between two power supplies, such as a battery and a wall adapter, each operating at 2.8 V to 5.5 V and delivering up to 1 A. The TPS2115A includes extensive protection circuitry including user-programmable current limiting, thermal protection, inrush current control, seamless supply transition, cross-conduction blocking, and reverse-conduction blocking. These features greatly simplify designing power multiplexer applications. Switch Status IN1 2.8 V to 5.5 V TPS2115A 1 NC 2 3 4 STAT IN1 D0 OUT D1 IN2 ILIM R1 0.1 µF GND 8 7 6 CL 5 RL RILIM IN2 2.8 V to 5.5 V C2 0.1 µF Figure 1. Typical Application 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TPS2115A-Q1 SBVS124 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 85°C (1) (2) TSSOP – PW ORDERABLE PART NUMBER Reel of 2000 TPS2115AIPWRQ1 TOP-SIDE MARKING 2115AQ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. TRUTH TABLE (1) (2) VI(IN2) > VI(IN1) (1) STAT OUT (2) 0 X Hi-Z IN2 1 No 0 IN1 0 1 Yes Hi-Z IN2 1 0 X 0 IN1 1 1 X 0 Hi-Z D0 D1 0 0 X = don’t care The undervoltage lockout circuit causes the output OUT to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or if neither of the supplies exceeds the internal VDD UVLO. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION D0 2 I D1 3 I TTL- and CMOS-compatible input pins. Each pin has a 1-µA pullup. The Truth Table shows the functionality of D0 and D1. GND 5 I Ground IN1 8 I Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. IN2 6 I Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. ILIM 4 I A resistor RILIM from ILIM to GND sets the current limit IL to 500/RILIM. OUT 7 O Power switch output STAT 1 O Open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is Hi-Z (i.e., EN is equal to logic 0). 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 TPS2115A-Q1 www.ti.com........................................................................................................................................................................................... SBVS124 – NOVEMBER 2008 FUNCTIONAL BLOCK DIAGRAM 1 µA 1 µA IN1 IN2 Internal V DD Vf = 0 V Vf = 0 V IO(OUT) Q1 8 Q2 6 7 Charge Pump VDD ULVO IN2 OUT k* IO(OUT) _ TPS2114A: k = 0.2% TPS2115A: k = 0.1% + 0.5 V 4 ILIM ULVO IN1 ULVO Cross-Conduction Detector + _ 0.6 V + EN2 + _ EN1 Q1 is ON Q2 is ON UVLO (VDD) VO(OUT) > V I(INx) UVLO (IN2) UVLO (IN1) D0 D1 GND 2 3 EN1 D0 D1 + _ 100 mV + Control Logic Thermal Sense IN2 + _ 5 IN1 1 STAT Q2 is ON Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 3 TPS2115A-Q1 SBVS124 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range unless otherwise noted VI Input voltage range IN1, IN2, D0, D1, ILIM –0.3 V to 6 V VO Output voltage range OUT, STAT –0.3 V to 6 V IO(sink) Output sink current STAT IO Continuous output current PD Continuous total power dissipation TA Operating free-air temperature range –40°C to 85°C TJ Operating virtual-junction temperature range –40°C to 125°C Tstg Storage temperature range –65°C to 150°C Tlead Lead temperature soldering (1) (2) 5 mA 1.5 mA See Dissipation Ratings 1,6 mm (1/16 inch) from case for 10 seconds 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. ELECTROSTATIC DISCHARGE (ESD) PROTECTION MAX ESD Human-Body Model (HBM) Electrostatic discharge protection 2000 Charged-Device Model (CDM) 500 UNIT V DISSIPATION RATINGS PACKAGE DERATING FACTOR ABOVE TA = 25°C TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING TSSOP (PW) 3.9 mW/°C 387 mW 213 mW 155 mW RECOMMENDED OPERATING CONDITIONS IN1 VI Input voltage IN2 MIN MAX VI(IN2) ≥ 2.8 V 1.5 5.5 VI(IN2) < 2.8 V 2.8 5.5 VI(IN1) ≥ 2.8 V 1.5 5.5 VI(IN1) < 2.8 V 2.8 5.5 5.5 D0, D1 0 VIH High-level input voltage D0, D1 2 VIL Low-level input voltage D0, D1 IO Current limit adjustment range OUT TA Operating free-air temperature TJ Operating virtual-junction temperature range 4 V V 0.7 V 1.25 A –40 85 °C –40 125 °C 0.63 Submit Documentation Feedback UNIT Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 TPS2115A-Q1 www.ti.com........................................................................................................................................................................................... SBVS124 – NOVEMBER 2008 ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted) PARAMETER Power Switch TEST CONDITIONS TA = 25°C, IL = 500 mA rDS(on) MIN TYP MAX VI(IN1) = VI(IN2) = 5.0 V 84 110 VI(IN1) = VI(IN2) = 3.3 V 84 110 VI(IN1) = VI(IN2) = 2.8 V 84 110 UNIT (1) Drain-source on-state resistance (INx to OUT) TA = 85°C, IL = 500 mA VI(IN1) = VI(IN2) = 5.0 V 150 VI(IN1) = VI(IN2) = 3.3 V 150 VI(IN1) = VI(IN2) = 2.8 V 150 mΩ Logic Inputs (D0 and D1) II Input current at D0 or D1 D0 or D1 = high, sink current 1 D0 or D1 = low, source current 0.5 1.4 5 D1 = high, D0 = low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A 55 90 D1 = high, D0 = low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A 1 12 µA Supply and Leakage Currents Supply current from IN1 (operating) Supply current from IN2 (operating) D0 = D1 = low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A 75 D0 = D1 = low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A 1 D1 = high, D0 = low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A 1 D1 = high, D0 = low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A 75 D0 = D1 = low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A D0 = D1 = low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A Quiescent current from IN1 (standby) D0 = D1 = high (inactive), IO(OUT) = 0 A Quiescent current from IN2 (standby) D0 = D1 = high (inactive), IO(OUT) = 0 A Forward leakage current from IN1 (measured from OUT to GND) VI(IN1) = 5.5 V, VI(IN2) = 3.3 V 1 12 55 90 0.5 2 VI(IN1) = 3.3 V, VI(IN2) = 5.5 V 1 VI(IN1) = 5.5 V, VI(IN2) = 3.3 V 1 VI(IN1) = 3.3 V, VI(IN2) = 5.5 V µA µA µA µA 0.5 2 D0 = D1 = high (inactive), VI(IN1) = 5.5 V, IN2 open, VO(OUT) = 0 V (shorted), TA = 25°C 0.1 5 µA Forward leakage current from IN2 (measured from OUT to GND) D0 = D1= high (inactive), VI(IN2) = 5.5 V, IN1 open, VO(OUT) = 0 V (shorted), TA = 25°C 0.1 5 µA Reverse leakage current to INx (measured from INx to GND) D0 = D1 = high (inactive), VI(INx) = 0 V, VO(OUT) = 5.5 V, TA = 25°C 0.3 5 µA Current Limit Circuit Current limit accuracy RILIM = 400 Ω 0.95 1.25 1.56 RILIM = 700 Ω 0.47 0.71 0.99 td Current limit settling time Time for short-circuit output current to settle within 10% of its steady state value II Input current at ILIM VI(ILIM) = 0 V, IO(OUT) = 0 A –15 1 Falling edge 1.15 A ms 0 µA UVLO IN1 and IN2 UVLO Rising edge IN1 and IN2 UVLO hysteresis Internal VDD UVLO (the higher of IN1 and IN2) Falling edge UVLO deglitch for IN1, IN2 1.30 1.35 30 57 65 2.4 2.53 Rising edge Internal VDD UVLO hysteresis 1.25 30 Falling edge 2.58 2.8 50 75 V mV V mV µs 110 Reverse Conduction Blocking Minimum input-to-output ΔVIO(blk) voltage difference to block switching (1) D0 = D1 = high, VI(INx) = 3.3 V. Connect OUT to a 5-V supply through a series 1-kΩ resistor. Set D0 = low. Slowly decrease the supply voltage until OUT connects to IN1. 80 100 120 mV The TPS2115A can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this specific case, the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 5 TPS2115A-Q1 SBVS124 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Thermal Shutdown Thermal shutdown threshold TPS2115A is in current limit. 135 Recovery from thermal shutdown TPS2115A is in current limit. 125 Hysteresis °C °C 10 °C IN2-IN1 Comparators Hysteresis of IN2-IN1 comparator 0.1 Deglitch of IN2-IN1 comparator (both ↑↓) 10 20 0.2 V 50 µs STAT Output Ileak Leakage current VO(STAT) = 5.5 V 0.01 1 µA Vsat Saturation voltage II(STAT) = 2 mA, IN1 switch is on 0.13 0.4 V td Deglitch time (falling edge only) µs 150 SWITCHING CHARACTERISTICS over operating free-air temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Switch tr Output rise time from an enable VI(IN1) = VI(IN2) = 5 V TA = 25°C, CL = 1 µF, IL = 500 mA, See Figure 2(a) 1 1.8 3 ms tf Output fall time from a disable VI(IN1) = VI(IN2) = 5 V TA = 25°C, CL = 1 µF, IL = 500 mA, See Figure 2(a) 0.5 1 2 ms 40 60 tt Transition time 40 60 IN1 to IN2 transition, VI(IN1) = 3.3 V, VI(IN2) = 5 V IN2 to IN1 transition, VI(IN1) = 5 V, VI(IN2) = 3.3 V TA = 85°C, CL = 10 µF, IL = 500 mA [Measure transition time as 10%-90% rise time or from 3.4 V to 4.8 V on VO(OUT)], See Figure 2(b) µs tPLH1 Turn-on propagation delay from enable VI(IN1) = VI(IN2) = 5 V, Measured from enable to 10% of VO(OUT) TA = 25°C, CL = 10 µF, IL = 500 mA, See Figure 2(a) 1 ms tPHL1 Turn-off propagation delay from a disable VI(IN1) = VI(IN2) = 5 V, Measured from disable to 90% of VO(OUT) TA = 25°C, CL = 10 µF, IL = 500 mA, See Figure 2(a) 5 ms tPLH2 Switch-over rising propagation delay Logic 1 to Logic 0 transition on D1, VI(IN1) = 1.5 V, VI(IN2) = 5 V, VI(D0) = 0 V, Measured from D1 to 10% of VO(OUT) TA = 25°C, CL = 10 µF, IL = 500 mA, See Figure 2(c) 40 100 µs tPHL2 Switch-over falling propagation delay Logic 0 to Logic 1 transition on D1, VI(IN1) = 1.5 V, VI(IN2) = 5 V, VI(D0) = 0 V, Measured from D1 to 90% of VO(OUT) TA = 25°C, CL = 10 µF, IL = 500 mA, See Figure 2(c) 5 10 ms 6 Submit Documentation Feedback 2 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 TPS2115A-Q1 www.ti.com........................................................................................................................................................................................... SBVS124 – NOVEMBER 2008 PARAMETER MEASUREMENT INFORMATION 90% 90% VO(OUT) 10% 10% 0V tr tf tPLH1 tPHL1 DO-D1 Switch Off Switch Enabled Switch Off (a) 5V 4.8 V VO(OUT) 3.4 V 3.3 V tt DO-D1 Switch #2 Enabled Switch #1 Enabled (b) 5V VO(OUT) 4.65 V 1.85 V 1.5 V tPLH2 tPHL2 DO-D1 Switch #1 Enabled Switch #2 Enabled Switch #1 Enabled (c) Figure 2. Propagation Delays and Transition Timing Waveforms Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 7 TPS2115A-Q1 SBVS124 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS OUTPUT SWITCHOVER RESPONSE 5V TPS2115A VI(D0) 2 V/div NC STAT 2 f = 28 Hz 78% Duty Cycle VI(D1) 2 V/div VO(OUT) 2 V/div 1 D0 3 D1 4 ILIM 0.1 µF 8 IN1 7 OUT 6 IN2 5 GND 50 W 1 µF 400 W 3.3 V 0.1 µF Output Switchover Response Test Circuit t - Time - 1 ms/div Figure 3. OUTPUT TURN-ON RESPONSE VI(D0) 2 V/div 5V TPS2115A VI(D1) 2 V/div f = 28 Hz 78% Duty Cycle NC 1 2 3 4 STAT IN1 7 D0 OUT D1 IN2 ILIM 0.1 µF 8 GND 6 5 1 µF 50 W 400 W 3.3 V VO(OUT) 2 V/div 0.1 µF Output Turn-On Response Test Circuit t - Time - 2 ms/div Figure 4. 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 TPS2115A-Q1 www.ti.com........................................................................................................................................................................................... SBVS124 – NOVEMBER 2008 TYPICAL CHARACTERISTICS (continued) OUTPUT SWITCHOVER VOLTAGE DROOP VI(DO) 5V 2 V/div TPS2115A NC VI(D1) f = 580 Hz 90% Duty Cycle CL = 1 µF 2 V/div 1 2 3 4 STAT D0 D1 ILIM 8 IN1 7 OUT 6 IN2 5 GND 0.1 µF CL 50 W 400 W VO(OUT) 2 V/div 0.1 µF CL = 0 µF Output Switchover Voltage Droop Test Circuit t - Time - 40 µs/div Figure 5. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 9 TPS2115A-Q1 SBVS124 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT SWITCHOVER VOLTAGE DROOP vs LOAD CAPACITANCE 5 VI = 5 V DVO(OUT) - Output Voltage Droop - V 4.5 4 3.5 3 RL = 10 W 2.5 2 1.5 1 RL = 50 W 0.5 0 0.1 VI 1 10 CL - Load Capacitance - µF 100 TPS2115A NC 1 2 f = 28 Hz 50% Duty Cycle 3 4 400 W STAT IN1 D0 OUT D1 IN2 ILIM GND 8 0.1 µF 7 6 5 50 W 0.1 µF 0.1 µF 1 µF 10 µF 47 µF 10 W 100 µF Output Switchover V oltage Droop T est Circuit Figure 6. 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 TPS2115A-Q1 www.ti.com........................................................................................................................................................................................... SBVS124 – NOVEMBER 2008 TYPICAL CHARACTERISTICS (continued) AUTO SWITCHOVER VOLTAGE DROOP VI(IN1) 2V/Div 5V TPS2115A 1 kW 1 2 f = 220 Hz 20% Duty Cycle STAT D0 3 4 D1 ILIM 400 W VO(OUT) 2V/Div IN1 0.1 µF 8 7 OUT IN2 GND 6 5 VOUT 3.3 V 10 µF 50 W 0.1 µF 75% less output voltage droop compared to TPS2115 Auto Switchover Voltage Droop Test Circuit t - Time - 250 µs/div Figure 7. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 11 TPS2115A-Q1 SBVS124 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) INRUSH CURRENT vs LOAD CAPACITANCE 300 - Inrush Current - mA 250 200 VI = 5 V 150 VI = 3.3 V I I 100 50 0 0 VI f = 28 Hz 90% Duty Cycle 20 40 60 80 CL - Load Capacitance - µF 100 TPS2115A NC 1 2 NC 3 4 400 W STAT IN1 D0 OUT D1 IN2 ILIM GND 8 0.1 µF To Oscilloscope 7 6 5 50 W 0.1 µF 0.1 µF 1 µF 10 µF 47 µF 100 µF Output Capacitor Inrush Current Test Circuit Figure 8. 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 TPS2115A-Q1 www.ti.com........................................................................................................................................................................................... SBVS124 – NOVEMBER 2008 TYPICAL CHARACTERISTICS (continued) SWITCH ON-RESISTANCE vs JUNCTION TEMPERATURE SWITCH ON-RESISTANCE vs SUPPLY VOLTAGE 120 rDS(on) - Switc h On-Resistance - m W rDS(on) - Switc h On-Resistance - m W 180 160 140 120 100 80 60 -50 115 110 105 100 95 90 85 80 0 50 100 TJ - J unction Temperature - °C 2 150 3 4 5 VI(INx) - Suppl y Voltage - V Figure 9. Figure 10. IN1 SUPPLY CURRENT vs SUPPLY VOLTAGE IN1 SUPPLY CURRENT vs SUPPLY VOLTAGE 0.96 60 Device Disabled VI(IN2) = 0 V IO(OUT) = 0 A IN1 Switch is ON VI(IN2) = 0 V IO(OUT) = 0 A 58 I(IN1) - IN1 Suppl y Current - µA 0.94 0.92 0.90 0.88 0.86 I I I(IN1) - IN1 Suppl y Current - µA 6 56 54 52 50 48 46 44 0.84 42 40 0.82 2 3 4 5 6 2 VI(IN1) - IN1 Supply Voltage - V Figure 11. 3 4 5 VI(IN1) - Suppl y Voltage - V 6 Figure 12. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 13 TPS2115A-Q1 SBVS124 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs JUNCTION TEMPERATURE SUPPLY CURRENT vs JUNCTION TEMPERATURE 1.2 70 I I(INx) - Supply Current - µA I I(INx) - Supply Current - µA 1 80 Device Disabled VI(IN1) = 5.5 V VI(IN2) = 3.3 V IO(OUT) = 0 A II(IN1) = 5.5 V 0.8 0.6 0.4 60 IN1 Switch is ON VI(IN1) = 5.5 V VI(IN2) = 3.3 V IO(OUT) = 0 A II(IN1) 50 40 30 20 0.2 10 II(IN2) = 3.3 V 0 -50 0 50 100 TJ - J unction Temperature - °C 150 0 -50 Figure 13. 14 II(IN2) 0 50 100 TJ - J unction Temperature - °C 150 Figure 14. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 TPS2115A-Q1 www.ti.com........................................................................................................................................................................................... SBVS124 – NOVEMBER 2008 APPLICATION INFORMATION Some applications have two energy sources, one of which should be used in preference to another. Figure 15 shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified value. Once the voltage on IN1 falls below this value, the TPS2115A will select the higher of the two supplies. This usually means that the TPS2115A will swap to IN2. Switch Status IN1 2.8 V to 5.5 V TPS2115A 1 2 NC 3 4 IN1 STAT D0 OUT D1 IN2 ILIM R1 0.1 µF GND 8 7 6 RL CL 5 RILIM IN2 2.8 V to 5.5 V C2 0.1 µF Figure 15. Auto-Selecting for a Dual Power Supply Application In Figure 16, the multiplexer selects between two power supplies based upon the D1 logic signal. OUT connects to IN1 if D1 is logic 1; otherwise, OUT connects to IN2. The logic thresholds for the D1 terminal are compatible with both TTL and CMOS logic. Switch Status IN1 2.8 V to 5.5 V TPS2115A 1 2 3 4 STAT IN1 D0 OUT D1 IN2 ILIM R1 0.1 µF GND 8 7 6 CL 5 RL RILIM IN2 2.8 V to 5.5 V 0.1 µF Figure 16. Manually Switching Power Sources Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 15 TPS2115A-Q1 SBVS124 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com DETAILED DESCRIPTION Auto-Switching Mode D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to the higher of IN1 and IN2. Manual Switching Mode D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic 1, otherwise OUT connects to IN2. N-Channel MOSFETs Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so output-to-input current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET switch if the output voltage is greater than the input voltage. Cross-Conduction Blocking The switching circuitry ensures that both power switches will never conduct at the same time. A comparator monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source voltage of the other FET is below the turn-on threshold voltage. Reverse-Conduction Blocking When the TPS2115A switches from a higher-voltage supply to a lower-voltage supply, current can potentially flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the TPS2115A will not connect a supply to the output until the output voltage has fallen to within 100 mV of the supply voltage. Once a supply has been connected to the output, it will remain connected regardless of output voltage. Charge Pump The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages. A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET. Current Limiting A resistor RILIM from ILIM to GND sets the current limit to 500/RILIM. Setting resistor RILIM equal to zero is not recommended as that disables current limiting. Output Voltage Slew-Rate Control The TPS2115A slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state (see Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can glitch the voltage bus and cause a system to hang up or reset. It can also cause reliability issues such as pitting the connector power contacts when hot-plugging a load such as a PCI card. The TPS2115A slews the output voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output voltage droop and reduces the output voltage hold-up capacitance requirement. 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS2115A-Q1 PACKAGE OPTION ADDENDUM www.ti.com 13-Jan-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPS2115AIPWRQ1 ACTIVE TSSOP PW Pins Package Eco Plan (2) Qty 8 2000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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