ATMEL U2794B-MFS

Features
• Supply Voltage 5 V
• Very Low Power Consumption 125 mW
• Very Good Image Rejection By Means of Phase Control Loop for Precise 90° Phase
•
•
•
•
•
•
Shifting
Duty-cycle Regeneration for Single-ended LO Input Signal
Low LO Input Level -10 dBm
LO Frequency from 70 MHz to 1 GHz
Power-down Mode
25 dB Gain Control
Very Low I/Q Output DC Offset Voltage Typically < 5 mV
Benefits
• Low Current Consumption
• Easy to Implement
• Perfect Performance for Large Variety of Wireless Applications
Electrostatic sensitive device.
Observe precautions for handling.
1000-MHz
Quadrature
Demodulator
U2794B
Description
The silicon monolithic integrated circuit U2794B is a quadrature demodulator manufactured using Atmel’s advanced UHF technology. This demodulator features a
frequency range from 70 MHz to 1000 MHz, low current consumption, selectable gain,
power-down mode and adjustment-free handling. The IC is suitable for direct conversion and image rejection applications in digital radio systems up to 1 GHz such as
cellular radios, cordless telephones, cable TV and satellite TV systems.
Rev. 4653C–CELL–06/03
1
Figure 1. Block Diagram
VS
IIX
PU
5,6
II
4
14
3
IX
Power
down
1
2
RFin
90°Control
loop
7
0°
90°
Frequency
doubler
8
19
20
10
16,18
GC
GND
I
Duty cycle 15 LO
regenerator 17
13 PC
12
11
OUTPUT
PCX
Q
OUTPUT
QX
9
QQ
QQX
Pin Configuration
Figure 2. Pinning SSO20
IX
1
20 QX
I
2
19
Q
II
3
18
GND
IIX
4
17
LOin
VS
5
16
GND
VS
6
15
LOXin
RFin
7
14 PU
RFXin
8
13
QQ
9
12 PCX
10
11 GC
QQX
2
PC
U2794B
4653C–CELL–06/03
U2794B
Pin Description
Pin
Symbol
Function
1
IX
IX output
2
I
I output
3
II
II lowpass filter I
4
IIX
IIX lowpass filter I
5
VS
Supply voltage
6
VS
Supply voltage
7
RFin
8
RFXin
9
QQ
10
QQX
RF input
RFX input
QQ lowpass filter Q
QQX lowpass filter Q
11
GC
GC gain control
12
PCX
PCX phase control
13
PC
14
PU
PC phase control
PU power up
15
LOXin
LOX input
16
GND
Ground
17
LOin
LO input
18
GND
Ground
19
Q
Q output
20
QX
QX output
3
4653C–CELL–06/03
Absolute Maximum Ratings
Parameters
Symbol
Value
Unit
Supply voltage
VS
6
V
Input voltage
Vi
0 to VS
V
Tj
+125
°C
Tstg
-40 to +125
°C
Symbol
Value
Unit
RthJA
140
K/W
Symbol
Value
Unit
VS
4.75 to 5.25
V
Tamb
-40 to +85
°C
Junction temperature
Storage-temperature range
Thermal Resistance
Parameters
Junction ambient SSO20
Operating Range
Parameters
Supply-voltage range
Ambient-temperature range
Electrical Characteristics
Test conditions (unless otherwise specified); VS = 5 V, Tamb = 25°C, referred to test circuit
System impedance ZO = 50 W, fiLO = 950 MHz, PiLO = -10 dBm
No.
Parameters
1.1
Test Conditions
Pin
Symbol
Min.
Supply-voltage range
5, 6
VS
4.75
1.2
Supply current
5, 6
IS
22
2
Power-down Mode
2.1
“OFF” mode supply
current
14, 5
6
ISPU
14
VPON
VPU £ 0.5 V
VPU = 1.0 V
Typ.
30
£1
20
Max.
Unit
Type*
5.25
V
A
35
mA
A
µA
µA
B
D
V
D
(1)
3
Switch Voltage
3.1
“Power ON”
4
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I » (VS -0.8 V)/RI
has to be added to the above power-down current for each output I, IX, Q, QX.
2. The required LO-Level is a function of the LO frequency (see Figure 8).
3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this purpose. Noise figure measurements without using the differential output signal result in a worse noise figure.
4. Using Pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved.
5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full bandwidth is required, the lowpass Pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can
be increased further by using a resistor between Pins 3, 4, 9 and 10. These resistors shunt the internal loads of
RI ~ 5.4 kW. The decrease in gain here has to be considered.
6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 W
load to approsimately 30 mV. For low signal distortion the load impedance should be RI ³ 5 kW.
2
2
7. Referred to the level of the output vector I + Q
8. The low-gain status is achieved with an open or high-ohmic Pin 11. A recommended application circuit for switching
between high and low gain status is hown in Figure 3.
4
U2794B
4653C–CELL–06/03
U2794B
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified); VS = 5 V, Tamb = 25°C, referred to test circuit
System impedance ZO = 50 W, fiLO = 950 MHz, PiLO = -10 dBm
No.
Parameters
3.2
“Power DOWN”
4
LO Input, LOin
4.1
Frequency range
4.2
Test Conditions
Input level
(2)
Pin
Symbol
Min.
14
VPOFF
17
fiLO
70
17
PiLO
-12
Typ.
-10
4.3
Input impedance
See Figure 12
17
ZiLO
50
4.4
Voltage standing
wave ratio
See Figure 5
17
VSWRLO
1.2
4.5
Duty-cycle range
17
DCRLO
5
RF Input, RFin
5.1
Noise figure (DSB)
symmetrical output
at 950 MHz (3)
at 100 MHz
7, 8
NF
5.2
Frequency range
fiRF = FiLO ± BWYQ
7, 8
fiRF
5.3
-1 dB input
compression point
High gain
Low gain
7, 8
P1dBHG
P1dBLG
5.4
Second order IIP
(4)
7, 8
0.4
Max.
Unit
Type*
1
V
D
1000
MHz
D
-5
dBm
D
W
D
2
D
0.6
D
12
10
dB
D
MHz
D
-8
+3.5
dBm
D
IIP2HG
35
dBm
D
dBm
D
40
1030
5.5
Third order IIP
High gain
Low gain
7, 8
IIP3HG
IIP3LG
+3
+13
5.6
LO leakage
Symmetric input
Asymmetric input
7, 8
LOL
£ -60
£ -55
dBm
D
see Figure 12
7, 8
ZiRF
500II0.8
WIIpF
D
MHz
D
5.7
Input impedance
6
I/Q Outputs (I, IX, Q, QX) Emitter Follower I = 0.6 mA
6.1
3–dB bandwidth
w/o external C
1, 2, 19,
20
BWI/Q
³ 30
6.2
I/Q amplitude error
1, 2, 19,
20
Ae
-0.5
£ ±0.2
+0.5
dB
B
6.3
I/Q phase error
1, 2, 19,
20
Pe
-3
£ ±1.5
+3
Deg
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I » (VS -0.8 V)/RI
has to be added to the above power-down current for each output I, IX, Q, QX.
2. The required LO-Level is a function of the LO frequency (see Figure 8).
3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this purpose. Noise figure measurements without using the differential output signal result in a worse noise figure.
4. Using Pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved.
5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full bandwidth is required, the lowpass Pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can
be increased further by using a resistor between Pins 3, 4, 9 and 10. These resistors shunt the internal loads of
RI ~ 5.4 kW. The decrease in gain here has to be considered.
6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 W
load to approsimately 30 mV. For low signal distortion the load impedance should be RI ³ 5 kW.
2
2
7. Referred to the level of the output vector I + Q
8. The low-gain status is achieved with an open or high-ohmic Pin 11. A recommended application circuit for switching
between high and low gain status is hown in Figure 3.
5
4653C–CELL–06/03
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified); VS = 5 V, Tamb = 25°C, referred to test circuit
System impedance ZO = 50 W, fiLO = 950 MHz, PiLO = -10 dBm
No.
Parameters
Test Conditions
Pin
Symbol
6.4
I/Q maximum output
swing
Symm. output
RL > 5 kW
1, 2, 19,
20
VPP
6.5
DC output voltage
1, 2, 19,
20
VOUT
6.6
DC output offset
voltage
(6)
1, 2, 19,
20
Voffset
6.7
Output impedance
see Figure 12
1, 2, 19,
20
7
Gain Control, GC
7.1
Control range power
Gain high
Gain low
11
7.2
Switch Voltage
7.3
“Gain high”
(7)
Min.
Typ.
Unit
2
2.5
2.8
3.1
Type*
D
V
A
<5
mV
Test
Spec.
Zout
50
W
D
GCR
GH
GL
25
23
-2
dB
dBm
dBm
D
B
D
11
(8)
Max.
1
V
11 < open
7.4
“Gain low”
7.5
Settling Time, ST
7.6
Power “OFF” - “ON”
TSON
<4
µs
D
7.7
Power “ON” - “OFF”
TSOFF
<4
µs
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I » (VS -0.8 V)/RI
has to be added to the above power-down current for each output I, IX, Q, QX.
2. The required LO-Level is a function of the LO frequency (see Figure 8).
3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this purpose. Noise figure measurements without using the differential output signal result in a worse noise figure.
4. Using Pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved.
5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full bandwidth is required, the lowpass Pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can
be increased further by using a resistor between Pins 3, 4, 9 and 10. These resistors shunt the internal loads of
RI ~ 5.4 kW. The decrease in gain here has to be considered.
6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 W
load to approsimately 30 mV. For low signal distortion the load impedance should be RI ³ 5 kW.
2
2
7. Referred to the level of the output vector I + Q
8. The low-gain status is achieved with an open or high-ohmic Pin 11. A recommended application circuit for switching
between high and low gain status is hown in Figure 3.
6
U2794B
4653C–CELL–06/03
U2794B
Figure 3. Test Circuit
PU
* optional for single-ended tests (notice 3 dB bandwidth of AD620)
T1, T2 = transmission line ZO = 50 W.
If no GC function is required, connect Pin 11 to GND.
For high and low gain status GC´ is to be switched to GND respectively to VS.
I/Q output normalized
Figure 4. I and Q phase for fRF > fLO. For fRF < fLO the phase is inverted.
1.5
1.0
Q
I
0.5
0.0
0
5
10
15
20
25
30
-0.5
-1.0
-1.5
time (arbitrary units)
7
4653C–CELL–06/03
Figure 5. Typical VSWR Frequency Response of the LO Input
6
VSWR
5
4
3
2
1
50
250
450
650
1050
850
LO Frequency ( MHz )
Figure 6. Noise Figure versus LO Frequency; o: Value at 950 MHz with RF Input
Matching with T3
18
16
NF (dB)
14
12
10
8
0
200
400
600
800
1000
LO Frequency (MHz)
Figure 7. Typical Suitable LO Power Range versus Frequency
0
PLOmax
PLO (dBm)
-10
-20
PLOmin
-30
-40
-50
30
40
50
60
70
80
90
LO Frequency (MHz)
8
U2794B
4653C–CELL–06/03
U2794B
Figure 8. Gain versus LO Frequency; x: Value at 950 MHz with RF Input Matching with
T3
30
Gain (dB)
26
22
18
14
10
0
200
400
600
800
1000
LO Frequency (MHz)
Figure 9. Typical Output Signal versus LO Frequency for PRF = -15 dBm and
PLO = -15 dBm
1600
1500
VI/Qout (mVpp)
1400
1300
1200
1100
1000
900
800
0
200
400
600
800
1000
LO Frequency (MHz)
Figure 10. Typical Suitable LO Power Range versus Frequency
10
0
PLO (dBm)
-10
-20
-30
-40
-50
0
200
400
600
800
1000
LO Frequency (MHz)
9
4653C–CELL–06/03
Figure 11. Typical Output Voltage (single ended) versus PRF at Tamb = 25°C and
PLO = -15 dBm
1800
1600
VI/Qout (mVpp)
1400
1200
1000
800
600
400
200
0
-40
-35
-30
-25
-20
-15
-10
PRF (dBm)
Figure 12. Typical S11 Frequency Response
j
0.5j
2j
0.2j
0
5j
0.2
0.5
aa
1
cc
2
1
5
bb
-0.2j
-5j
-0.5j
-2j
-j
a: LO input, LO frequency from 100 MHz to 1100 MHz, marker: 950 MHz
b: RF input, RF frequency from 100 MHz to 1100 MHz, marker: 950 MHz
c: I/Q Outputs, Baseband Frequency from 5 MHz to 55 MHz, marker: 25 MHz
10
U2794B
4653C–CELL–06/03
U2794B
Figure 13. Evaluation Board Layout
Figure 14. Evaluation Board
11
4653C–CELL–06/03
External Components
CUCC
CRFX
CLO
CNLO
CRF
CII, CQQ
T3
CI, CIX
CQ, CQX
CPDN
CGC
CPC
CNPC
GSW
100 nF
1 nF
100 pF
1 nF
100 pF
100 pF
100 pF
100 pF
100 pF
optional external lowpass filters
transmission line for RF-input matching, to connect
optionally
optional for AC-coupling at
baseband outputs
not connected
not connected
not connected
gain switch
Calibration Part
CO, CS, CL
RL
Conversion to Single
Ended Output
100 pF
50 W
(see data sheet of AD620)
OP1, OP2
RG1, RG2
RD1, RD2
CS1, CS2
CS3, CS4
12
AD620
prog. gain, see datasheet, for 5.6 k W a gain of 1 at
50 W is achieved together with RD1 and RD2.
450 W
100 nF
100 nF
U2794B
4653C–CELL–06/03
U2794B
Description of the
Evaluation Board
Board material: epoxy; er = 4.8, thickness = 0.5 mm, transmission lines: ZO = 50 W
The board offers the following functions:
•
Test circuit for the U2794B:
–
The supply voltage and the control inputs GC, PC and PU are connected via
a plug strip. The control input voltages can be generated via external
potentiometers; then the inputs should be AC-grounded (time requirements
in burst mode for power up have to be considered).
–
The outputs I, IX, Q, QX are DC coupled via an plug strip or can be ACconnected via SMB plugs for high frequency tests e.g. noise figure or sparameter measurement. The Pins II, IIX, QQ, QQX allow user-definable
filtering with 2 external capacitors CII, CQQ.
–
The offsets of both channels can be adjusted with two potentimeters or
resistors.
–
The LO- and the RF-inputs are AC-coupled and connected via SMB plugs. If
transmission line T3 is connected to the RF-input and AC-grounded at the
other end, gain and noise performance can be improved (input matching to
50 W).
–
The complementary RF-input is AC-coupled to GND (CRFX = 1 nF), the
same appears to the complementary LO input (CNLO = 1 nF).
•
A calibration part which allows to calibrate an s-parameter analyzer directly to the inand output- signal ports of the U2794B.
•
For single-ended measurements at the demodulator outputs, two OPs (e.g., AD620
or other) can be con-figured with programmable gain; together with an outputdivider network RD = 450 W to RL = 50 W, direct measurements with 50 W load
impedances are possible at frequencies t < 100 kHz.
13
4653C–CELL–06/03
Ordering Information
Extended Type Number
Package
Remarks
U2794B-MFS
SSO20
Tube, MOQ 830 pcs
U2794B-MFSG3
SSO20
Taped and reeled, MOQ 4000 pcs
Package Information
5.7
5.3
Package SSO20
Dimensions in mm
6.75
6.50
4.5
4.3
1.30
0.15
0.05
0.25
0.65
5.85
20
0.15
6.6
6.3
11
technical drawings
according to DIN
specifications
1
14
10
U2794B
4653C–CELL–06/03
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© Atmel Corporation 2003.
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Printed on recycled paper.
4653C–CELL–06/03
xM