www.datasheet4u.com uP6161 Preliminary Single 12V Input Supply Dual Regulator Synchronous-Buck-PWM and Linear-Regulator Controller Features General Description The uP6161 integrates a high performance synchronousrectified buck controller and a linear-regulator controller. This part works with a single +12V supply voltage and delivers two high quality output voltages for both processing unit and memory unit. An internal linear regulator provides optimum 9V drive voltage for efficiency and thermal management. The buck controller features internal MOSFET drivers that supports bootstrapped voltage for high efficiency power conversion. The bootstrap diode is built-in to simplify the circuit design and minimize external part count. It incorporates simple, single feedback loop, voltage-control with fast transient response. The linear controller drives an external N-Channel MOSFET with under voltage protection during both soft start and normal operation. Other features include adjustable operation frequency, internal soft start, under voltage protection, adjustable over current protection and shutdown function. With the above function, this part provides customers a compact, well protected and cost-effective solution. This part is available in SOP-14 and QFN3x3 -16L packages. Applications Power Supplies for Microprocessors or Subsystem Power Supplies Cable Modems, Set Top Boxes, and DSL Modems Operate with Single 12V Supply Self-Regulated 9V Drive Voltage Integrated Boot Diode Provide Two Regulated Voltages One Synchronous-Rectified Buck Controller One Linear Controller Both Controllers Drive N-Channel MOSFETs Smaller Converter Size Excellent Output Voltage Regulation 1.5% for Buck Controller 2% for Linear Controller Simple Single-Loop Control Design Voltage-Mode PWM Control Fast Transient Response High-Bandwidth Error Amplifier Lossless, Programmable Overcurrent Protection Uses Lower MOSFET RDS(ON) Adjustable Frequency from 150kHz to 1MHz Internal Soft Start for Both Outputs Under Voltage Protection for Both Outputs including Soft Start Cycle SOP-14 and QFN3x3-16 packages RoHS Compliant and 100% Lead Free Ordering Information Order Number Package Type Industrial Power Supplies; General Purpose Supplies uP6161S14 SOP - 14 12V Input DC-DC Regulators uP6161Q QFN3x3 - 16 Low-Voltage Distributed Power Supplies uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 Remark Note: uPI products are compatible with the current IPC/ JEDEC J-STD-020 and RoHS requirements. They are 100% matte tin (Sn) plating and suitable for use in SnPb or Pbfree soldering processes. 1 www.datasheet4u.com uP6161 Preliminary 11 LGATE LDRV 5 10 PVCC9 LFB 6 9 VCC9 AGND 7 8 VCC12 FB 2 PHASE 4 1 13 FB COMP 12 PGND 11 LGATE PGND LDRV 3 10 PVCC9 LFB 4 9 VCC9 AGND SOP-14 8 PGND VCC12 12 UGATE 3 14 COMP 7 PHASE VCC12 13 BOOT 2 15 RT/DIS 6 UGATE PGND 14 RT/DIS 1 5 BOOT 16 Pin Configuration QFN3x3 – 16L Typical Application Circuit VIN1 +12V VCC12 8 BOOT PVCC9 10 1 UGATE VCC9 14 9 5 uP6161S14 13 LDRV VOUT2 VOUT1 PHASE VIN2 LGATE 11 LFB 6 PGND 13 FB 4 R1 RT/DIS# 2 Disable Enable GND uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 COMP 7 3 R2 2 www.datasheet4u.com uP6161 Preliminary Functional Block Diagram VCC9 SS3 SS2 SS1 Soft Start VCC5 Internal POR & Reference Regulator 0.6V Internal Regulator PVCC9 VOCP 0.6V FB VCC12 Enable & Protection Logic BOOT UGATE 0.4V SS1 Gate Control Logic 0.8V SS2 PHASE PVCC9 LFB 0.8V SS3 Oscillator LGATE LDRV COMP uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 RT/DIS GND PGND 3 www.datasheet4u.com Preliminary uP6161 Functional Pin Description Pin No. SOP QFN Pin Name Pin Function 1 15 Bootstrap Supply for the floating upper gate driver. Connect the bootstrap capacitor CBOOT between BOOT pin and the PHASE pin to form a bootstrap circuit. The bootstrap capacitor BOOT provides the charge to turn on the upper MOSFET. Typical values for CBOOT range from 0.1uF to 0.47uF. Ensure that CBOOT is placed near the IC. 2 16 RT/DIS 3 1 Error Amplifier Output. This is the output of the error amplifier (EA) and the non-inverting COMP input of the PWM comparator. Use this pin in combination with the FB pin to compensate the voltage-control feedback loop of the buck converter. 4 2 FB Feedback Voltage for Buck Converter. This pin is the inverting input to the error amplifier. A resistor divider from the output to GND is used to set the regulation voltage. Use this pin in combi nati on wi th the C OMP pi n to compensate the voltage control feedback loop of the converter. 5 3 LDRV Driver Output for Linear Regulator. This pin provides the gate voltage for the linear regulator pass transistor. Connect this pin to the gate of an external N-Channel MOSFET to form a linear regulator. 6 4 LF B Feedback Voltage for Linear Regulator. This pin is the inverting input to the error amplifier. A resistor divider from the output to GND is used to set the regulation voltage. 7 5 AGND Signal Ground for the IC. All voltages levels are measured with respect to this pin. Tie this pin to the ground island/plane through the lowest impedance connection available. 8 7, 8 9 9 10 10 Pow er PVCC9. This is the output of the internal 9V linear regulator. It provides current required PVCC9 fo r d ri vi ng N-C ha nne l MOS F E Ts o f b uc k c o nve rte r. A mi ni mum 1 uF c e ra mi c c a p a c i to r physically near the IC is required for locally bypassing the input voltage. 11 11 Low er Gate D river Output. C onnect thi s pi n to the gate of lower MOS FE T. Thi s pi n i s LGATE moni tored by the adapti ve shoot-through protecti on ci rcui try to determi ne when the lower MOSFET has turn off. 12 6, 12 Frequency Setting and Chip Disable. A resistor to GND sets the operation frequency of for the buck converter. Pulling this pin to GND disables both buck and linear regulators. Supply Voltage. This is the power supply pin for the IC; it sources the internal 9V regulator VCC12 used to the gate drivers. A minimum 1uF ceramic capacitor is required for locally bypassing the input voltage. VC C 9 VCC9. This pin supplies bias current for the IC. A minimum 1uF ceramic capacitor physically near the IC is required for locally bypassing the input voltage. PGND Pow er Ground for the IC. 13 13 PHASE Sw itch Node. Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin is used as the sink for the UGATE driver, and to monitor the voltage drop across the lower MOSFET for over current protection. This pin is also monitored PHASE by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. A Schottky diode between this pin and ground is recommended to reduce negative transient voltage which is common in a power supply system. 14 14 U pper Gate D river Output. C onnect thi s pi n to the gate of upper MOS FE T. Thi s pi n i s UGATE moni tored by the adapti ve shoot-through protecti on ci rcui try to determi ne when the upper MOSFET has turned off. Exposed Pad Pow er Ground for the IC. For QFN package only. This exposed pad should be well soldered to PCB for effective heat conduction. Connect the exposed pad the ground. uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 4 www.datasheet4u.com uP6161 Preliminary Functional Description The buck controller features internal MOSFET drivers that supports 12V + 12V bootstrapped voltage for high efficiency power conversion. The bootstrap diode is built-in to simplify the circuit design and minimize external part count. It incorporates simple, single feedback loop, voltage-control with fast transient response. The linear controller drives an external N-Channel MOSFET with undervoltage protection during both softstart and normal operation. Other features include adjustable operation frequency, internal softstart, undervoltage protection, adjustable overcurrent protection and shutdown function. Supply Voltage The uP6161 is designed to work with a single supply rail. It integrates two linear regulators providing optimal supply voltages for gate drivers and control circuitry respectively as shown in Figure 1. The 9V linear regulator generates 9V PVCC9 for gate drives achieving optimum balance between efficiency and thermal management. The 5V linear regulator works with VCC9 input generates VCC5 for internal control circuitry. If 12V driving voltage is preferred, simply connect +12V to the PVCC9 pin and let VCC12 open. +12V VCC12 9V Linear Regulator PVCC9 uP6161 Gate Drivers POR Monitoring VCC9 power on reset with typical rising threshold level as 7.5V. All the three supply inputs require minimum 1uF ceramic capacitors for local bypassing. Place the bypass capacitors physically near the IC. No external bypass capacitor is required for filtering the VCC5 voltage. Bootstrap Circuitry The uP6161 integrates MOSFET gate drives that are powered from the PVCC9 pin and support 12V+12V driving capability. A bootstrap diode is embedded to facilitates PCB design and reduce the total BOM cost. Connect a ceramic bootstrap diode between BOOT and PHASE pins to form a bootstrap circuit for providing charge to turn on/off the upper MOSFET. No external Schottky diode is required. Converters that consist of uP6161 feature high efficiency without special consideration on the selection of MOSFETs. Chip Enable and Frequency Setting The RT/DIS is a multifunctional pin: chip shutdown and frequency setting. Pulling low this pin to GND by an open drain/collector transistor shuts down the uP6161 and disables both buck and linear controllers. The switching frequency is set by a resistor connecting to the RT/DIS pin as: fOSC = 23500000 + 74000 RRT (Hz) Figure 2 shows the dependence between the resistor chosen and the resulting switching frequency. 1000 Switching Frequency (kHz) The uP6161 integrates a high performance synchronousrectified buck controller and a linear-regulator controller. This part works with a single +12V supply voltage and delivers two high quality output voltages for both processing unit and memory unit. An internal linear regulator provides optimum 9V drive voltage for efficiency and thermal management. 100 5V Linear Regulator 10 Control Circuitry 100 RRT (kohm) 1000 Figure 2. Switching Frequency vs. RRT Soft Start Figure 1. Supply Voltage Configuration Once POR is acknowledged and RT/DIS pin is released, Both PVCC9 and VCC9 are continuously monitored for uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 5 www.datasheet4u.com uP6161 Preliminary Functional Description the uP6161 initiates its digital soft start cycle to prevent surge current from power supply input during turn on (referring to the Functional Block Diagram). The error amplifiers are three-input devices. Reference voltage VREF or the internal soft start voltage SS2/SS3 whichever is smaller dominates the behavior of the non-inverting inputs of the error amplifiers. SS2/SS3 internally ramps up to 0.8V in 4096 cycles of the internal oscillator frequency after the after the softstart cycle is initiated. Take 600kHz switching frequency for example (1.67us per cycle), the ramp-up time is about 6.8ms. Accordingly, the output voltages follow the soft start signals SS2/SS3 and linearly ramp up to their final level, resulting minimum inrush current from input voltage. The SS2/SS3 signals keep ramping up after it exceeds the internal 0.8V reference voltages. However, the internal 0.8V reference voltages takes over the behavior of error amplifier after SS > VREF. When the SS2/SS3 signal climb to its ceiling voltage (5V), the uP6161 claims the end of softstart cycle and enable the under voltage protection of the output voltages. Figure 3 shows a typical start up interval for uP6161 where the RT/DIS pin has been released from a grounded (system shutdown) state. Note the LDO output voltage (LVO) starts ramping up only after the PWM output voltage (SVO) is within regulation. RT/DIS (1V/Div) SVO (0.5V/Div) LVO (0.5V/Div) ramping up to 5VDD. Another softstart is initiated after SS ramps up to 5VDD. The hiccup period is about 8ms. Figure 4 shows the start up interval where VIN does not present initially. SVO (0.5V/Div) V IN (5V/Div) LVO (0.5V/Div) LGATE (10V/Div) Time (5ms/Div) Figure 4. Softstart where VIN does not Present Initially. Output Voltage Selection The output voltage can be programmed to any level between the 0.8V internal reference, up to the 80% of VIN supply. The lower limitation of output voltage is caused by the internal reference. The upper limitation of the output voltage is caused by the maximum available duty cycle (80% typical). This is to leave enough time for overcurrent detection. Output voltage out of this range is not allowed. A voltage divider sets the output voltage (refer to the Typical Application Circuit on page 1 for detail). In real applications, choose R2 in 100Ω ~ 10kΩ range and choose appropriate R1 according to the desired output voltage. VOUT = VREF × R1 + R2 R1 + R2 = 0.8 V × R2 R2 Overcurrent Protection (OCP) PHASE (10V/Div) Time (5ms/Div) Figure 3. Softstart Behavior. Power Input Detection The uP6161 detects PHASE voltage for the present of power input when the UGATE turns on the first time. If the PHASE voltage does not exceed 2.0V when the UGATE turns on, the uP6161 asserts that power input in not ready and stops the softstart cycle. However, the internal SS continues uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 The uP6161 detects voltage drop across the lower MOSFET (VPHASE) for overcurrent protection when it is turned on. If VPHASE is lower than the user-programmable voltage VOCP, the uP6161 asserts OCP and shuts down the converter. The OCP level can be calculated according the onresistance of the lower MOSFET used. IOCP = − VOCP RDS(ON) (A) Connecting a resistance from LGATE to GND selects the 6 www.datasheet4u.com Preliminary uP6161 Functional Description appropriate VOCP as shown in Table 1. Also shown in Table 1 is OCP level if a lower MOSFET with 10mΩ RDS(ON) is used. When programming the OCP level, take into consideration the conditions that affect RDS(ON) of the lower MOSFET, including operation junction temperature, gate driving voltage and distribution. Consider the RDS(ON) at maximum operation temperature and lowest gate driving voltage. Table 1. OCP Level Selection ROCP (Ω) open 42k 24k 10k VOCP (mV) -375 -300 -225 -150 IOCP (A) 37.5 25 22.5 15 Another factor should taken into consideration is the ripple of the inductor current. The current near the valley of the ripple current is used for OCP, resulting the averaged OCP level a little higher than the calculated value. Output Under Voltage Protection of Linear Regulator The LDRV and LFB voltages are monitored during both softstart and normal operation for output under voltage protection. The uP6161 asserts UVP if the error amplifier saturates, LDRV goes to ceiling high and LFB voltage is lower than 0.6V for 10us. This demands VCC12 > (VOUT + VTH + 1V) where VTH is the threshold voltage of the external N-Channel MOSFET. This is to ensure that the output voltage can follow the softstart signal and will not saturate the error amplifier. That means a low threshold voltage MOSFET is required for low VCC12 applications. This also demands that VIN2 should be ready before the soft start cycle is initiated. The uP6161 disables the output voltages upon the triggering of UVP. The uP6161 repeats the softstart cycle if the output under voltage is not removed. uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 7 www.datasheet4u.com uP6161 Preliminary Absolute Maximum Rating Supply Input Voltage, VCC12 (Note 1) -------------------------------------------------------------------------------------------- -0.3V to +15V PHASE to GND DC ------------------------------------------------------------------------------------------------------------------------------------- -1V to 15V < 200ns ---------------------------------------------------------------------------------------------------------------------------- -3V to 30V BOOT to PHASE ---------------------------------------------------------------------------------------------------------------------------- -0.3V to +15V UGATE to PHASE ------------------------------------------------------------------------------------------------ -0.3V to (BOOT - PHASE +0.3V) PVCC9, VCC9, LDRV ----------------------------------------------------------------------------------------------------- -0.3V to VCC12 + 0.3V LGATE ------------------------------------------------------------------------------------------------------------------------ -0.3V to + (PVCC9 + 0.3V) Other Pins -------------------------------------------------------------------------------------------------------------------------------------- -0.3V to +6V Storage Temperature Range ------------------------------------------------------------------------------------------------------------- -65OC to +150OC Junction Temperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC Lead Temperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC ESD Rating (Note 2) HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V Thermal Information Package Thermal Resistance (Note 3) θJA SOP-14 ------------------------------------------------------------------------------------------------------------------------------ 120°C/W θJC QFN3x3-16 ----------------------------------------------------------------------------------------------------------------------------- 5OC/W θJA QFN3x3-16 ---------------------------------------------------------------------------------------------------------------------------- 68OC/W Power Dissipation, PD @ TA = 25°C SOP-14 ----------------------------------------------------------------------------------------------------------------------------------------------- 0.83W QFN3x3-16 ------------------------------------------------------------------------------------------------------------------------------------------ 1.47W Recommended Operation Conditions Operating Junction Temperature Range (Note 4) ------------------------------------------------------------------------ -40°C to +125°C Operating Ambient Temperature Range -------------------------------------------------------------------------------------- -40°C to +85°C Supply Input Voltage, VCC12 ----------------------------------------------------------------------------------------------------------- +10.8V to 13.2V Electrical Characteristics (VCC12 = 12V, TA = 25OC, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Units Supply Input Supply Voltage V C C 12 Supply Current ICC12 Quiescent Supply Current ICC12_Q 10.8 -- 13.2 V UGATE and LGATE Open; VCC12 = 12V, Switching -- 4 -- mA VFB = VREF + 0.1V, No Switching -- 3 -- mA 13.2 V VIN1 3.0 VCC12 POR Threshold VCC12RTH -- 8.7 -- V PVCC9 POR Threshold VVCC9RTH PVCC9 = VCC9 rising -- 7.5 8 V POR Hysteresis VCC9HYS PVCC9 = VCC9 falling -- 0.8 -- V Power Input Voltage Pow er On Reset uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 8 www.datasheet4u.com uP6161 Preliminary Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Units -- 9.0 -- V 540 620 700 kHz -- 4 -- V -- 6.8 -- ms P V C C 9 LD O PVCC9 Output Voltage PVC C 9 V C C 12 = 1 2 V Oscillator and Soft Start Switching Frequency fOSC Sawtooth Amplitude ΔVOSC Soft Start Interval TSS RRT = 45.3kΩ fOSC = 620kHz Reference Voltage Reference Voltage for PWM VREF 0.788 0.8 0.812 V Reference Voltage for LDO VREF 0.784 0.8 0.816 V Error Amplifier for Buck Controller Open Loop DC Gain Gain-Bandwidth Product Slew Rate AO Guaranteed by Design 55 70 -- dB GBWP Guaranteed by Design -- 10 -- MHz SR Guaranteed by Design 4 6 -- V/us COMP High Output Voltage VCOMP_H -- 4.7 -- V COMP Low Output Voltage VCOMP_L -- 0.6 -- V COMP High Source Current ICOMP_H -- -2.8 -- mA Undervoltage Level (VFB/VREF) VUVP 70 75 80 % Buck Controller Gate Drivers UGATE Source Current IUG_SRC PVCC = 9V, VBOOT - VUG = 8V -- -1.5 -- A UGATE Sink Output Impedance RUG_SNK PVCC = 9V, IUG = 100mA -- 2 4 Ω LGATE Source Current ILG_SRC PVCC = 9V, VLG = 1V -- -1.5 -- A LGATE Sink Output Impedance RLG_SNK PVCC = 9V, ILG = 100mA -- 2 4 Ω 70 75 80 % Maximum Duty Cycle Linear-Regulator Controller AO Guaranteed by Design 55 70 -- dB GBWP Guaranteed by Design -- 2 -- MHz Slew Rate SR Guaranteed by Design 2 4 -- V/us FB Bias Current IFB VFB = 0.8V -- 0.01 1 uA LDRV High Output Voltage VLDRV_H P V C C = 9V -- 8.5 9.0 V LDRV Low Output Voltage VLDRV_L P V C C = 9V -- 0.0 0.5 V LDRV High Source Current ILDRV_H 5 -- -- mA LDRV Low Sink Current ILDRV_L 5 -- -- mA Undervoltage Level (VLFB/VREF) VUVP 70 75 80 % Open Loop DC Gain Gain-Bandwidth Product Percent of Nominal uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 9 www.datasheet4u.com uP6161 Preliminary Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Units -- -375 -- mV 0.3 0.4 0.5 V Protection Over Current Threshold VPHASE Enable Threshold VRT/DIS RLGATE = open Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions. uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 10 www.datasheet4u.com uP6161 Preliminary Typical Operation Characteristics Turn On Waveforms Power On Waveforms SVOUT (0.5V/Div) VCC12 (5V/Div) LVOUT (0.5V/Div) PVCC9 (5V/Div) SVOUT (0.5V/Div) RT/DIS (0.5V/Div) LVOUT (0.5V/Div) PHASE (10V/Div) 2.5ms/Div 5ms/Div Gate Waveforms Gate Waveforms UGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div) LGATE (5V/Div) PHASE (5V/Div) LGATE (5V/Div) UGATE-PHASE (5V/Div) UGATE-PHASE (5V/Div) 25ns/Div 25ns/Div Over Current Protection Trun Off Waveforms RT/DIS (1V/Div) SVOUT (0.5V/Div) LDRV (2V/Div) PHASE (10V/Div) PHASE (10V/Div) IOUT (10A/Div) 10ms/Div uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 5us/Div 11 www.datasheet4u.com uP6161 Preliminary Typical Operation Characteristics PVCC9 Voltage vs. VCC12 Voltage Switching Frequency vs. RRT 10 1000 Switching Frequency (kHz) PVCC9 Voltage (V) 9.5 9 8.5 8 7.5 100 7 8 10 12 1000 PVCC9 Voltage vs. Temperature DC/DC Output Voltage vs. Temperature DC/DC Output Voltage Variation (%) 9.06 9.05 9.04 9.03 9.02 9.01 9 -50 0 50 100 0.5 0.2 -0.1 -0.4 -0.7 -1 -50 150 O 0 50 100 150 O Junction Temperature ( C) VCC12 = 12V Junction Temperature ( C) Switching Frequency vs. Temperature LDO Output Voltage vs. Temperature 2 0.5 LDO Output Voltage Variation (%) Switching Frequency Variation (%) 100 RRT (kΩ) 9.07 PVCC9 Output Voltage (V) 10 14 VCC12 Voltage (V) 1 0 -1 -2 -3 -4 -50 0 50 100 O Junction Temperature ( C) uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 150 0.3 0.1 -0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3 -1.5 -50 0 50 100 150 O Junction Temperature ( C) 12 www.datasheet4u.com Preliminary uP6161 Application Information This page is intentionally left blank and will be updated when the silicon data is available. uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 13 www.datasheet4u.com uP6161 Preliminary Package Information SOP-14 Package 0.76 REF 1.27 REF 1.85 REF 8.50 - 8.75 5.80 - 6.20 3.80 - 4.00 4.00 MIN 8.00 MIN 6.15 REF 1.27 BSC 0.32 - 0.52 Recommended Solder Pad Layout 1.45 - 1.60 0.20 BSC 0.18 - 0.25 1.75 MAX 0.10 - 0.25 0.41 - 0.89 7.62 BSC Note 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm. uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 14 www.datasheet4u.com uP6161 Preliminary Package Information QFN3x3 - 16L Package 0.35 - 0.45 1.50 - 1.75 9 13 1.50 - 1.75 2.90 - 3.10 Pin 1 mark (Note 6) 5 1 2.90 - 3.10 0.18 - 0.30 0.50 BSC Bottom View - Exposed Pad 0.80 - 1.00 3.45 - 3.55 1.60 - 1.70 0.00 - 0.05 2.10 - 2.20 0.20 - REF 0.20 - 0.30 0.50 BSC Recommended Solder Pitch and Dimensions Note 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm. uPI Semiconductor Corp., http://www.upi-semi.com Rev. P00, File Name: uP6161-DS-P0001 15