NEC UPC8104

DATASHEET
SHEET
DATA
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC8104GR
UP CONVERTER + QUADRATURE MODULATOR IC
FOR DIGITAL MOBILE COMMUNICATION SYSTEMS
DESCRIPTION
The µPC8104GR is a silicon monolithic integrated circuit designed as quadrature modulator for digital mobile
communication systems. This modulator consists of 1.9 GHz up-converter and 400 MHz quadrature modulator which
are packaged in 20 pin SSOP. The device has power save function and can operate 2.7 to 5.5 V supply voltage,
therefore, it can contribute to make RF block small, high performance and low power consumption.
FEATURES
•
20 pin SSOP suitable for high density surface mounting.
•
High linearity up converter is incorporated; PRFout(sat) = −6 dBm TYP.
•
Low phase difference due to digital phase shifter is adopted.
•
Wide operating frequency range.
•
External IF filter can be applied between modulator output and up converter input terminal.
•
Supply voltage: VCC = 2.7 to 5.5 V
•
Equipped with power save function.
Up converter; fRFout = 800 MHz to 1.9 GHz
Modulator
; fMODout = 100 MHz to 400 MHz, fI/Q = DC to 10 MHz
APPLICATION
•
Digital cordless phones
•
Digital cellular phones
ORDERING INFORMATION
PART NUMBER
µPC8104GR-E1
PACKAGE
20 pin plastic SSOP
SUPPLYING FORM
Embossed tape 12 mm wide. QTY 2.5 kp/Reel.
Pin 1 indicates pull-out direction of tape.
* For evaluation sample order, please contact your local NEC sales office. (Order number: µPC8104GR)
Caution electro-static sensitive device
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. P10099EJ4V0DS00 (4th edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1995, 1999
µPC8104GR
INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (Top View)
Lo1 in 1
Lo1 in 2
20 VCC
90˚
Phase
Shifter
REG.
19 Power Save
GND 3
(MOD)
18 GND
I 4
17 GND
I 5
16 MOD out
Q 6
15 Up Con in
Q 7
14 Up Con in
13 VCC
(UP Con)
GND 8
(UP Con)
RF out 9
12 Lo2 in
GND 10
(UP Con)
11 Lo2 in
APPLICATION EXAMPLE
(PHS)
RX
DEMO.
÷N
SW
I
Q
PLL
PLL
µ PC8104GR
I
0˚
φ
TX
PA
90˚
Q
Filter
2
Data Sheet P10099EJ4V0DS00
µPC8104GR
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
TEST CONDITION
Supply Voltage
VCC
6.0
V
TA = +25 °C
Power Save Voltage
VPS
6.0
V
TA = +25 °C
Power Dissipation
PD
430
mW
TA = +85 °C
Operating Temperature
TA
−40 to +85
°C
Storage Temperature
Tstg
−55 to +150
°C
Note1
Note 1: Mounted on 50 × 50 × 1.6 mm double copper clad epoxy glass board
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply Voltage
VCC
2.7
3.0
5.5
V
Operating Temperature
TA
−40
+25
+85
°C
fRFout
0.8
1.9
GHz
Up Converter Input Freq.
fUpConin
100
400
MHz
Modulator Output Frequency
fMODout
Up Converter RF Frequency
TEST CONDITIONS
PLo1in = −10 dBm
Lo1 Input Frequency
fLo1in
Lo2 Input Frequency
fLo2in
800
1800
MHz
PLo2in = −10 dBm
I/Q Input Frequency
fI/Qin
DC
10
MHz
PI/Qin = 600 mVp-p MAX (Single ended)
ELECTRICAL CHARACTERISTICS (TA = +25 °C, VCC = 3.0 V, Unless Otherwise Specified VPS ≥ 1.8 V)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
28
37
mA
No input signal
0.1
10
µA
VPS ≤ 1.0 V
−13.5
−8.5
dBm
LOL
−40
−30
dBc
ImR
−40
−30
dBc
UP CONVERTER + QUADRATURE MODULATOR TOTAL
Total Circuit Current
Total Circuit Current at
Power-Save Mode
Total Output Power
Lo Carrier Leak
Note2
Image Rejection (Side Band
Leak)
IccTOTAL
18
Icc(PS)TOTAL
PRFout
−18.5
I/Q DC = 1.5 V
PI/Qin = 500 mVp-p (Single ended)
Note 2: Lo1 + Lo2
Data Sheet P10099EJ4V0DS00
3
µPC8104GR
STANDARD CHARACTERISTICS FOR REFERENCE
(TA = +25 °C, VCC = 3.0 V, Unless Otherwise Specified VPS ≥ 1.8 V)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
UP CONVERTER BLOCK
Up Con. Circuit Current
Up Con. Circuit Current at
Power-Save Mode
Conversion Gain
IccUpCon
12
Icc(PS)UpCon
5
mA
No input signal
µA
VPS ≤ 1.0 V
fRFout = 1.9 GHz
CG
4
dB
Maximum Output Power
PRF(sat)
−6
dBm
Output Intercept Point
OIP3
0
dBm
fUpConin = 240.0 MHz/240.2 MHz
QUADRATURE MODULATOR BLOCK
MOD. Circuit Current
MOD. Circuit Current at
Power-Save Mode
10
16
Icc(PS)MOD
21
mA
No input signal
5
µA
VPS ≤ 1.0 V
PMODout
−16.5
Lo1 Carrier Leak
LOL
−40
−30
dBc
Image Rejection
(Side Band Leak)
ImR
−40
−30
dBc
I/Q 3rd Order Intermodulation
Distortion
IM3I/Q
−50
−30
dBc
I/Q Input Impedance
ZI/Q
20
kΩ
I/Q Bias Current
II/Q
5
µA
Lo1 Input VSWR
ZLo1
1.2:1
X:1
Power Save Rise Time
TPS(RISE)
2.0
5.0
µs
VPS(OFF) → VPS(ON)
Power Save Fall Time
TPS(FALL)
2.0
5.0
µs
VPS(ON) → VPS(OFF)
Output Power
4
IccMOD
dBm
Data Sheet P10099EJ4V0DS00
I/Q DC = 1.5 V
PI/Qin = 500 mVp-p (Single ended)
I/Q DC = 1.5 V
PI/Qin = 500 mVp-p (Single ended)
(I → I, Q → Q)
µPC8104GR
PIN EXPLANATION
PIN
NO.
ASSIGNMENT
SUPPLY
VOL. (V)
PIN
VOL.(V)
1
Lo1in
−
0
2
Lo1in
−
2.4
FUNCTION AND APPLICATION
Lo1 input for phase shifter.
This input impedance is 50 Ω
matched internally.
GND for
modulator
0
−
Connect to the ground with
minimum inductance.
Track length should be kept as
short as possible.
4
I
VCC/2
−
Input for I signal. This input
impedance is larger than 20 kΩ.
Relations between amplitude
and VCC/2 bias of input signal
are following.
VCC/2 (v)
≥ 1.35
Amp. (mVp-p) Note
400
≥ 1.5
600
≥ 1.75
1000
5
I
VCC/2
−
Input for I signal. This input
impedance is larger than 20 kΩ.
VCC/2 biased DC signal should
be input.
6
Q
VCC/2
−
Input for Q signal. This input
impedance is larger than 20 kΩ.
VCC/2 biased DC signal should
be input.
7
Q
VCC/2
−
Input for Q signal. This input
impedance is larger than 20 kΩ.
Relations between amplitude
and VCC/2 bias of input signal
are following.
VCC/2 (v)
MODout
−
1.5
1
50 Ω
Bypass of Lo1 input.
This pin is grounded through
internal capacitor.
Open in case of single ended.
3
16
EQUIPMENT CIRCUIT
2
4
5
7
6
Amp. (mVp-p) Note
≥ 1.35
400
≥ 1.5
600
≥ 1.75
1000
Output from modulator.
This is emitter follower output.
16
Note In case of that I/Q input signals are single ended.
Of course, I/Q signal inputs can be used either single endedly or differentially with proper terminations.
Data Sheet P10099EJ4V0DS00
5
µPC8104GR
PIN EXPLANATION
PIN
NO.
ASSIGNMENT
SUPPLY
VOL. (V)
PIN
VOL.(V)
8
GND
for Upconverter
0
−
11
Lo2in
−
2.0
Bypass of Lo2 input.
Grounded through external
capacitor.
12
Lo2in
−
0
Lo2 input of Up-converter.
This pin is high impedance
input.
13
VCC for Upconverter
2.7 to 5.5
−
Supply voltage pin for Upconverter.
9
RFout
VCC
−
RF output from Up-Converter.
This pin is open collector output.
10
FUNCTION AND APPLICATION
Connect to the ground with
minimum inductance.
Track length should be kept as
short as possible.
EQUIPMENT CIRCUIT
12
11
9
14
UpConin
−
2.0
IF input for Up-converter.
This pin is high impedance
input.
15
UpConin
−
2.0
Bypass of IF input.
Grounded through external
capacitor.
17
GND
0
−
Connect to the ground with
minimum inductance.
Track length should be kept as
short as possible.
Power
Save
VP/S
−
Power save control pin can be
controlled ON/SLEEP state with
bias as follows;
18
19
VP/S (v)
1.8 to 5.5
0 to 1.0
20
VCC for
Modulator
2.7 to 5.5
−
STATE
ON
SLEEP
Supply voltage pin for
modulator. Internal regulator
can be kept stable condition of
supply bias against the variable
temperature or VCC.
: Externally
6
Data Sheet P10099EJ4V0DS00
14
15
19
µPC8104GR
EXPLANATION OF INTERNAL FUNCTION
BLOCK
90° PHASE
SHIFTER
FUNCTION/OPERATION
BLOCK DIAGRAM
Input signal from Lo1 is send to digital
circuit of T-type flip-flop through frequency
doubler. Output signal from T-type F/F is
changed to same frequency as Lo1 input
and that have quadrature phase shift, 0°,
90°, 180°, 270°. These circuits have
function of self phase correction to make
correctly quadrature signals.
from Lo1in
×2
÷ 2 F/F
BUFFER AMP.
Buffer amplifiers for each phase signals to
send to each mixers.
MIXER
Each signals from buffer amp. are
quadrature modulated with two doublebalanced mixers.
High accurate phase and amplitude inputs
are realized to good performance for
image rejection.
I
I
Q
Q
ADDER
Output signals from each mixers are
added with adder and send to final
amplifier.
to MODout
Data Sheet P10099EJ4V0DS00
7
µPC8104GR
TYPICAL CHARACTERISTICS (TA = +25 °C)
Unless otherwise specified VCC = VPS = 3 V, I/Q DC offset = I/Q DC offset = 1.5 V, I/Q Input Signal = 500 mVp-p
(single ended), PLo1in = −10 dBm, PLo2in = −10 dBm, (continuous wave)
SUPPLY VOLTAGE vs CIRCUIT CURRENT
[UP CONVERTER BLOCK]
40
SUPPLY VOLTAGE vs CONVERSION GAIN
35
RF : 1.9 GHz
Lo2 : 1.66 GHz, –20 dBm
IF : 240 MHz, –20 dBm
VPS = VCC = 3 V
10
CG - Conversion Gain - dB
ICC - Circuit Current - mA
30
25
20
15
5
0
VCC = VPS = 3 V
RF None
ICC Total
ICC MOD
ICC Up Con
10
5
0
1
2
3
4
VCC - Supply Voltage - V
0
0
8
1
2
3
4
VCC - Supply Voltage - V
5
6
Data Sheet P10099EJ4V0DS00
5
6
µPC8104GR
[UP CONVERTER BLOCK]
[UP CONVERTER BLOCK]
Lo2 INPUT POWER vs CONVERSION GAIN
INPUT POWER vs OUTPUT POWER, IM3
+10
OIP3 = +0.2 dBm
10
CG - Conversion Gain - dB
0
Pout - Up Con. Output Power, IM3 - dBm
–10
–20
–30
PRFout
–40
fRFout = 1.9 GHz
fLo2in = 1.66 GHz
fIFin = 240 MHz
PIFin = –20 dBm
VCC = VPS = 3 V
5
0
IM3
–50
–40
–60
–70
–80
–40
–30
–20
–10
0
PLo2in - Lo2 Input Power - dBm
+10
fRFout = 1.9 GHz
fLo2in = 1.66 GHz
PLo2in = –10 dBm
fIFin1 = 240.0 MHz
fIFin2 = 240.2 MHz
VCC = VPS = 3V
–30
–20
–10
0
PUpConin - Up Con. Input Power - dBm
+10
Data Sheet P10099EJ4V0DS00
9
µPC8104GR
[UP CONVERTER BLOCK]
[UP CONVERTER BLOCK]
Lo2 INPUT POWER vs CONVERSION GAIN
SUPPLY VOLTAGE vs CONVERSION GAIN
RF : 900 MHz
Lo2 : 1 140 MHz, –20 dBm
IF : 240 MHz, –20 dBm
VPS = VCC = 3 V
CG - Conversion Gain - dB
GC - Conversion Gain - dB
15
fRFout = 900 MHz
fLo2in = 1 140 MHz
fIFin = 240 MHz
PIFin = –20 dBm
15
VCC = VPS = 3 V
10
10
5
5
1
2
3
4
VCC - Supply Voltage - V
5
–40
6
[UP CONVERTER BLOCK]
INPUT POWER vs OUTPUT POWER, IM3
Lo1 INPUT POWER vs OUTPUT POWER,
LOCAL LEAK, IMAGE REJECTION,
I/Q 3RD ORDER INTERMODULATION
DISTORTION
OIP3 = +7 dBm
–20
PRFout
–30
–40
IM3
–50
–60
fRFout = 900 MHz
fLo2in = 1 140 MHz
PLo2in = –10 dBm
fIFin1 = 240.0 MHz
fIFin2 = 240.2 MHz
VCC = VPS = 3 V
–30
–20
–10
0
PUpConin - Up Con. Input Power - dBm
+10
LOL (ISOLO) - Local Leak, ImR - Image Rejection, IM3 I/Q - dBc
Pout - Up Con. Output Power, IM3 - dBm
–10
10
–10
10
0
–80
–40
+10
[MODULATOR BLOCK]
+10
–70
–30
–20
–10
0
PLo2in - Lo2 Input Power - dBm
<PHS>
384 kbps
RNYQ
0
α = 0.5
<0000>
All zero
Pout
–20
–10
–20
LOL (ISOLO)
–30
–30
–40
ImR
–40
–50
–60
–70
–30
Data Sheet P10099EJ4V0DS00
IM3I/Q
–20
–10
0
PLo1in - Lo1 Input Power - dBm
–50
+10
PMODout - Modulator Output Power - dBm
0
µPC8104GR
[MODULATOR BLOCK]
[MODULATOR BLOCK]
0
Pout
–10
–20
–20
–30
–30
LOL (ISOLO)
–40
ImR
–40
–50
PMODout - Modulator Output Power - dBm
LOL (ISOLO) - Local Leak, ImR - Image Rejection, IM3 I/Q - dBc
(PHS) 384 Kbps
RNYQ α = 0.5
(0000) All zero
–10
–10
Pout
–20
–20
ImR
–30
–30
–40
–40
LOL (ISOLO)
–50
–50
IM3I/Q
–60
–70
50
100
–60
200
PMODout - Modulator Output - Power - dBm
–10
10
LOL(ISOLO) - Local Leak, ImR - Image Rejection, IM3 I/Q - dBC
Lo1 INPUT FREQUENCY vs OUTPUT POWER,
LOCAL LEAK, IMAGE REJECTION, I/Q 3RD,
ORDER INTERMODULATION DISTORTION
I/Q INPUT SIGNAL vs OUTPUT POWER,
LOCAL LEAK, IMAGE REJECTION,
I/Q 3RD ORDER INTERMODULATION
DISTORTION
–70
500
fLo1 - Lo1 Input Frequency - MHz
–60
IM3I/Q
–50
–70
0
0.5
1
PI/Qin - I/Q Input Signal - Vp-p
[MODULATOR + UP CONVERTER]
[MODULATOR BLOCK]
I/Q INPUT SIGNAL vs VECTOR ERROR,
MAGNITUDE ERROR, PHASE ERROR
7
∆M
5
∆A
3
∆φ
2
7
5
∆M
3
∆A
2
1
0
VCC = 3 V
Lo1: 15 dBm
I/Q DC 1 500 mV
AC 430 mVp-p
<PHS> 384 kbps
RNYQ α = 0.5
PN9
10
∆φ - Phase Error - deg.
∆ A - Magnitude Error - %rms
∆ M - Vector Error - %rms
∆φ - Phase Error - deg.
∆ A - Magnitude Error - %rms
∆ M - Vector Error - %rms
10
VCC = 3 V
Lo1: 240 MHz
–10 dBm
Lo2: 1 660 MHz
–8 dBm
I/Q DC 1 500 mV
AC
<PHS> 384 kbps
RNYQ α = 0.5
PN9
Lo1 INPUT FREQUENCY vs VECTOR ERROR,
MAGNITUDE ERROR, PHASE ERROR
∆φ
1
0
500
1 000
1 500
0
0
PI/Qin - I/Q Input Signal - mVp-p
100
200
300
400
500
fLo1 - Lo1 Input Frequency - MHz
Data Sheet P10099EJ4V0DS00
11
µPC8104GR
[MODULATOR + UP CONVERTER]
[MODULATOR BLOCK]
TYPICAL SINE WAVE MODULATION
OUTPUT SPECTRUM
TYPICAL SINE WAVE MODULATION
OUTPUT SPECTRUM
REF 0.0 dBm
10 dB/
RBW
3 kHz
VBW
10 kHz
SWP
5.0 s
REF 0.0 dBm
10 dB/
–ATT 10 dB
RBW
1 kHz
VBW
1 kHz
SWP
2.0 s
CENTER 1.9000000 GHz
SPAN 200.0 kHz
ATT 10 dB
CENTER 240.0000 MHz
SPAN 200.0 kHz
<PHS> 384 Kbps, RNYQ α = 0.5, MOD Pattern (0000), all zero.
[MODULATOR + UP CONVERTER]
[MODULATOR BLOCK]
TYPICAL π/4 DQPSK MODULATION OUTPUT SPECTRUM
<PDC> 42 kbps, RNYQ α = 0.5, MOD Pattern <PN9>
REF 0.0 dBm
10 dB/
ATT 10 dB
MARKER
1.4999000 GHz
72.00 dB
ADJ BS
21.0 kHz
1
DL 0.0 dBm
3
2
RBW 3 kHz
VBW 3 kHz
SWP 5.0 s CENTER 1.500000 GHz
REF –10.0 dBm
10 dB/
ATT 0 dB
MARKER
289.9000 MHz
76.50 dB
ADJ BS
21.0 kHz
DL –10.0 dBm
4
SPAN 500 kHz
1
2
3
RBW 3 kHz
VBW 3 kHz
SWP 5.0 s CENTER 240.0000 MHz
4
SPAN 500 kHz
∗∗∗ Multi Marker List ∗∗∗
No. 1: 239.9000 MHz –76.50 dB
No. 2: 239.9500 MHz –70.50 dB
No. 3: 240.0500 MHz –71.00 dB
No. 4: 240.1000 MHz –75.75 dB
∗∗∗ Multi Marker List ∗∗∗
No. 1: 1.4999000 GHz –72.00 dB
No. 2: 1.4999500 GHz –66.00 dB
No. 3: 1.5000500 GHz –68.75 dB
No. 4: 1.5001000 GHz –72.00 dB
[MODULATOR + UP CONVERTER]
[MODULATOR BLOCK]
TYPICAL π/4 DQPSK MODULATION OUTPUT SPECTRUM
<PHS> 384 kbps, RNYQ α = 0.5, MOD Pattern (PN9)
ATT 0 dB
REF –10.0 dBm
10 dB/
MARKER
1.899100 GHz
69.50 dB
ADJ BS
192 kHz
DL –10.0 dBm
1
2
3
4
RBW 3 kHz
VBW 10 kHz
SWP 5.0 s CENTER 1.900000 GHz SPAN 2.000 MHz
MARKER
239.100 MHz
68.75 dB
ADJ BS
192 kHz
DL –10.0 dBm
1
2
3
4
RBW 3 kHz
VBW 10 kHz
SWP 5.0 s CENTER 240.000 MHz SPAN 2.000 MHz
∗∗∗ Multi Marker List ∗∗∗
No. 1: 239.100 MHz –68.75 dB
No. 2: 239.400 MHz –68.25 dB
No. 3: 240.600 MHz –68.25 dB
No. 4: 240.900 MHz –69.00 dB
∗∗∗ Multi Marker List ∗∗∗
No. 1: 1.899100 GHz –69.50 dB
No. 2: 1.899400 GHz –69.00 dB
No. 3: 1.900600 GHz –69.00 dB
No. 4: 1.900900 GHz –69.50 dB
12
ATT 0 dB
REF –10.0 dBm
10 dB/
Data Sheet P10099EJ4V0DS00
µPC8104GR
RFout OUTPUT IMPEDANCE
3; 162.25 Ω
–87.695 Ω
955.19 fF
1 900.000 000 MHz
MARKER 3
1.9 GHz
RF out
Marker
1. 900 MHz
2. 1.5 GHz
3. 1.9 GHz
3
1
2
START 800.000 000 MHz
STOP 2 000.000 000 MHz
Lo2in INPUT IMPEDANCE
2; 20.184 Ω
–113.66 Ω
843.51 fF
1 660.000 000 MHz
MARKER 2
1.66 GHz
Lo2 in
Marker
1. 900 MHz
2. 1.66 GHz
3. 1.8 GHz
2
1
3
START 800.000 000 MHz
STOP 1 900.000 000 MHz
Data Sheet P10099EJ4V0DS00
13
µPC8104GR
MODout OUTPUT IMPEDANCE
2; 49.244 Ω
13.58 Ω
9.0056 nH
240.000 000 MHz
MARKER 2
240 MHz
MOD out
(IF out)
2
Marker
1
START 50.000 000 MHz
3
1. 100 MHz
2. 240 MHz
3. 400 MHz
STOP 500.000 000 MHz
UP CON. in INPUT IMPEDANCE
2; 262.19 Ω
–394.97 Ω
1.679 pF
240.000 000 MHz
MARKER 2
240 MHz
Up Con in
(IF in)
Marker
2
1
3
START 50.000 000 MHz
14
STOP 500.000 000 MHz
Data Sheet P10099EJ4V0DS00
1. 100 MHz
2. 240 MHz
3. 400 MHz
µPC8104GR
Lo1in INPUT IMPEDANCE
2; 51.727 Ω
–2.0059 Ω
330.5 pF
240.000 000 MHz
MARKER 2
240 MHz
Lo1 in
Marker
2
1. 100 MHz
2. 240 MHz
3. 400 MHz
31
START 50.000 000 MHz
STOP 500.000 000 MHz
TEST CIRCUIT
(fRF = 1.9 GHz)
Lo2
1 000 pF
100 pF
S.G
10 kΩ
VCC
GND
RFout
GND
4
5
6
7
8
9
10
Lo2 in
Up Con in
Q
3
Lo2 in
Up Con in
Q
2
VCC
MOD out
1
Lo1
fLo2 = 1.5 to 1.8 GHz
PIN = –10 dBm
11
I
12
GND
13
I
14
GND
15
GND
16
Power Save
17
Lo1 in
18
VCC
19
100 pF
Lo1 in
20
100
pF
0.1 µ H
Open
S.G
S.P.A
1000 pF
fLo1 = 100 to 400 MHz
PIN = –10 dBm
L
C
I
I
Q
100
pF
fRF = 1.9 GHz
Q
I/Q Signal Generator
L: (Micro Stripline)
C: around 3 pF
f : DC to hundreds kHz
A : 0.5 Vp-p (I, Q only)
V : 1.5 V (I, I, Q, Q)
Data Sheet P10099EJ4V0DS00
15
µPC8104GR
TEST BOARD
VCC (Up Con.)
10 000 pF
P.S.
VCC (MOD)
10 000 pF
10 000 pF
1 000 pF
10 K
Lo2
1 000 pF
100 pF
100 pF
1 000 pF
Lo1
3 pF
100 pF
3 pF
RFout
1 000 pF
100 pF
100 nH
(OPEN)
1 000 pF
Iin
In case of this test board,
the output signal from MOD.
is directly connected to the
up converter input port through
1000 pF, which is DC coupling.
We recommend to insert
a low pass filter between
MOD output and up converter
input port to reject
harmonics of the Lo1 signal
and to avoid saturation
of the up converter.
GND
Qin
10 000 pF
I
16
10 000 pF
Q
Data Sheet P10099EJ4V0DS00
fRF = 1.9 GHz
fLo2 = 1.66 GHz
fLo1 = 240 MHz
µPC8104GR
PACKAGE DIMENSIONS
20 PIN PLASTIC SSOP (225 mil) (UNIT: mm)
20
11
detail of lead end
+7˚
3˚–3˚
1
10
6.7 ± 0.3
6.4 ± 0.2
1.8 MAX.
4.4 ± 0.1
1.5 ± 0.1
1.0 ± 0.2
0.5 ± 0.2
0.15
0.65
+0.10
0.22 –0.05
0.15
+0.10
–0.05
0.575 MAX.
0.10 M
0.1 ± 0.1
NOTE
Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
Data Sheet P10099EJ4V0DS00
17
µPC8104GR
NOTE ON CORRECT USE
(1) Observe precautions for handling because of electrostatic sensitive devices.
(2) Form a ground pattern as wide as possible to keep the minimum ground impedance (to prevent undesired
oscillation).
(3) Keep the track length of the ground pins as short as possible.
(4) Connect a bypass capacitor (e.g. 1 000 pF) to the VCC pin.
(5) I, Q DC offset voltage should be same as the I, Q DC offset voltage (to prevent changing the local leak level with
power save control.)
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered in the following recommended conditions. Other soldering methods and
conditions than the recommended conditions are to be consulted with our sales representatives.
µPC8104GR
Soldering Method
Soldering Conditions
Symbol
Infrared ray reflow
Peak package’s surface temperature: 235 °C or below,
Reflow time: 30 seconds or below (210 °C or higher),
Note
Number of reflow process: 3, Exposure limit : None
IR35-00-3
VPS
Peak package’s surface temperature: 215 °C or below,
Reflow time: 40 seconds or below (200 °C or higher),
Note
Number of reflow process: 3, Exposure limit : None
VP15-00-3
Wave soldering
Solder temperature: 260 °C or below
Flow time: 10 seconds or below,
Note
Number of reflow process: 1, Exposure limit : None
WS60-00-1
Partial heating method
Terminal temperature: 300 °C or below
Flow time: 3 seconds/pin or below,
Note
Exposure limit : None
Note Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25 °C and relative humidity at 65 % or less.
Caution
Apply only a single process at once, except for “Partial heating method”.
For details of recommended soldering conditions for surface mounting, refer to information
document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E)
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
18
Data Sheet P10099EJ4V0DS00
µPC8104GR
[MEMO]
Data Sheet P10099EJ4V0DS00
19
µPC8104GR
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
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rights of third parties by or arising from use of a device described herein or any other liability arising from use
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intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
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of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8