DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT µPC8186K DIRECT QUADRATURE MODULATOR IC FOR PDC SYSTEMS DESCRIPTION The µPC8186K is a silicon microwave monolithic IC developed as quadrature modulator for PDC systems. This IC integrates a pre-mixer for local signals plus a quadrature modulator operating from 893 MHz to 1 453 MHz. This IC is packaged in 24-pin QFN and therefore is suitable for higher density mounting. This low power IC employs NEC’s proprietary bipolar process NESATTM III (fT = 20 GHz) and also has a built-in power save function and can operate 2.7 to 3.6 V supply voltage. Consequenty the µPC8186K can contribute to make RF blocks smaller size, higher performance and lower power consumption. FEATURES • • • • • • Directly modulate in 893 to 1 453 MHz Built-in pre-mixer for local signals External LC filter can be applied between modulator output and pre-mixer input terminal Current consumption: ICC = 34 mA TYP. @VCC = 3.0 V Equipped with power save function 24-pin QFN suitable for higher density mounting APPLICATION • Digital cellular telephone: PDC800 MHz, PDC1.5 GHz ORDERING INFORMATION Part Number µPC8186K-E1 Package 24-pin plastic QFN (4.1 × 5.2 × 0.95 mm) Supplying Form Embossed tape 12 mm wide. Pin 1 is in pull-out direction. QTY 2.5 kpcs/reel. Remark To order evaluation samples, please contact your local NEC sales office. (Part number for sample order: µPC8186K) Caution Electro-static sensitive devices The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. P14896EJ2V0DS00 (2nd edition) Date Published October 2000 N CP(K) Printed in Japan © 2000 µPC8186K INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS AGCout1 20 AGCout2 21 VCC (PP) RFout GND (PP) LO_Hinb LO_Hin LO_Linb LO_Lin (TOP View) 19 18 17 16 15 14 13 12 VPS_AGC 11 VCC (MIX) REG. REG. AGC Cont 2 VCC (AGC) 22 10 GND (MIX) VCC (I/Q) 23 9 LC2 GND (I/Q) 24 8 LC1 4 5 6 7 N.C. VCC (φ ) GND (φ ) Iinb 3 Qin 2 Qinb 1 Iin Phase Shifter Data Sheet P14896EJ2V0DS00 µPC8186K QUADRATURE MODULATOR SERIES Part Number Functions ICC (mA) fLO1in (MHz) fMODout (MHz) 50 to 150 Up-Converter Phase fRFout (MHz) Shifter Package Application µPC8101GR 150 MHz Quad. Mod 15/@ 2.7 V 100 to 300 µPC8104GR RF Up-Converter + IF Quad. Mod 28/@ 3.0 V 100 to 400 900 to 1 900 µPC8105GR 400 MHz Quad. Mod 16/@ 3.0 V 100 to 400 External µPC8110GR 1GHz Direct Quad. Mod 24/@ 3.0 V 800 to 1 000 Direct µPC8125GR RF Up-Converter + IF Quad. Mod + AGC 36/@ 3.0 V 220 to 270 1 800 to 2 000 PHS µPC8126GR 900 MHz Direct Quad. Mod with Offset-Mixer 35/@ 3.0 V 915 to 960 915 to 960 (LO pre-mixer) PDC800 MHz µPC8129GR ×2LO IF Quad. Mod + RF Up-Converter 28/@ 3.0 V 200 to 800 100 to 400 800 to 1900 F/F 20-pin SSOP GSM, (5.72 mm (225)) DCS1800, etc. µPC8158K RF Up-Converter + IF Quad. Mod + AGC 28/@ 3.0 V 100 to 300 800 to 1 500 CR 28-pin QFN µPC8186K Direct Quad. Mod. with Offset-Mixer 34/@ 3.0 V 893 to 1 453 µPC8126K 889 to 960 External F/F 20-pin SSOP CT-2, etc. (5.72 mm (225)) Digital Doubler Comm. + F/F 16-pin SSOP (5.72 mm (225)) PDC800 MHz, 20-pin SSOP (5.72 mm (225)) etc. 28-pin QFN PDC800 M/ 1.5 G 24-pin QFN For outline of the quadrature modulator series, please refer to the application note ‘Usage of µPC8101, 8104, 8105, 8125, 8129’ (Document No. P13251E) and so on. Data Sheet P14896EJ2V0DS00 3 µPC8186K ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Symbol VCC Power Save and AGC Control Pin Applied Voltage VPS/VAGC Conditions Ratings Unit Pins 6, 11, 19, 22, 23 TA = +25°C 5.0 V Pin 12, TA = +25°C 5.0 V 300 mW Note TA = +85°C Power Dissipation PD Operating Ambient Temperature TA –30 to +85 °C Storage Temperature Tstg –55 to +150 °C Note Mounted on double sided copper clad 50 × 50 × 1.6 mm epoxy glass PWB. RECOMMENDED OPERATING RANGE Parameter Test Conditions MIN. TYP. MAX. Unit 2.7 3.0 4.0 V Supply Voltage VCC Pins 6, 11, 19, 22, 23 Power Save Voltage VPS Pin 12 0 – 0.3 V AGC Control Voltage VAGC Pin 12 1.0 – 2.5 V TA –30 +25 +80 °C Pre-Mixer Output Frequency fMIXout 893 – 1 453 MHz Modulator Output Frequency fRFout fMIXout + fI/Qin 893 – 1 453 MHz LO_H Input Frequency fLO_Hin PLO_Hin = −10 dBm 600 – 1 738 MHz LO_L Input Frequency fLO_Lin PLO_Lin = −10 dBm 120 – 285 MHz VI/Qin = 500 mVP-P/pin(MAX) Differential phase input DC – 10 MHz Operating Ambient Temperature I/Q Input Frequency 4 Symbol fI/Qin LO_H Input Power PLO_Hin –13 –10 –7 dBm LO_L Input Power PLO_Lin –13 –10 –7 dBm I/Q Input Amplitude VI/Qin Differential phase input I/Q (DC) = lb/Qb (DC) = VCC/2 – – 500 mVP-P I/Q Offset Voltage I/Q(DC) Ib/Qb(DC) VI/Qin = 700 mVP-P Single end input – 1.6 – V Data Sheet P14896EJ2V0DS00 µPC8186K ELECTRICAL SPECIFICATIONS 1 (BY TEST CIRCUIT 1) TA = +25°C, VCC1 = VCC2 = VCC3 = VCC4 = VCC5 = 3.0 V, unless otherwise specified, VPS/VAGC = 2.5 V (High), I/Q (DC) = lb/Qb (DC) = VCC/2 = 1.5 V, VI/lbin = VQ/Qbin = 500 mVP-P/pin (differential phase input), fI/Qin = 2.625 kHz, π/4DQPSK modulated wave input, Transmission rate: 42 kbps, Filter roll-off rate: α = 0.5, MOD pattern: all zero, fLO_Lin = 180 MHz, PLO_Lin = −10 dBm, fLO_Hin = 768 MHz, PLO_Hin = −10 dBm, fRFout = 948 MHz + fI/Qin Parameter Symbol Conditions MIN. TYP. MAX. Unit No signal input 28 34 41 mA VPS ≤ 0.3 V (Low), No signal input – 0.3 1 µA IAGC VAGC = 3.0 V – 110 – µA Total RF Output Power 1 PRFout1 VAGC = 2.5 V –9.5 –6.5 –4 dBm Total RF Output Power 2 PRFout2 VAGC = 1.0 V – –40 – dBm fLOL = fLO_Lin + fLO_Hin – –40 –30 dBc Modulator + Pre-Mixer Total Circuit Current ICC(TOTAL) Total Circuit Current at Power Save Mode AGC Control Current ICC(PS)TOTAL Local Carrier Leak LOL Image Rejection (Side-band Leak) ImR – –40 –30 dBc I/Q 3rd Order Intermodulation Distortion IM3(I/Q) – –50 –30 dBc AGC Gain Control Range GCR VAGC = 2 V → 1 V 27 32 – dB ∆f = ±50 kHz, MOD Pattern: PN 9 – –65 –60 dBc Adjacent Channel Power Leakage Power Saving Response Time Padj Rise Time TPS(Rise) VPS_AGC (Pin12) = 0 V → 2.5 V – 2 5 µs Fall Time TPS(Fall) VPS_AGC (Pin12) = 2.5 V → 0 V – 2 5 µs I/Q Input Impedance ZI/Q Value between Pins l/lb and Q/Qb – 200 – kΩ I/Q Input Bias Current II/Q Value between Pin I and lb or between Q and Qb – 5 13 µA Error Vector Magnitude (Vector Error) EVM MOD pattern: PN 9 – 1.2 3.0 %rms Noise Floor Level NFL fRFout = 893 MHz fcenter = 885 MHz, SPAN = 0 Hz, RBW = 30 kHz, VBW = 100 kHz, ATT = 0 dB – –134 –131 dBc/Hz Data Sheet P14896EJ2V0DS00 5 µPC8186K ELECTRICAL SPECIFICATIONS 2 (BY TEST CIRCUIT 2) TA = +25°C, VCC1 = VCC2 = VCC3 = VCC4 = VCC5 = 3.0 V, unless otherwise specified, VPS/VAGC = 2.5 V (High), I/Q (DC) = lb/Qb (DC) = VCC/2 = 1.5 V, VI/lbin = VQ/Qbin = 500 mVP-P/pin (differential phase input), fI/Qin = 2.625 kHz, π/4DQPSK modulated wave input, Transmission rate: 42 kbps, Filter roll-off rate: α = 0.5, MOD pattern: all zero, fLO_Lin = 178.05 MHz, PLO_Lin = −10 dBm, fLO_Hin = 1 619.05 MHz, PLO_Hin = −10 dBm, fRFout = 1 441 MHz + fI/Qin Parameter Symbol Conditions MIN. TYP. MAX. Unit No signal input 28 34 41 mA VPS ≤ 0.3 V (Low), No signal input – 0.3 1 µA IAGC VAGC = 3.0 V – 110 – µA Total RF Output Power 1 PRFout1 VAGC = 2.5 V –11 –9 –6 dBm Total RF Output Power 2 PRFout2 VAGC = 1.0 V – –44 – dBm fLOL = fLO_Lin + fLO_Hin – –40 –30 dBc Modulator + Pre-Mixer Total Circuit Current ICC(TOTAL) Total Circuit Current at Power Save Mode AGC Control Current Local Carrier Leak LOL Image Rejection (Side-band Leak) ImR – –40 –29 dBc I/Q 3rd Order Intermodulation Distortion IM3(I/Q) – –50 –30 dBc AGC Gain Control Range GCR VAGC = 2 V → 1 V 27 32 – dB ∆f = ±50 kHz, MOD Pattern: PN 9 – –65 –60 dBc Adjacent Channel Power Leakage Power Saving Response Time 6 ICC(PS)TOTAL Padj Rise Time TPS(Rise) VPS_AGC (Pin12) = 0 V → 2.5 V – 2 5 µs Fall Time TPS(Fall) VPS_AGC (Pin12) = 2.5 V → 0 V – 2 5 µs I/Q Input Impedance ZI/Q Value between Pins l/lb and Q/Qb – 200 – kΩ I/Q Input Bias Current II/Q Value between Pin I and lb or between Q and Qb – 5 13 µA Error Vector Magnitude (Vector Error) EVM MOD pattern: PN 9 – 1.2 3.0 %rms Suprious within the TX Band Psup fLO_L ×8, fLO_L ×8 (Image) – –70 –65 dBc Data Sheet P14896EJ2V0DS00 µPC8186K Note ELECTRICAL SPECIFICATIONS 3 (BY TEST CIRCUIT 2 ) TA = +25°C, VCC1 = VCC2 = VCC3 = VCC4 = VCC5 = 2.8 V, unless otherwise specified, VPS/VAGC = 2.5 V (High), I/Q (DC) = lb/Qb (DC) = VCC/2 = 1.6 V, VI/Qin = 700 mVP-P, VIb/Qbin = 0 VP-P (Single end input), fI/Qin = 2.625 kHz, π/4DQPSK modulated wave input, Transmission rate: 42 kbps, Filter roll-off rate: α = 0.5, MOD pattern: all zero, fLO_Lin = 178.05 MHz, PLO_Lin = −10 dBm, fLO_Hin = 1619.05 MHz, PLO_Hin = −10 dBm, fRFout = 1441 MHz + fI/Qin Parameter Symbol Conditions MIN. TYP. MAX. Unit Modulator + Pre-Mixer Total RF Output Power PRFout VAGC = 2.5 V – –12.5 – dBm Error Vector Magnitude (Vector Error) EVM MOD pattern: PN 9 – 1.5 – %rms ∆f = ±50 kHz, MOD Pattern: PN 9 – –65 –60 dBc Adjacent Channel Power Leakage Padj Note Resistor value between pins 20 and 21: 1.3 kΩ Data Sheet P14896EJ2V0DS00 7 µPC8186K PIN EXPLANATIONS Supply Voltage (V) Pin Voltage Iin VCC/2 – Input for I signal. This input impedance is 200 kΩ. In case of that I/Q input signals are differential, amplitude of the signal is 500 mVP-P max. 2 Iinb VCC/2 – Input for I signal. This input impedance is 200 kΩ. In case of that I/Q input signals are single ended, VCC/2 biased DC signal should be input. In case of the I/Q input signals are differential, amplitude of the signal is 500 mVP-P max. 3 Qinb VCC/2 – Input for Q signal. This input impedance is 200 kΩ. In case of that I/Q input signals are differential, amplitude of the signal is 500 mVP-P max. 4 Qin VCC/2 – Input for I signal. This input impedance is 200 kΩ. In case of that I/Q input signals are single ended, VCC/2 biased DC signal should be input. In case of the I/Q input signals are differential, amplitude of the signal is 500 mVP-P max. 5 N.C. – – This pin is not connected to internal circuit. This pin should be opened or grounded. ––––––––––––––––– Pin No. Symbol 1 Function and Applications 1 2 3 4 6 VCC(φ) 2.7 to 4.0 – Supply voltage pin for modulator circuit. ––––––––––––––––– 7 GND(φ) 0 – Ground pin for modulator circuit. This pin should be grounded with minimum inductance. Form the ground pattern as widely as possible to minimize ground impedance. ––––––––––––––––– 8 LC1 – 2.64 9 LC2 – 2.64 External inductor and capacitor can supress harmonics spurious of LO frequency. LC value should be determined according to LO input frequency and suppression level. Note Pin Voltages are measured at VCC = 3.0 V. 8 Internal Equivalent Circuit Note (V) Data Sheet P14896EJ2V0DS00 External 8 9 µPC8186K Pin No. 10 Symbol GND (MIX) Supply Voltage (V) Pin Voltage 0 – Function and Applications Ground pin for pre-mixer circuit. This pin should be grounded with minimum inductance. Form the ground pattern as widely as possible to minimize ground impedance. 11 VCC (MIX) 2.7 to 4.0 – Supply voltage pin for pre-mixer circuit. 12 VPS_AGC VPS/VAGC – Power save control pin for modulator, pre-mixer and AGC circuits. This pin also assigned as gain control pin for AGC circuits. Operation status with applied voltages are as follows. 13 LO_Lin – 1.87 VPS/VAGC (V) State 0 to 0.3 OFF (Sleep Mode) 1 to 2.5 On (AGC Mode) Low-band local signal input for premixer. This pin must be coupled with DC cut capacitor 330 pF and should be terminated with 51Ω resistor. 14 LO_Linb – 1.87 Bypass pin of pre-mixer’s low-band local input. This pin should be decoupled with 330 pF capacitor. 15 LO_Hin – 1.93 High-band local signal input for premixer. This pin must be coupled with DC cut capacitor 330 pF and should be terminated with 51Ω resistor. 16 LO_Hinb – 1.93 17 GND (PP) 0 – 18 19 RFout VCC (PP) – 2.7 to 4.0 Internal Equivalent Circuit Note (V) 2.07 – ––––––––––––––––– ––––––––––––––––– REG. 12 AGC Cont 13 14 15 16 Bypass pin of pre-mixer’s high-band local input. This pin should be decoupled with 330 pF capacitor. Ground pin for RF output buffer. This pin should be grounded with minimum inductance. Form the ground pattern as widely as possible to minimize ground impedance. RF output pin. This pin is emitter follower which is low impedance output port. This pin can be easily matched to 50Ω impedance using external coupling capacitor. Supply voltage pin for RF output buffer. ––––––––––––––––– External 18 ––––––––––––––––– Note Pin Voltages are measured at VCC = 3.0 V. Data Sheet P14896EJ2V0DS00 9 µPC8186K Supply Voltage (V) Pin Voltage AGCout1 – 2.99 AGCout2 – 2.99 Pin No. Symbol 20 21 Function and Applications Internal Equivalent Circuit Note (V) Due to the external inductor to output line of internal AGC amplifier, suprious can be suppressed. External 20 22 VCC (AGC) 2.7 to 4.0 – Supply voltage pin for internal AGC amplifier circuit. 23 VCC (I/Q) 2.7 to 4.0 – Supply voltage pin for I/Q mixer circuit. 24 GND (I/Q) 0 – Ground pin for modulator circuit. This pin should be grounded with minimum inductance. Note Pin Voltages are measured at VCC = 3.0 V. 10 Data Sheet P14896EJ2V0DS00 ––––––––––––––––– ––––––––––––––––– ––––––––––––––––– 21 µPC8186K TEST CIRCUIT 1 (For fRFout = 948 MHz + fI/Qin) BPF1 Signal Generator BPF2 Signal Generator LO_H BPF3 33 pF Spectrum Analyzer 51 Ω 33 pF 19 18 17 33 pF 16 LO_L 51 Ω 330 pF 15 14 330 pF 13 10 nF VPS_AGC 22 nH 20 12 REG. 3.9 kΩ 0.1 µ //1 000 p //100 pF VCC 21 11 REG. 22 nH AGC Cont 22 10 23 9 0.1 µ //1 000 p //100 pF VCC 8.2 nH 24 8 Phase Shifter 3 pF 1 2 3 4 5 6 VCC 100 pF 100 pF 100 pF 100 pF 7 0.1 µ //1 000 p//100 pF I/Q Signal Generator Data Sheet P14896EJ2V0DS00 11 µPC8186K TEST CIRCUIT 2 (For fRFout = 1 441 MHz + fI/Qin) BPF1 Signal Generator BPF2 Signal Generator LO_H BPF3 33 pF Spectrum Analyzer 51 Ω 33 pF 19 18 17 33 pF 16 LO_L 51 Ω 330 pF 15 14 330 pF 13 10 nF VPS_AGC 8.2 nH 20 12 REG. 1.3 kΩ 0.1 µ //1 000 p //100 pF VCC 21 11 REG. 8.2 nH AGC Cont 22 10 23 9 0.1 µ //1 000 p //100 pF VCC 4.7 nH Phase Shifter 24 1 2 3 4 5 6 VCC 100 pF 100 pF 100 pF 100 pF I/Q Signal Generator 12 Data Sheet P14896EJ2V0DS00 8 2 pF 7 0.1 µ //1 000 p//100 pF µPC8186K PACKAGE DIMENSIONS 24-PIN PLASTIC QFN (UNIT: mm) 5.2 ± 0.2 Bottom View 5.1 0.22 0.45±0.1 Pin 1 4.2 ± 0.2 4.1 Pin 24 0.5 0.95 ± 0.1 0.15 4 – C0.5 Data Sheet P14896EJ2V0DS00 13 µPC8186K NOTES ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent undesired oscillation). (3) Keep the track length of the ground pins as short as possible. (4) Connect a bypass capacitor to the VCC pin. RECOMMENDED SOLDERING CONDITIONS This product should be soldered under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Soldering Method Soldering Conditions Recommended Condition Symbol Infrared Reflow Package peak temperature: 235°C or below Time: 30 seconds or less (at 210°C) Note Count: 3, Exposure limit: None IR35-00-3 VPS Package peak temperature: 215°C or below Time: 40 seconds or less (at 200°C) Note Count: 3, Exposure limit: None VP15-00-3 Partial Heating Pin temperature: 300°C Time: 3 seconds or less (per side of device) Note Exposure limit: None – Note After opening the dry pack, keep it in a place below 25°C and 65% RH for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E). 14 Data Sheet P14896EJ2V0DS00 µPC8186K [MEMO] Data Sheet P14896EJ2V0DS00 15 µPC8186K NESAT (NEC Silicon Advanced Technology) is a trademark of NEC Corporation. • The information in this document is current as of October, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. 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