DATA SHEET MOS INTEGRATED CIRCUIT µPD168101 MONOLITHIC QUAD H-BRIDGE DRIVER CIRCUIT DESCRIPTION The µPD168101 is monolithic quad H-bridge driver LSI which uses power MOSFETs in the output stages. By using the MOS process, this driver IC has substantially improved the voltage loss of the output stage and power consumption as compared with conventional driver circuits using bipolar transistors. By eliminating the charge pump circuit, the current during power-OFF is drastically decreased. In addition, a low-voltage malfunction prevention circuit is also provided that prevents the IC from malfunctioning when the supply voltage drops. As the package, a 24-pin plastic TSSOP is adopted to enable the creation of compact, slim application sets. This driver IC can drive two stepping motor at the same time, and is ideal for driving stepping motors in the lens of a camera. It is the best for lens drive drivers, such as a digital camera and a video camera. Moreover, since the input of two terminals is respectively owned to H bridge 1 circuit, a maximum of four loads, such as DC motor, can be driven simultaneously. FEATURES Four H bridge circuits employing power MOSFETs Low current consumption by eliminating charge pump VM pin current when power-OFF: 10 µA MAX. VDD pin current: 10 µA MAX. Input logic frequency: 100 kHz 3-V power supply Minimum operating supply voltage: 2.5 V Low voltage malfunction prevention circuit 24-pin plastic TSSOP (5.72 mm (225)) ORDERING INFORMATION Part Number µPD168101MA-6A5 Package 24-pin plastic TSSOP (5.72 mm (225)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14846EJ1V0DS00 (1st edition) Date Published April 2001 N CP(K) Printed in Japan © 2001 µPD168101 ABSOLUTE MAXIMUM RATINGS (TA = 25°°C) When mounted on a glass epoxy board (10 cm × 10 cm × 1 mm, 15% copper foil) Parameter Symbol Condition Rating Unit VDD −0.5 to +6.0 V VM −0.5 to +6.0 V Input voltage VIN −0.5 to VDD + 0.5 V Output terminal voltage VOUT 6.2 V Control block supply voltage IM(DC) DC ±0.35 A/ch IM(pulse) PW ≤ 10 ms, Duty ≤ 5% ±0.7 A/ch Output current Power consumption PT 0.7 W Peak junction temperature TCH(MAX) 150 °C Storage temperature range Tstg −55 to +150 °C RECOMMENDED OPERATING CONDITIONS When mounted on a glass epoxy board (10 cm × 10 cm × 1 mm, 15% copper foil) Parameter Symbol Condition MIN. TYP. MAX. Unit VDD 2.5 5.5 V VM 2.7 5.5 V −0.25 +0.25 A 100 kHz 85 °C 125 °C Control block supply voltage 2 Output current IM(DC) DC Operating frequency fIN IN terminal Operating temperature range TA Peak junction temperature TCH(MAX) −10 Data Sheet S14846EJ1V0DS µPD168101 CHARACTERISTICS (Unless otherwise specified, VDD = VM = 3 V, TA = 25°°C) Parameter Symbol Condition MIN. TYP. MAX. Unit Off state VM pin current IM(OFF) All control terminal = 0 V Per VM terminal 10 µA VDD terminal current at the time of standby IDD(ST) All control terminal = 0 V 10 µA VDD terminal current at the time of operation IDD 1 mA High level input current IIH VIN = VDD 0.06 mA Low level input current IIL VIN = 0 V Input pull down resistance RIND High level input voltage VIH Low level input voltage µA −1.0 50 200 kΩ 2.5 V ≤ VDD ≤ 5.5 V 0.7 × VDD VDD+0.3 V VIL 2.5 V ≤ VDD ≤ 5.5 V −0.3 0.3 × VDD V H-bridge ON resistance RON 2.7 V ≤ VM = VDD ≤ 5.5 V IM = 0.25 A, Upper + lower 1.1 Ω Low voltage malfunction prevention circuit operating voltage VDDS1 VM = 5 V, −10°C ≤ TA ≤ +85°C 0.8 2.5 V VDDS2 VM = 3 V, −10°C ≤ TA ≤ +85°C 0.65 2.5 V H bridge output turn-on time 1 tON1 H bridge output turn-on time 2 tON2 H bridge output turn-off time tOFF H bridge output rise time tr H bridge output fall time tf 0.7 µs 1.0 RM = 20 Ω, Figure 1 tON1: turn-on time from all control = 0 V tON2: turn-on time at operation 0.7 2.0 µs 0.2 0.5 µs 0.3 1.0 µs 0.07 0.2 µs Remarks 1. As for thermal shutdown circuit (TSD), junction temperature operates above 150°C. At the time of over thermal detection, current supply is stopped by making all output terminals into high impedance. In addition, thermal shutdown circuit does not operate at the time of standby. 2. A low voltage malfunction operation prevention circuit operates, if a voltage power supply (VDD) becomes less than 2.5 V. All output terminals be high impedance at the time of UVLO operation. Data Sheet S14846EJ1V0DS 3 µPD168101 Figure 1. Switching time condition (1) IN2 = Low-level 100% 90% VIN1 10% tON tOFF tr tf OUT1A→OUT1B 90% 90% IM 10% Hi-Z 10% Hi-Z (2) IN2 = High-level 100% 90% VIN1 10% tOFF tON tf tr OUT1B→OUT1A OUT1B→OUT1A 90% 90% IM 10% 10% brake FUNCTION TABLE The logic of each channel is as follows Channel 1 Channel 2 IN1 IN2 OUT1A OUT1B IN3 IN4 OUT2A L L Z Z L L Z Z L H L H L H L H H L H L H L H L H H L L H H L L IN5 IN6 OUT3A OUT3B IN7 IN8 OUT4A OUT4B L L Z Z L L Z Z L H L H L H L H H L H L H L H L H H L L H H L L Channel 3 Channel 4 H: High-level, L: Low-level, Z: High impedance When all control pin is low-level, IC becomes stand-by state and current consumption is reduced. 4 OUT2B Data Sheet S14846EJ1V0DS µPD168101 PIN CONNECTION VM1 1 24 VDD OUT1A 2 23 OUT1B PGND 3 22 PGND OUT2A 4 21 OUT2B OUT3A 5 20 VM23 PGND 6 19 OUT3B OUT4A 7 18 PGND VM4 8 17 OUT4B IN1 9 16 IN8 IN2 10 15 IN7 IN3 11 14 IN6 IN4 12 13 IN5 Pin No. Pin name Pin function 1 VM1 2 OUT1A Output terminal 3 PGND Ground terminal 4 OUT2A Output terminal 5 OUT3A Output terminal 6 PGND Ground terminal 7 OUT4A Output terminal 8 VM4 Output block supply voltage input terminal 9 IN1 Control terminal (channel 1) 10 IN2 Control terminal (channel 1) 11 IN3 Control terminal (channel 2) 12 IN4 Control terminal (channel 2) 13 IN5 Control terminal (channel 3) 14 IN6 Control terminal (channel 3) 15 IN7 Control terminal (channel 4) 16 IN8 Control terminal (channel 4) 17 OUT4B Output terminal 18 PGND Ground terminal 19 OUT3B Output terminal 20 VM23 21 OUT2B Output terminal 22 PGND Ground terminal 23 OUT1B Output terminal 24 VDD Output block supply voltage input terminal Output block supply voltage input terminal Control block supply voltage input terminal Data Sheet S14846EJ1V0DS 5 µPD168101 BLOCK DIAGRAM 24 VDD TSD UVLO VM1 1 IN1 1A 9 IN2 Control circuit (1) H-bridge (1) 2 1B 10 23 PGND 3 VM2, 3 20 IN3 2A 11 IN4 Control circuit (2) H-bridge (2) 4 2B 12 21 PGND IN5 3A 13 IN6 Control circuit (3) H-bridge (3) 22 5 3B 14 19 PGND 6 VM4 8 IN7 4A 15 IN8 Control circuit (4) H-bridge (4) 7 4B 16 17 PGND 18 Cautions 1. The terminal which has more than one should connect not only one terminal but all terminals. 2. Pull down resistance is connected to the input terminal. It’s not necessary that the input terminal is connected when it isn’t used. 3. The motor part power supply terminals VM1, VM23, and VM4 are separated inside, and can impress an individually different power supply. 4. The motor part power supply terminal of the output which is not used should impress voltage of recommended operation condition, or should connect to GND. In addition, if voltage is impressed to VM terminal even when an input is open, VM terminal current (10 µAMAX) is flow at the time of standby. 6 Data Sheet S14846EJ1V0DS µPD168101 TYPICAL CHARACTERISTICS PT vs. TA characteristics IDD, IDD(ST) vs. VDD characteristics 1 0.8 VDD pin current IDD, IDD(ST) (mA) Total power dissipation PT (W) 1 0.7 W 0.6 178°C/W 0.4 0.2 0 –10 10 30 50 70 90 TA = 25°C 0.8 IDD 0.6 0.4 0.2 IDD(ST) 0 100 IM vs. VM characteristics 3 4 5 6 IIH, IIL vs. VDD characteristics 30 60 TA = 25°C TA = 25°C 25 Input current IH, IIL ( µ A) OFF state VM pin current IM(OFF) ( µ A) 2 Control block supply voltage VDD (V) Ambient temperature TA (°C) 20 15 10 50 IIH 40 30 20 10 5 IIL 0 1 2 3 4 5 0 6 Output block supply voltage VM (V) 1 2 3 4 5 VIH, VIL vs. VDD characteristics 5 200 TA = 25°C TA = 25°C Input voltage VIH, VIL (V) 150 100 50 0 6 Control block supply voltage VDD (V) RIND vs. VDD characteristics Input pull-down resistance RIND (kΩ) 1 1 2 3 4 5 6 4 3 VIH, VIL 2 1 0 Control block supply voltage VDD (V) 1 2 3 4 5 6 Control block supply voltage VDD (V) Data Sheet S14846EJ1V0DS 7 µPD168101 Detect voltage at low voltage characteristics RON vs. VM characteristics 1.5 2 VDD (L→H) H-bridge ON resistance RON (Ω) Detect voltage VDDS (V) TA = 25°C 1.5 VDD (H→L) 1 0.5 0 1 2 3 4 5 TA = 25°C IM = 0.25 A 1 0.5 0 6 Output block supply voltage VM (V) H-bridge ON resistance RON (Ω) VM = 2.7 V IM = 0.25 A 1 0.5 0 20 40 60 80 0.4 100 H-bridge output rise time tr (µ s) H-bridge output fall time tf (µ s) tr 0.4 0.2 tf 6 Output block supply voltage VM (V) 8 tOFF 0 1 2 3 4 5 6 Output block supply voltage VM (V) 0.6 5 tON2 0.8 0.8 4 tON1 1.2 TA = 25°C RM = 20 Ω 3 6 1.6 tr, tf vs. VM characteristics 2 5 TA = 25°C RM = 20 Ω 1 1 4 3 2 Ambient temperature TA (°C) 0 2 tON1, tON2, tOFF vs. VM characteristics H-bridge output turn-on time tON1, tON2 (µ s) H-birdge output turn-off time tOFF (µs) RON vs. TA characteristics 1.5 0 –20 1 Output block supply voltage VM (V) Data Sheet S14846EJ1V0DS 1 to 10 µ F 1 to 10 µ F Battery VM4 VM2, 3 VM1 TSD 1A VDD H bridge 1 IN3 IN4 IN5 IN6 2B PGND Control circuit 3A Level Shift circuit H bridge 3 3B Motor 2 PGND 4A IN7 IN8 Motor 1 2A H bridge 2 IN2 CPU 1B PGND UVLO IN1 STANDARD CONNECTION EXAMPLE Data Sheet S14846EJ1V0DS This circuit diagram is an example of connection, and is not a thing aiming at mass production. VDD = VM = 2.7 V to 5.5 V DC/DC CONVERTER H bridge 4 4B PGND 9 µPD168101 GND µPD168101 PACKAGE DIMENSION 24-PIN PLASTIC TSSOP (5.72 mm (225)) 13 24 detail of lead end F G R P L S 12 1 E A H A' I J S D M N K C M S B NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 6.65±0.10 A' 6.5±0.1 B 0.575 C 0.5 (T.P.) D E 0.22±0.05 0.1±0.05 F 1.2 MAX. G 1.0±0.05 H I J K L M 6.4±0.1 4.4±0.1 1.0±0.1 0.17±0.025 0.5 0.10 N 0.08 P 3°+5° −3° R 0.25 S 0.6±0.15 P24MA-50-6A5 10 Data Sheet S14846EJ1V0DS µPD168101 RECOMMENDED SOLDERING CONDITIONS Solder this product under the following recommended conditions. For soldering methods and conditions other than those recommended, consult NEC. For details of the recommended soldering conditions, refer to information document “Semiconductor Device Mounting Technology Manual”. Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C; Time: 30 secs. max. (210°C min.); Number of times: 3 times max; Number of day: none; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2Wt% max.) is recommended. IR35-00-3 VPS Package peak temperature: 215°C; Time: 40 secs. max. (200°C min.); Number of times: 3 times max.; Number of day: none; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt% max.) is recommended. VP15-00-3 Wave soldering Package peak temperature: 260°C; Time: 10 secs. max.; Preheating temperature: 120°C max.; Number of times: once; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt% max.) is recommended. WS60-00-1 Caution Do not use two or more soldering methods in combination. Data Sheet S14846EJ1V0DS 11 µPD168101 [MEMO] 12 Data Sheet S14846EJ1V0DS µPD168101 [MEMO] Data Sheet S14846EJ1V0DS 13 µPD168101 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 14 Data Sheet S14846EJ1V0DS µPD168101 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 Data Sheet S14846EJ1V0DS 15 µPD168101 • The information in this document is current as of March, 2001. The information is subject to change without notice. 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