NEC UPD178006A

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD178004A, 178006A, 178016A, 178018A
8-BIT SINGLE-CHIP MICROCONTROLLERS
The µ PD178004A, 178006A, 178016A and 178018A are 8-bit single-chip CMOS microcontrollers that incorporate
hardware for digital tuning systems.
The CPU uses the 78K/0 architecture, which makes it easy to implement high-speed access to internal memory
and control of peripheral hardware. Also, the instructions used are the high-speed 78K/0 instructions, suitable for
system control.
The rich assortment of peripheral hardware includes an input/output port, 8-bit timer, A/D converter, serial interface,
power-ON clear circuits, as well as a pre-scaler for digital tuning, a PLL frequency synthesizer and a frequency counter.
The µ PD178P018A, one-time PROM or EPROM versions which can be operated in the same supply voltage range
as for the mask ROM versions, and various development tools, are also available.
For more information on functions, refer to the following User’s Manuals. Be sure to read them when
designing.
µ PD178018A Subseries User’s Manual: to be prepared
78K/0 Series User’s Manual Instruction: U12326E
FEATURES
• Internal high-capacity ROM and RAM
Items
Program Memory
Product Name
ROM
µPD178004A
32 Kbytes
µPD178006A
48 Kbytes
µPD178016A
µPD178018A
Data Memory
Internal High-Speed RAM
1 024 bytes
Buffer RAM
32 bytes
Internal Expanded RAM
Not provided
2 048 bytes
60 Kbytes
• Instruction Cycle: 0.44 µ s (4.5-MHz crystal oscillator used)
• Large array of on-chip peripheral hardware
General-purpose input/output port, A/D converter, serial interface, timer, frequency counter, power-ON clear
circuits.
• On-chip hardware for a PLL frequency synthesizer.
Dual modulus pre-scaler, programmable divider, phase comparator, charge pump.
• Vector interrupt sources: 17
• Supply Voltage: VDD = 4.5 to 5.5 V (during PLL operation)
VDD = 3.5 to 5.5 V (during CPU operation, when the system clock is fX/2 or lower)
VDD = 4.5 to 5.5 V (during CPU operation, when the system clock is fX)
The information in this document is subject to change without notice.
Document No. U12641EJ1V0DS00 (1st Edition)
Date Published July 1997 N
Printed in Japan
©
1997
µPD178004A, 178006A, 178016A, 178018A
APPLICATIONS
Car stereo, home stereo systems.
ORDERING INFORMATION
Part Number
µPD178004AGC-×××-3B9
µPD178006AGC-×××-3B9
µPD178016AGC-×××-3B9
µPD178018AGC-×××-3B9
Remark
Package
80-pin plastic QFP
80-pin plastic QFP
80-pin plastic QFP
80-pin plastic QFP
(14
(14
(14
(14
× 14 mm, 0.65-mm pitch)
× 14 mm, 0.65-mm pitch)
× 14 mm, 0.65-mm pitch)
× 14 mm, 0.65-mm pitch)
××× denotes the ROM code number. Also, the ROM code number becomes E×× when the I2C bus is used.
µ PD178018A SUBSERIES AND µPD178003 SUBSERIES EXPANSION
µ PD178018A Subseries
80 pins
µ PD178P018A Note
80 pins
PROM : 60 KB
RAM : 3 KB
µ PD178018A
ROM : 60 KB
RAM : 3 KB
80 pins
µPD178016A
ROM : 48 KB
RAM : 3 KB
80 pins
µ PD178006A
ROM : 48 KB
RAM : 1 KB
80 pins
µ PD178004A
ROM : 32 KB
RAM : 1 KB
80 pins
µPD178003 Note
ROM : 24 KB
RAM : 0.5 KB
80 pins
µPD178002 Note
ROM : 16 KB
RAM : 0.5 KB
µ PD178003 Subseries
Note
2
Under development
µPD178004A, 178006A, 178016A, 178018A
OUTLINE OF FUNCTION
(1/2)
µPD178004A
Product name
µ PD178006A
µPD178016A
µ PD178018A
Item
Internal
memory
ROM (ROM configuration)
32 Kbytes
(mask ROM)
High-speed RAM
1 024 bytes
Buffer RAM
32 bytes
Expansion RAM
Not provided
48 Kbytes
(mask ROM)
60 Kbytes
(mask ROM)
2 048 bytes
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Instruction cycle
With variable instruction execution time function
0.44 µ s/0.88 µs/1.78 µs/3.56 µ s/7.11 µs/14.22 µs (with 4.5-MHz crystal resonator)
Instruction set
•
•
•
•
I/O port
Total
CMOS input
CMOS I/O
N-ch open-drain I/O
N-ch open-drain output
A/D converter
8-bit resolution × 6 channels
Serial interface
• 3-wire/SBI/2-wire/I2 C bus Note mode selectable
: 1 channel
• 3-wire serial I/O mode
(with automatic transfer/receive function of up to 32 byte) : 1 channel
Timer
•
•
•
•
Buzzer (BEEP) output
1.5 kHz, 3 kHz, 6 kHz
Vectored
interrupt
Source
Maskable
Internal: 8, external: 7
Non-maskable
Internal: 1
Software
Internal: 1
Test input
Note
16-bit operation
Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjustment, etc.
: 62 pins
: 1 pin
: 54 pins
: 4 pins
: 3 pins
Basic timer (timer carry FF (10 Hz))
:
8-bit timer/event counter
:
8-bit timer (D/A converter: PWM output) :
Watchdog timer
:
1
2
1
1
channel
channels
channel
channel
Internal: 1
When using the I2 C bus mode (including when this mode is implemented by program without using the
peripheral hardware), consult your local NEC sales representative when you place an order for mask.
3
µPD178004A, 178006A, 178016A, 178018A
(2/2)
Product name
µ PD178004A
µPD178006A
µ PD178016A
µPD178018A
Item
PLL frequency
synthesizer
Division mode
Two types
• Direct division mode (VCOL pin)
• Pulse swallow mode (VCOH and VCOL pins)
Reference frequency
7 types selectable by program (1, 3, 5, 9, 10, 25, 50 kHz)
Charge pump
Error out output: 2 (EO0 and EO1 pins Note 1)
Phase comparator
Unlock detectable by program
Frequency counter
• Frequency measurement
• AMIFC pin: for 450-kHz count
• FMIFC pin: for 450-kHz/10.7-MHz count
D/A converter (PWM output)
8-/9-bit resolution × 3 channels (shared by 8-bit timer)
Standby function
• HALT mode
• STOP mode
Reset
• Reset by RESET pin
• Internal reset by watchdog timer
• Reset by power-ON clear circuit (3-value detection)
• Detection of less than 4.5 V Note 2 (CPU clock: fX)
• Detection of less than 3.5 V Note 2 (CPU clock: fX/2 or less and on power application)
• Detection of less than 2.5 V Note 2 (in STOP mode)
Power supply voltage
• VDD = 4.5 to 5.5 V (with PLL operating)
• VDD = 3.5 to 5.5 V (with CPU operating, CPU clock: fX/2 or less)
• VDD = 4.5 to 5.5 V (with CPU operating, CPU clock: fX)
Package
• 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
Notes 1. The EO1 pin can be set to high impedance for the µ PD178016A and 178018A.
The following shows an application example.
µ PD178016A
µ PD178018A
EO0
LPF
VCO
To Mixer
EO1
VCOH
VCOL
LPF : Low path filter
VCO : Voltage controlled oscillator
• To lock to a target frequency at high speed
Setting the EO0 and EO1 pins to error out output improves the output current potential and LPF
voltage control potential.
• Normal state
Setting only the EO0 pin to error out output maintains the LPF stable.
2. These voltage values are maximum values. Reset is actually executed at a voltage lower than these
values.
4
µPD178004A, 178006A, 178016A, 178018A
TABLE OF CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................ 6
2. BLOCK DIAGRAM ........................................................................................................................... 8
3. PIN FUNCTION LIST ........................................................................................................................ 9
3.1 PORT PINS ................................................................................................................................ 9
3.2 PINS OTHER THAN PORT PINS ............................................................................................ 10
3.3 INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ..... 11
4. MEMORY SPACE .......................................................................................................................... 14
5. PERIPHERAL HARDWARE FUNCTION FEATURES .................................................................. 15
5.1 PORTS ..................................................................................................................................... 15
5.2 CLOCK GENERATOR ............................................................................................................ 16
5.3 TIMER ...................................................................................................................................... 16
5.4 BUZZER OUTPUT CONTROL CIRCUIT ................................................................................ 18
5.5 A/D CONVERTER ................................................................................................................... 19
5.6 SERIAL INTERFACES ............................................................................................................ 19
5.7 PLL FREQUENCY SYNTHESIZER ........................................................................................ 21
5.8 FREQUENCY COUNTER ........................................................................................................ 22
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS .................................................................... 23
6.1 INTERRUPT FUNCTIONS ...................................................................................................... 23
6.2 TEST FUNCTION .................................................................................................................... 26
7. STANDBY FUNCTION ................................................................................................................... 27
8. RESET FUNCTION ........................................................................................................................ 27
9. INSTRUCTION SET ....................................................................................................................... 28
10. ELECTRICAL SPECIFICATIONS .................................................................................................. 30
11. PACKAGE DRAWINGS ................................................................................................................. 46
12. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 47
APPENDIX A. DIFFERENCES BETWEEN µPD178018A AND µPD178018 SUBSERIES ............... 48
APPENDIX B. DEVELOPMENT TOOLS ............................................................................................ 49
APPENDIX C. RELATED DOCUMENTS ........................................................................................... 51
5
µPD178004A, 178006A, 178016A, 178018A
1. PIN CONFIGURATION (TOP VIEW)
RESET
VDD
REGOSC
X1
X2
GND
REGCPU
P06/INTP6
P05/INTP5
P04/INTP4
P03/INTP3
P02/INTP2
P01/INTP1
P00/INTP0
P125
P124
P123
P122
P121
P120
• 80-PIN PLASTIC QFP (14 × 14 mm, 0.65 mm pitch)
µ PD178004AGC-×××-3B9, 178006AGC-×××-3B9
µ PD178016AGC-×××-3B9, 178018AGC-×××-3B9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
1
59
2
58
3
57
4
56
5
55
6
54
7
53
8
52
9
51
10
50
11
49
12
48
13
47
14
46
15
45
16
44
17
43
18
42
19
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P37
P36/BEEP
P35
P34/TI2
P33/TI1
P32
P31
P30
P67
P66
P65
P64
P63
P62
P61
P60
P57
P56
P55
P54
GNDPORT
VDDPORT
P43
P44
P45
P46
P47
AMIFC
FMIFC
VDDPLL
VCOH
VCOL
GNDPLL
EO0
EO1
IC
P50
P51
P52
P53
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P132/PWM0
P133/PWM1
P134/PWM2
P40
P41
P42
Cautions 1.
2.
3.
4.
6
Connect
Connect
Connect
Connect
the Internally Connected (IC) pin to GND directly.
VDDPORT and VDD PLL pins to V DD.
the GNDPORT and GNDPLL pins to GND.
each of the REGOSC and REGCPU pins to GND via a 0.1-µF capacitor.
µPD178004A, 178006A, 178016A, 178018A
AMIFC
:
AN10 to AN15 :
BEEP
:
BUSY
:
EO0, EO1
:
FMIFC
:
GND
:
GNDPLL
:
GNDPORT
:
IC
:
INTP0 to INTP6 :
P00 to P06
:
P10 to P15
:
P20 to P27
:
P30 to P37
:
P40 to P47
:
P50 to P57
:
P60 to P67
:
P120 to P125 :
AM Intermediate Frequency Counter Input
A/D Converter Input
Buzzer Output
Busy Output
Error Out Output
FM Intermediate Frequency Counter Input
Ground
PLL Ground
Port Ground
Internally Connected
Interrupt Inputs
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 12
P132 to P134 :
PWM0 to PWM2 :
REGCPU
:
REGOSC
:
RESET
:
SB0, SB1
:
SCK0, SCK1 :
SCL
:
SDA0, SDA1 :
SI0, SI1
:
SO0, SO1
:
STB
:
TI1, TI2
:
VCOL, VCOH :
VDD
:
VDDPLL
:
VDDPORT
:
X1, X2
:
Port 13
PWM Output
Regulator for CPU Power Supply
Regulator for Oscillator Circuit
Reset Input
Serial Data Bus Input/Output
Serial Clock Input/Output
Serial Clock Input/Output
Serial Data Input/Output
Serial Data Input
Serial Data Output
Strobe Output
Timer Clock Input
Local Oscillator Input
Power Supply
PLL Power Supply
Port Power Supply
Crystal Oscillator Connection
7
µPD178004A, 178006A, 178016A, 178018A
2. BLOCK DIAGRAM
TI1/P33
8-bit TIMER/
EVENT COUNTER 1
PORT 0
TI2/P34
8-bit TIMER/
EVENT COUNTER 2
8-bit TIMER 3
WATCHDOG TIMER
BASIC TIMER
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
78K/0
CPU
CORE
SERIAL
INTERFACE 0
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
SERIAL
INTERFACE 1
INTP0/P00 to
INTP6/P06
BEEP/P36
RESET
X1
X2
VDDPORT
GNDPORT
VDD
REGOSC
REGCPU
GND
6
7
PORT 1
6
P10 to P15
PORT 2
8
P20 to P27
PORT 3
8
P30 to P37
PORT 4
8
P40 to P47
PORT 5
8
P50 to P57
PORT 6
8
P60 to P67
PORT 12
6
P120 to P125
PORT 13
3
P132 to P134
D/A CONVERTER
(PWM)
3
PWM0/P132 to
PWM2/P134
A/D CONVERTER
INTERRUPT
CONTROL
BUZZER OUTPUT
FREQUENCY
COUNTER
AMIFC
FMIFC
PLL
EO0
EO1
VCOL
VCOH
RESET
SYSTEM
CONTROL
CPU
PERIPHERAL
PLL
VOLTAGE
REGULATOR
VOLTAGE
REGULATOR
VOSC
VCPU
Remark The internal ROM and RAM capacities depend on the version.
8
P01 to P06
ROM
RAM
ANI0/P10 to
ANI5/P15
P00
6
VDDPLL
GNDPLL
IC
µPD178004A, 178006A, 178016A, 178018A
3. PIN FUNCTION LIST
3.1 PORT PINS
Pin Name
P00
I/O
Input
P01 to P06 I/O
P10 to P15 I/O
P20
I/O
Function
Port 0.
7-bit input/output port.
Input only
After Reset Alternate Function
Input
Input/output mode can be specified bit-wise. Input
Port 1.
6-bit input/output port.
Input/output mode can be specified bit-wise.
Input
Port 2.
Input
8-bit input/output port.
Input/output mode can be specified bit-wise.
P21
INTP0
INTP1 to INTP6
ANI0 to ANI5
SI1
SO1
P22
SCK1
P23
STB
P24
BUSY
P25
SI0/SB0/SDA0
P26
SO0/SB1/SDA1
P27
SCK0/SCL
P30 to P32 I/O
Port 3.
Input
P33
8-bit input/output port.
Input/output mode can be specified bit-wise.
—
TI1
P34
TI2
P35
—
P36
BEEP
P37
—
P40 to P47 I/O
Port 4.
8-bit input/output port.
Input/output mode can be specified in 8-bit units.
Test input flag (KRIF) is set to 1 by falling edge detection.
Input
—
P50 to P57 I/O
Port 5.
8-bit input/output port.
Input/output mode can be specified bit-wise.
Input
—
P60 to P63 I/O
Port 6.
8-bit input/output port.
Input/output mode can be
specified bit-wise.
Input
—
Input
—
P64 to P67
Middle voltage N-ch open drain
input/output port.
LEDs can be driven directly.
P120 to
P125
I/O
Port 12.
6-bit input/output port.
Input/output mode can be specified bit-wise.
P132 to
P134
Output
Port 13.
3-bit output port.
N-ch open-drain output port.
—
PWM0 to
PWM2
9
µPD178004A, 178006A, 178016A, 178018A
3.2 PINS OTHER THAN PORT PINS
Pin Name
I/O
Function
After Reset Alternate Function
INTP0 to
INTP6
Input
External maskable interrupt inputs with specifiable valid edges (rising
edge, falling edge, both rising and falling edges).
Input
P00 to P06
SI0
Input
Serial interface serial data input
Input
P25/SB0/SDA0
SI1
P20
SO0
Output
Serial interface serial data output
Input
SO1
P26/SB1/SDA1
P21
SB0
I/O
Serial interface serial data input/output
Input
P25/SI0/SDA0
SB1
P26/SO0/SDA1
SDA0
P25/SI0/SB0
SDA1
P26/SO0/SB1
SCK0
I/O
Serial interface serial clock input/output
Input
P27/SCL
SCK1
P22
SCL
P27/SCK0
STB
Output
Serial interface automatic transmit/receive strobe output
Input
P23
BUSY
Input
Serial interface automatic transmit/receive busy input
Input
P24
TI1
Input
External count clock input to 8-bit timer (TM1)
Input
P33
TI2
External count clock input to 8-bit timer (TM2)
BEEP
Buzzer output
Input
P36
ANI0 to ANI5 Input
A/D converter analog input
Input
P10 to P15
PWM0 to PWM2
Output
PWM output
—
P132 to P134
EO0, EO1
Output
Error out output from charge pump of the PLL frequency synthesizer
—
—
VCOL
Input
Inputs PLL local band frequency (In HF, MF mode)
—
—
VCOH
Input
Inputs PLL local band frequency (In VHF mode)
—
—
AMIFC
Input
Inputs AM intermediate frequency counter
—
—
FMIFC
Input
Inputs FM intermediate frequency counter
—
—
RESET
Input
System reset input
—
—
X1
Input
System clock oscillation resonator connection
—
—
X2
—
—
—
REGOSC
—
Oscillation regulator. Connected to GND via a 0.1-µF capacitor.
—
—
REGCPU
—
CPU power supply regulator. Connected to GND via a 0.1-µ F capacitor.
—
—
VDD
—
Positive power supply
—
—
GND
—
Ground
—
—
VDDPORT
—
Positive power supply for port block
—
—
GNDPORT
—
Ground for port block
—
—
VDDPLL Note
—
Positive power supply for PLL
—
—
GNDPLL Note
—
Ground for PLL
—
—
IC
—
Internally connected. Connected to GND or GNDPORT.
—
—
Note
10
Output
P34
Connect a capacitor of approximately 1 000 pF between the V DDPLL pin and GNDPLL pin.
µPD178004A, 178006A, 178016A, 178018A
3.3 INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins.
Refer to Figure 3-1 for the configuration of the input/output circuit of each type.
Table 3-1. I/O Circuit Type of Each Circuit
Pin Name
I/O Circuit Type
I/O
Recommended Connections of Unused Pins
P00/INTP0
2
Input
Connected to GND or GNDPORT
P01/INTP1 to P06/INTP6
8
I/O
P10/ANI0 to P15/ANI5
11-A
Set in general-purpose input port mode by software and
individually connected to VDD, VDDPORT, GND, or GNDPORT
via resistor.
P20/SI1
8
P21/SO1
5
P22/SCK1
8
P23/STB
5
P24/BUSY
8
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
10
P30 to P32
5
P33/TI1, P34/TI2
8
P35
P36/BEEP
P37
5
P40 to P47
5-G
P50 to P57
5
P60 to P63
13-D
P64 to P67
5
Output
Set to low-level output by software and open
P120 to P125
P132/PWM0 to P134/PWM2
19
EO0
DTS-EO1
Open
Note
EO1
DTS-EO3
VCOL, VCOH
DTS-AMP
Input
—
—
Set to disabled status by software and open
AMIFC, FMIFC
IC
Note
Connected to GND or GNDPORT directly
For the µ PD178004A and 178006A, the I/O circuit type is DTS-EO1.
11
µPD178004A, 178006A, 178016A, 178018A
Figure 3-1. Pin Input/Output Circuit of List (1/2)
Type 2
Type 8
VDD
data
IN
P-ch
IN/OUT
output
disable
N-ch
Schmitt-Triggered Input with
Hysteresis Characteristics
Type 10
Type 5
VDD
VDD
data
data
P-ch
P-ch
IN/OUT
IN/OUT
output
disable
open-drain
output disable
N-ch
N-ch
input
enable
Type 5-G
Type 11-A
VDD
VDD
data
data
P-ch
P-ch
IN/OUT
IN/OUT
output
disable
N-ch
P-ch
comparator
output
disable
+
_
N-ch
N-ch
VREF (Threshold voltage)
input
enable
Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports,
and should be read as V DDPORT and GNDPORT, respectively.
12
µPD178004A, 178006A, 178016A, 178018A
Figure 3-1. Pin Input/Output Circuit of List (2/2)
Type 13-D
Type DTS-EO3
IN/OUT
VDDPLL
data
output disable
N-ch
DW
P-ch
VDD
OUT
RD
UP
P-ch
N-ch
GNDPLL
Middle-Voltage Input Buffer
Type DTS-AMP
Type 19
VDDPLL
OUT
N-ch
IN
Type DTS-EO1
VDDPLL
DW
P-ch
OUT
UP
N-ch
GNDPLL
Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports,
and should be read as VDD PORT and GNDPORT, respectively.
13
µPD178004A, 178006A, 178016A, 178018A
4. MEMORY SPACE
Figure 4-1 shows the µPD178004A, 178006A, 178016A, and 178018A memory map.
Figure 4-1. Memory Map
FFFFH
Special Function Registers
(SFR) 256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
FABFH
General-Purpose
Registers
32 × 8 bits
Use Prohibited
F800H
F7FFH
Internal Expanded RAM
2 048 × 8 bits
Internal High-Speed
RAM
1 024 × 8 bits
F000H
EFFFH
FB00H
FAFFH
Use Prohibited Note 2
nnnnH + 1
Use Prohibited
Data Memory
Space
FAE0H
FADFH
nnnnH
Buffer RAM 32 × 8 bits
Program Area
FAC0H
FABFH
1000H
0FFFH
CALLF Entry Area
0800H
07FFH
Use Prohibited
Program Area
0080H
007FH
nnnnH + 1
nnnnH
Program Memory
Space
CALLT Table Area
Internal ROM
0040H
003FH
Note 3
Vectored Table Area
0000H
0000H
Notes 1. Available only for µ PD178016A and 178018A
2. The µ PD178018A does not contain this use prohibited area.
3. The internal ROM capacity depends on the version (see the table below).
Corresponding Product
Name
14
Internal ROM Last Address
nnnnH
µPD178004A
7FFFH
µPD178006A, 178016A
BFFFH
µPD178018A
EFFFH
Note 1
µPD178004A, 178006A, 178016A, 178018A
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 PORTS
The following 3 types of I/O ports are available.
• CMOS input (P00)
: 1
• CMOS input/output (P01 to P06, port 1 to port 5, P64 to P67, port 12) : 54
• N-channel open-drain input/output (P60 to P63)
: 4
• N-ch open drain output (Port 13)
: 3
Total
: 62
Table 5-1. Port Functions
Name
Pin Name
Function
Port 0
P00
Dedicated input port pins
P01 to P06
Input/output port pins. Input/output specifiable bit-wise.
Port 1
P10 to P15
Input/output port pins. Input/output specifiable bit-wise.
Port 2
P20 to P27
Input/output port pins. Input/output specifiable bit-wise.
Port 3
P30 to P37
Input/output port pins. Input/output specifiable bit-wise.
Port 4
P40 to P47
Input/output port pins. Input/output specifiable in 8-bit units.
Test flag (KRIF) is set to 1 by falling edge detection.
Port 5
P50 to P57
Input/output port pins. Input/output specifiable bit-wise.
Port 6
P60 to P63
N-channel open-drain input/output port pins. Input/output specifiable bit-wise.
LED direct drive capability.
P64 to P67
Input/output port pins. Input/output specifiable bit-wise.
Port 12
P120 to P125
Input/output port pins. Input/output specifiable bit-wise.
Port 13
P132 to P134
N-ch open drain output port.
15
µPD178004A, 178006A, 178016A, 178018A
5.2 CLOCK GENERATOR
The instruction execution time can be changed as follows.
0.44 µs/0.88 µ s/1.78 µs/3.56 µ s/7.11 µs/14.22 µs (@ 4.5-MHz crystal oscillator with system clock.)
Figure 5-1. Clock Generator Block Diagram
Clock to the PLL
frequency synthesizer,
basic timer and buzzer
output control circuit.
Prescaler
X1
System
Clock
Oscillator
X2
fX
Selector
Scaler
STOP
fXX
Clock to peripheral
hardware other than
the above.
Prescaler
fXX fXX fXX
2 22 23
fXX
24
fX
2
Selector
Standby
Control
Circuit
Wait Control
Circuit
To INTP0
Sampling Clock
5.3 TIMER
The µPD178004A, 178006A, 178016A, and 178018A incorporate 5 channels of the timer.
• Basic timer
: 1 channel
• 8-bit timer/event counter
: 2 channels
• 8-bit timer (D/A converter) Note
: 1 channel
• Watchdog timer
: 1 channel
Note
Used is shared with the 8/9-bit resolution × 3-channel D/A converter (PWM output).
Figure 5-2. Basic Timer Block Diagram
4.5 MHz
16
Divider
INTTMC
CPU Clock
(fCPU)
µPD178004A, 178006A, 178016A, 178018A
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal Bus
INTTM1
8-Bit Compare
Register (CR10)
8-Bit Compare
Register (CR20)
Selector
Match
Match
INTTM2
fxx/2 to fxx/2 9
fx/2 11
Selector
8-Bit Timer
Register 1 (TM1)
Selector
TI1/P33
Clear
Clear
fxx/2 to fxx/2 9
fx/2 11
8-Bit Timer
Register 2 (TM2)
Selector
Selector
TI2/P34
Internal Bus
Figure 5-4. 8-Bit Timer (D/A Converter) Block Diagram
Internal Bus
INTPWM
PWM Mode
Select Register
PWM Duty Setting Block
PWM Data Register 2 Note
(PWMR2)
PWM Data Register 1
(PWMR1)
PWM Data Register 0
(PWMR0)
Comparator
Comparator
Comparator
PWM PWM PWM
0SE 1SE 2SE
4.5 MHz
Clock
Generation
Block
Clear
Circuit
fPWM
b8
9-Bit Binary Counter
b0
Output Select
Block
P132/PWM0
Output Select
Block
P133/PWM1
Output Select
Block
P134/PWM2
PWM PWM PWM PWM PWM
BIT CK0 MD ST RES
PWM Control Register
Internal Bus
Note
The PWM data register 2 (PWMR2) is multiplexed with the PWM timer register (PWMTMR).
17
µPD178004A, 178006A, 178016A, 178018A
Figure 5-5. Watchdog Timer Block Diagram
f xx
23
Prescaler
f xx
24
f xx
25
f xx
26
f xx
27
f xx
28
f xx
29
f xx
2 11
INTWDT
Maskable
Interrupt Request
Selector
Control
Circuit
8-Bit Counter
Reset
INTWDT
Non-Maskable
Interrupt Request
5.4 BUZZER OUTPUT CONTROL CIRCUIT
The clock with the following frequency can be output as a buzzer output.
• 1.5 kHz/3 kHz/6 kHz (@ 4.5-MHz crystal oscillator with system clock)
Figure 5-6. Buzzer Output Control Circuit Block Diagram
Selector
1.5 kHz
3 kHz
6 kHz
BEEP/P36
3
TCL27 TCL26 TCL25
P36
Output Latch
Port Mode Register 3
Timer Clock Select Register 2
Internal Bus
18
PM36
µPD178004A, 178006A, 178016A, 178018A
5.5 A/D CONVERTER
An A/D converter of 8-bit resolution × 6 channels is incorporated.
The following two types of the A/D conversion operation start-up methods are available.
• Hardware start
• Software start
Figure 5-7. A/D Converter Block Diagram
Resistor String
Sample & Hold Circuit
ANI0/P10
ANI1/P11
VDD
Voltage Comparator
ANI2/P12
Selector
ANI3/P13
Tap
Selector
ANI4/P14
ANI5/P15
Succesive Approximation
Register (SAR)
INTP3/P03
Edge
Detection
Circuit
GND
Control
Circuit
INTAD
INTP3
A/D Conversion
Result Register (ADCR)
Internal Bus
5.6 SERIAL INTERFACES
2 channels of the clocked serial interface are incorporated.
• Serial interface channel 0
• Serial interface channel 1
Table 5-2. Types and Functions of Serial Interface
Function
3-wire serial I/O mode
Serial Interface Channel 0
(MSB/LSB first switchable)
Serial Interface Channel 1
(MSB/LSB first switchable)
—
(MSB/LSB first switchable)
3-wire serial I/O mode with automatic
transmission/ reception function
SBI (serial bus interface) mode
(MSB first)
—
2-wire serial I/O mode
(MSB first)
—
I2C Bus Mode
(MSB first)
—
19
µPD178004A, 178006A, 178016A, 178018A
Figure 5-8. Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/SDA0/P25
Serial I/O Shift
Register 0 (SIO0)
Selector
Output
Latch
SO0/SB1/SDA1/P26
Selector
Busy/Acknowledge
Output Circuit
Bus Release/Command/
Acknowledge Detection
Circuit
Interrupt Request
Signal Generator
Serial Clock Counter
SCK0/SCL/P27
fXX/2 to fXX/2 8
Serial Clock
Control Circuit
Selector
Figure 5-9. Serial Interface Channel 1 Block Diagram
Internal Bus
Automatic Data Transmit/
Receive Address Pointer
(ADTP)
Buffer RAM
Automatic Data
Transmit/Receive
Interval Specification
Register (ADTI)
Match
SI1/P20
Serial I/O Shift Register 1 (SIO1)
SO1/P21
5-Bit Counter
STB/P23
BUSY/P24
SCK1/P22
Handshake
Control
Circuit
Serial Counter
Interrupt Request
Signal Generator
INTCSI1
f XX/2 to f XX/2 8
Serial Clock Control Circuit
20
Selector
INTCSI0
µPD178004A, 178006A, 178016A, 178018A
5.7 PLL FREQUENCY SYNTHESIZER
Figure 5-10. PLL Frequency Synthesizer Block Diagram
Internal Bus
PWM
Data Transfer Register
PLL Mode
Select Register
PLL PLL
MD1 MD0
2
PLL Data Register
(PLLRL, PLLRH, PLLR0)
2
fN
VCOH
Mixer
Input Select
Block
Programmable
Divider
VCOL
Voltage
Control
Generator
Note
PLL
NS0
4.5 MHz
fr
EO1
Phase
Comparator
( φ -DET)
Reference
Frequency
Generator
Charge
Pump
EO0
Unlock
FF
4
Note
Low pass
Filter
PLL PLL PLL PLL
RF3 RF2 RF1 RF0
PLL Reference
Mode Register
Note
PLL Unlock
FF Judge
Register
Internal Bus
EOC EOC
ON1 ON0
PLL
UL0
EO Select
Register
External circuit
Cautions 1. Be sure to set EOCON0 to 0.
2. For the µPD178004A and 178006A, do not set EOCON1 to 1.
21
µPD178004A, 178006A, 178016A, 178018A
5.8 FREQUENCY COUNTER
Figure 5-11. Frequency Counter Block Diagram
2
FMIFC
Input Select
Block
Gate Time
Control Block
IF Counter
Register
(IFC)
Block
Start/Stop
Control Block
AMIFC
2
IFC IFC IFC IFC
MD1 MD0 CK1 CK0
IF Counter
Mode Select
Register
22
IFC
JG0
IF Counter
Gate Judge
Register
Internal Bus
IFC IFC
ST RES
IF Counter
Control
Register
µPD178004A, 178006A, 178016A, 178018A
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 INTERRUPT FUNCTIONS
Interrupt functions include three types and 17 sources, as shown below.
• Non-maskable: 1
• Maskable
: 15
• Software
: 1
Table 6-1. Interrupt Source List
Note 1
Interrupt Source
Interrupt
Type
Default
Priority
Name
Nonmaskable
—
INTWDT
Watchdog timer overflow
(watchdog timer mode 1 selected)
Maskable
0
INTWDT
Watchdog timer overflow
(interval timer mode selected)
1
INTP0
Pin input edge detection
2
Software
Trigger
Internal/
External
Basic
Vector Table Configuration
Address
Type Note 2
Internal
0004H
(A)
(B)
0006H
(C)
INTP1
0008H
(D)
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTP6
0012H
8
INTCSI0
End of serial interface channel 0 transfer
9
INTCSI1
End of serial interface channel 1 transfer
0016H
10
INTTMC
Generation of match signal of basic timer
0018H
11
INTPWM
Generation of match signal of 8-bit timer
001AH
12
INTTM1
Generation of match signal of 8-bit timer/
event counter 1
001CH
13
INTTM2
Generation of match signal of 8-bit timer/
event counter 2
001EH
14
INTAD
End of conversion by A/D converter
0020H
—
BRK
BRK instruction execution
External
Internal
Internal
0014H
003EH
(B)
(E)
Notes 1. The default priority is a priority order when two or more maskable interrupts are generated
simultaneously. 0 is the highest order and 14, the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.
23
µPD178004A, 178006A, 178016A, 178018A
Figure 6-1. Interrupt Function Basic Configuration (1/2)
(A) Internal non-maskable interrupt
Internal Bus
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
Standby Release
Signal
(B) Internal maskable interrupt
Internal Bus
MK
Interrupt
Request
PR
IE
ISP
Priority Control
Circuit
IF
Vector Table
Address
Generator
Standby Release
Signal
(C) External maskable interrupt (INTP0)
Internal Bus
Interrupt
Request
Sampling Clock
Select Register
(SCS)
External Interrupt
Mode Register
(INTM0)
Sampling
Clock
Edge
Detection
Circuit
MK
IF
IE
PR
Priority Control
Circuit
ISP
Vector Table
Address
Generator
Standby Release
Signal
24
µPD178004A, 178006A, 178016A, 178018A
Figure 6-1. Interrupt Function Basic Configuration (2/2)
(D) External maskable interrupt (except INTP0)
Internal Bus
External Interrupt
Mode Register
(INTM0, INTM1)
Interrupt
Request
Edge Detection
Circuit
MK
PR
IE
ISP
Priority Control
Circuit
IF
Vector Table
Address
Generator
Standby Release
Signal
(E) Software interrupt
Internal Bus
Interrupt
Request
IF :
IE :
ISP :
MK :
PR :
Priority Control
Circuit
Vector Table
Address
Generator
Interrupt request flag
Interrupt enable flag
In-service priority flag
Interrupt mask flag
Priority specification flag
25
µPD178004A, 178006A, 178016A, 178018A
6.2 TEST FUNCTION
A test function with a single source is provided, as shown in Table 6-2.
Table 6-2. Test Input Source List
Test Input Source
Internal/External
Name
INTPT4
Trigger
Port 4 falling edge detection
External
Figure 6-2. Test Function Basic Configuration
Internal Bus
MK
Test Input
IF : Test input flag
MK : Test mask flag
26
IF
Standby Release
Signal
µPD178004A, 178006A, 178016A, 178018A
7. STANDBY FUNCTION
There are the following two standby functions to reduce the system power consumption.
• HALT mode : The CPU operating clock is stopped.
The average consumption current can be reduced by intermittent operation in combination with
the normal operating mode.
• STOP mode : The system clock oscillation is stopped. All operations by the system clock are stopped and
current consumption can be considerably reduced.
Figure 7-1. Stand-by Function
System Clock Operation
Interrupt
Request
HALT
Instruction
STOP
Instruction
Interrupt
Request
STOP Mode
(System clock
oscillation stopped)
HALT Mode
(Clock supply to CPU is
stopped, oscillation
continued)
8. RESET FUNCTION
There are the following three reset methods.
• External reset input by RESET pin
• Internal reset by watchdog timer runaway time detection
• Internal reset by Power-On Clear (POC).
27
µPD178004A, 178006A, 178016A, 178018A
9. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,
ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second
Operand
[HL + byte]
#byte
First
Operand
A
r Note
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B]
$addr16
1
None
[HL + C]
A
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
r
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
sfr
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
ROR
ROL
RORC
ROLC
INC
DEC
DBNZ
B,C
!addr16
DBNZ
INC
DEC
MOV
PSW
MOV
MOV
PUSH
POP
MOV
ROR4
ROL4
[DE]
[HL]
[HL + byte]
[HL + B]
[HL + C]
X
MULU
C
DIVUW
Note
28
MOV
Except r = A
µPD178004A, 178006A, 178016A, 178018A
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
First Operand
#word
AX
ADDW
SUBW
CMPW
rp
MOVW
AX
rp Note
MOVW
XCHW
sfrp
MOVW
saddrp
!addr16
MOVW
MOVW
SP
None
MOVW
MOVW Note
INCW
DECW
PUSH
POP
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
MOVW
SP
Note
MOVW
MOVW
Only when rp = BC, DE or HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
First Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
A.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
sfr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
PSW.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
[HL].bit
MOV1
BT
BF
BTCLR
SET1
CLR1
CY
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
SET1
CLR1
NOT1
(4) Call instruction/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
First Operand
Basic instruction
AX
BR
!addr16
CALL
BR
Compound
instruction
!addr11
CALLF
[addr5]
CALLT
$addr16
BR, BC, BNC
BZ, BNZ
BT, BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
29
µPD178004A, 178006A, 178016A, 178018A
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Parameter
Symbol
Power supply voltage
VDD
Input voltage
VI1
Excluding P60 to P63
VI2
P60 to P63
Output voltage
Test Conditions
Rating
Unit
–0.3 to + 7.0
V
–0.3 to VDD + 0.3
V
–0.3 to +16
V
–0.3 to VDD + 0.3
V
N-ch Open-drain
VO
Output withstand
voltage
VBDS
P132 to P134
N-ch Open-drain
16
V
Analog input voltage
VAN
P10 to P15
Analog input pin
–0.3 to VDD + 0.3
V
Output current high
I OH
1 pin
–10
mA
P01 to P06, P30 to P37, P56, P57, P60 to P67,
–15
mA
–15
mA
Peak value
15
mA
Effective value
7.5
mA
P120 to P125 total
P10 to P15, P20 to P27, P40 to P47, P50 to P55,
P132 to P134 total
Output current low
I OL Note
1 pin
Operating ambient
temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Note
Effective value should be calculated as follows: [Effective value] = [Peak value] × √duty
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single
parameter even momentarily. That is, the absolute maximum ratings are rated values at which
the product is on the verge of suffering physical damage, and therefore the product must be
used under conditions which ensure that the absolute maximum ratings are not exceeded.
Remark The characteristics of alternate-function pins and port pins are the same unless specified otherwise.
RECOMMENDED SUPPLY VOLTAGE RANGES (T A = –40 to +85 °C)
Parameter
Power supply voltage
Symbol
Test Conditions
TYP.
MAX.
Unit
VDD1
During CPU operation and PLL operation.
4.5
5.5
V
VDD2
While the CPU is operating and the PLL is stopped.
Cycle Time: TCY ≥ 0.89 µ s
3.5
5.5
V
VDD3
While the CPU is operating and the PLL is stopped.
Cycle Time: TCY = 0.44 µs
4.5
5.5
V
Remark T CY: Cycle Time (Minimum instruction execution time)
30
MIN.
µPD178004A, 178006A, 178016A, 178018A
DC CHARACTERISTICS (TA = –40 to +85 °C, V DD = 3.5 to 5.5 V)
(1/3)
Parameter
Symbol
Input voltage high
VIH1
P10
P30
P40
P64
VIH2
P00 to P06, P20, P22,
P24 to P27, P33, P34,
RESET
VIH3
P60 to P63
(N-ch Open-drain)
VIL1
P10
P30
P40
P64
VIL2
P00 to P06, P20, P22,
P24 to P27, P33, P34,
RESET
VIL3
P60 to P63
(N-ch Open-drain)
Input voltage low
Output voltage high
Output voltage low
Test Conditions
to
to
to
to
to
to
to
to
P15,
P32,
P47,
P67,
P15,
P32,
P47,
P67,
P21, P23,
P35 to P37,
P50 to P57,
P120 to P125
VOL1
VOL2
TYP.
MAX.
Unit
0.7 VDD
VDD
V
0.85 VDD
VDD
V
0.7 VDD
15
V
0
0.3 VDD
V
0
0.15 VDD
V
4.5 V ≤ VDD ≤ 5.5 V
0
0.3 VDD
V
3.5 V ≤ VDD < 4.5 V
0
0.2 VDD
V
4.5 V ≤ VDD ≤ 5.5 V
IOH = –1 mA
VDD – 1.0
V
3.5 V ≤ VDD < 4.5 V
IOH = –100 µA
VDD – 0.5
V
P21, P23,
P35 to P37,
P50 to P57,
P120 to P125
VOH1
MIN.
P50 to P57, P60 to P63
VDD = 4.5 to 5.5 V,
IOH = 15 mA
P01 to P06, P10 to P15,
P20 to P27, P30 to P37,
P40 to P47, P64 to P67,
P120 to P125,
P132 to P134
VDD = 4.5 to 5.5 V,
IOL = 1.6 mA
SB0, SB1, SCK0
VDD = 4.5 to 5.5 V,
open-drain pulled-up
(R = 1 KΩ)
0.4
2.0
V
0.4
V
0.2 VDD
V
Remark The characteristics of alternate-function pins and port pins are the same unless specified otherwise.
31
µPD178004A, 178006A, 178016A, 178018A
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V)
Parameter
Input leakage
current high
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
VIN = VDD
3
µA
VIN = 15 V
80
µA
VIN = 0 V
–3
µA
–3 Note
µA
I LIH1
P00 to P06,
P20 to P27,
P40 to P47,
P64 to P67,
RESET
I LIH2
P60 to P63
I LIL1
P00 to P06,
P20 to P27,
P40 to P47,
P64 to P67,
RESET
I LIL2
P60 to P63
Output leakage
current high
ILOH
P132 to P134
VOUT = 15 V
3
µA
Output leakage
current low
ILOL
P132 to P134
VOUT = 0 V
–3
µA
Output off leak
current
I LOF
EO0, EO1
VOUT = VDD,
VOUT = 0 V
±1
µA
Input leakage
current low
Note
P10 to P15,
P30 to P37,
P50 to P57,
P120 to P125,
(2/3)
P10 to P15,
P30 to P37,
P50 to P57,
P120 to P125,
When an input instruction is executed, the low-level input leakage current for P60 to P63 becomes –200
µ A (MAX.) only in one clock cycle (at no wait). It remains at –3 µ A (MAX.) for other than an input instruction.
Remark The characteristics of alternate-function pins and port pins are the same unless specified otherwise.
REFERENCE CHARACTERISTICS (TA = 25 °C, VDD = 5 V)
Parameter
Symbol
Output current high
IOH1
Test Conditions
EO0
IOL1
EO0
EO1 (EOCON0 = 0)
32
MIN.
VOUT = VDD – 1 V
EO1 (EOCON0 = 0)
Output current low
(1/2)
TYP.
–4
–1.8
VOUT = 1 V
Unit
mA
mA
6
3.5
MAX.
mA
mA
µPD178004A, 178006A, 178016A, 178018A
DC CHARACTERISTICS (TA = –40 to +85 °C, V DD = 3.5 to 5.5 V)
Parameter
Power Supply
Note 1
Symbol
IDD1
Current
IDD2
IDD3
IDD4
Data Hold
VDR1
Power Supply
VDR2
Voltage
Data Hold
Power Supply Current
(3/3)
Test Conditions
While the CPU is operating
and the PLL is stopped
fX = 4.5 MHz operation
While the CPU is operating
and the PLL is stopped
HALT Mode
Pin X1 sine wave
input VIN = VDD.
fX = 4.5 MHz operation
When the crystal is oscillating
TYP.
MAX.
Unit
2.5
15
mA
TCY = 0.44 µs Note 3
VDD = 4.5 to 5.5 V
4.0
27
mA
TCY = 0.89 µs Note 2
0.7
1.5
mA
TCY = 0.44 µs Note 3
VDD = 4.5 to 5.5 V
1.0
2.0
mA
TCY = 0.89 µs
MIN.
Note 2
TCY = 0.44 µs
4.5
5.5
V
TCY = 0.89 µs
3.5
5.5
V
2.6
5.5
V
2
4
µA
2
30
µA
VDR3
When the crystal oscillator is stopped
When power off by Power On Clear is detected
IDR1
While the crystal oscillator
IDR2
is stopped
TA = 25 °C, V DD = 5V
Notes 1. The port current is not included.
2. When the Processor Clock Control register (PCC) is set at 00H, and the Oscillation Mode Select
register (OSMS) is set at 00H.
3. When PCC is set at 00H and OSMS is set at 01H.
Remarks 1. TCY: Cycle Time (Minimum instruction execution time)
2. fx: System clock oscillator frequency.
REFERENCE CHARACTERISTICS (TA = 25 °C, VDD = 5 V)
Parameter
Power Supply
Current
Symbol
IDD5
(2/2)
Test Conditions
During CPU operation
and PLL operation.
TCY = 0.44 µs
MIN.
Note
TYP.
7
MAX.
Unit
mA
VCOH pin sine wave
input
fIN = 130 MHz,
VIN = 0.15 Vp-p
Note
When the Processor Clock Control register (PCC) is set at 00H, and the Oscillation Mode Select register
(OSMS) is set at 01H.
Remark TCY: Cycle Time (Minimum instruction execution time)
33
µPD178004A, 178006A, 178016A, 178018A
AC CHARACTERISTICS
(1) BASIC OPERATION (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V)
Parameter
Symbol
Cycle time
TCY
Test Conditions
f XX = fX/2
Note 1
MIN.
, f X = 4.5 MHz operation
TYP.
MAX.
Unit
0.89
14.22
µs
(Minimum instruction
f XX = f
,
4.5 ≤ V DD ≤ 5.5 V
0.44
7.11
µs
execution time)
f X = 4.5 MHz operation
3.5 ≤ V DD < 4.5 V
0.89
7.11
µs
4.5 ≤ VDD ≤ 5.5 V
0
4.5
MHz
3.5 V ≤ V DD ≤ 4.5 V
0
275
kHz
TI1, TI2 input
fTI
frequency
X Note 2
TI1, TI2 input high/
tTIH ,
4.5 ≤ VDD ≤ 5.5 V
111
ns
low-level width
tTIL
3.5 V ≤ V DD ≤ 4.5 V
1.8
µs
µs
sam Note 3
Interrupt input high/
TINTH,
INTP0
low-level width
TINTL
8/f
INTP1 to INTP6
RESET low level
width
t RSL
10
µs
10
µs
Notes 1. When oscillation mode selection (OSMS) register is set at 00H.
2. When OSMS is set at 01H.
3. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection
of fsam is possible between f XX/2 N, fXX /32, fXX/64 and f XX/128 (when N = 0 to 4).
Remarks 1. f XX: System clock frequency (f X or fX/2)
2. f X: System clock oscillation frequency
60
60
10
10
Operation
Guaranteed
Range
2.0
1.0
0.5
0.4
Operation
Guaranteed
Range
2.0
1.0
0.5
0.4
0
0
1
2
3
4
5
Power Supply Voltage VDD [V]
34
T CY vs V DD (At F XX = F X system clock operation)
Cycle Time T CY [µ s]
Cycle Time T CY [µ s]
T CY vs V DD (At F XX = F X/2 system clock operation)
6
1
2
3
4
5
Power Supply Voltage VDD [V]
6
µPD178004A, 178006A, 178016A, 178018A
(2) SERIAL INTERFACE (T A = –40 to +85 °C, VDD = 3.5 to 5.5 V)
(a) Serial interface channel 0
(i) 3-wire serial I/O mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
SI0 setup time (to SCK0↑)
SI0 hold time (from SCK0↑)
SO0 output delay time from SCK0↓
Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
1 600
ns
tKH1,
4.5 V ≤ VDD ≤ 5.5 V
tKCY1/2 – 50
ns
t KL1
3.5 V ≤ VDD < 4.5 V
tKCY1/2 – 100
ns
tSIK1
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
150
ns
400
ns
tKCY1
tKSI1
t KSO1
C = 100 pF
Note
300
ns
MAX.
Unit
C is the load capacitance of SO0 output line.
(ii) 3-wire serial I/O mode (SCK0 ... external clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
Symbol
Test Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
1 600
ns
tKH2,
4.5 V ≤ VDD ≤ 5.5 V
400
ns
t KL2
3.5 V ≤ VDD < 4.5 V
800
ns
tKCY2
SI0 setup time (to SCK0↑)
tSIK2
100
ns
SI0 hold time (from SCK0↑)
tKSI2
400
ns
SO0 output delay time from SCK0↓
t KSO2
SCK0 at rising or falling edge time
t R2, tF2
Note
C = 100 pF Note
300
ns
1 000
ns
C is the load capacitance of SO0 output line.
35
µPD178004A, 178006A, 178016A, 178018A
(iii) SBI mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
SB0, SB1 setup time (to SCK0↑)
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
3 200
ns
t KH3,
4.5 V ≤ VDD ≤ 5.5 V
tKCY3/2 – 50
ns
t KL3
3.5 V ≤ VDD < 4.5 V
tKCY3/2 – 150
ns
t SIK3
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
300
ns
t KCY3/2
ns
t KCY3
SB0, SB1 hold time (from SCK0↑)
t KSI3
SB0, SB1 output delay time from
tKSO3
SCK0↓
4.5 V ≤ VDD ≤ 5.5 V
0
250
ns
C = 100 pF Note 3.5 V ≤ VDD < 4.5 V
0
1 000
ns
R = 1 kΩ
SB0, SB1↓ from SCK0↑
t KSB
t KCY3
ns
SCK0↓ from SB0, SB1↓
t SBK
t KCY3
ns
SB0, SB1 high-level width
t SBH
t KCY3
ns
SB0, SB1 low-level width
tSBL
t KCY3
ns
Note R and C are the load resistance and load capacitance of SB0 and SB1 output line.
(iv) SBI mode (SCK0 ... external clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
SB0, SB1 setup time (to SCK0↑)
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
3 200
ns
t KH4,
4.5 V ≤ VDD ≤ 5.5 V
400
ns
t KL4
3.5 V ≤ VDD < 4.5 V
1 600
ns
t SIK4
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
300
ns
tKCY4/2
ns
t KCY4
SB0, SB1 hold time (from SCK0↑)
t KSI4
SB0, SB1 output delay time from
tKSO4
SCK0↓
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
C = 100 pF Note 3.5 V ≤ VDD < 4.5 V
0
1 000
ns
R = 1 kΩ
SB0, SB1↓ from SCK0↑
t KSB
tKCY4
ns
SCK0↓ from SB0, SB1↓
t SBK
tKCY4
ns
SB0, SB1 high-level width
t SBH
tKCY4
ns
SB0, SB1 low-level width
tSBL
tKCY4
ns
SCK0 at rising or falling edge time
Note
36
tR4, t F4
R and C are the load resistance and load capacitance of SB0 and SB1 output line.
1 000
ns
µPD178004A, 178006A, 178016A, 178018A
(v) 2-wire serial I/O mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY5
SCK0 high-level width
t KH5
SCK0 low-level width
t KL5
SB0, SB1 setup time (to SCK0↑)
Test Conditions
R = 1 kΩ
C = 100 pF
Note
tSIK5
MIN.
MAX.
Unit
1 600
ns
tKCY5/2 – 160
ns
4.5 V ≤ VDD ≤ 5.5 V tKCY5/2 – 50
ns
3.5 V ≤ VDD < 4.5 V tKCY5/2 – 100
ns
4.5 V ≤ VDD ≤ 5.5 V
300
ns
3.5 V ≤ VDD < 4.5 V
350
ns
400
ns
ns
SB0, SB1 hold time (from SCK0↑)
tKSI5
600
SB0, SB1 output delay time from
SCK0↓
tKSO5
0
Note
TYP.
300
ns
R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line.
(vi) 2-wire serial I/O mode (SCK0 ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY6
1 600
ns
SCK0 high-level width
t KH6
650
ns
SCK0 low-level width
t KL6
800
ns
SB0, SB1 setup time (to SCK0↑)
tSIK6
100
ns
SB0, SB1 hold time (from SCK0↑)
tKSI6
t KCY6/2
ns
SB0, SB1 output delay time from
tKSO6
SCK0↓
C = 100 pF
SCK0 at rising or falling edge time
Note
R = 1 kΩ
Note
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
3.5 V ≤ VDD < 4.5 V
0
500
ns
1 000
ns
tR6, tF6
R and C are the load resistance and load capacitance of SB0 and SB1 output line.
37
µPD178004A, 178006A, 178016A, 178018A
(vii) I2C Bus mode (SCL ... internal clock output)
Parameter
SCL cycle time
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
10
µs
tKCY7 – 160
ns
t KCY7
R = 1 kΩ
SCL high-level width
t KH7
C = 100 pF Note
SCL low-level width
t KL7
t KCY7 – 50
ns
SDA0, SDA1 setup time (to SCL↑)
t SIK7
200
ns
SDA0, SDA1 hold time
(from SCL↓)
t KSI7
SDA0, SDA1 output delay time
(from SCL↓)
tKSO7
0
ns
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
3.5 V ≤ VDD < 4.5 V
0
500
ns
SDA0, SDA1↓ from SCL↑ or
SDA0, SDA1↑ from SCL↑
tKSB
200
ns
SCL↓ from SDA0, SDA1↓
t SBK
400
ns
SDA0, SDA1 high-level width
t SBH
500
ns
Note
R and C are the load resistance and load capacitance of SCL, SDA0 and SDA1 output line.
(viii) I 2C Bus mode (SCL ... external clock input)
Parameter
SCL cycle time
SCL high-/low-level width
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
t KCY8
1 000
ns
t KH8, tKL8
400
ns
SDA0, SDA1 setup time (to SCL↑)
t SIK8
SDA0, SDA1 hold time
(from SCL↓)
t KSI8
SDA0, SDA1 output delay time
tKSO8
from SCL↓
200
ns
0
ns
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
C = 100 pF Note 3.5 V ≤ VDD < 4.5 V
0
500
ns
R = 1 kΩ
SDA0, SDA1↓ from SCL↑ or
SDA0, SDA1↑ from SCL↑
tKSB
200
ns
SCL↓ from SDA0, SDA1↓
t SBK
400
ns
SDA0, SDA1 high-level width
t SBH
500
ns
SCL at rising or falling edge time
Note
38
tR8, t F8
1 000
R and C are the load resistance and load capacitance of SDA0 and SDA1 output line.
ns
µPD178004A, 178006A, 178016A, 178018A
(b) Serial interface channel 1
(i) 3-wire serial I/O mode (SCK1 ... internal clock output)
Parameter
SCK1 cycle time
SCK1 high/low-level width
SI1 setup time (to SCK1↑)
SI1 hold time (from SCK1↑)
SO1 output delay time (from SCK1↓)
Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
1 600
ns
tKH9,
4.5 V ≤ VDD ≤ 5.5 V
tKCY9/2 – 50
ns
t KL9
3.5 V ≤ VDD < 4.5 V
tKCY9/2 – 100
ns
tSIK9
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
150
ns
400
ns
tKCY9
tKSI9
t KSO9
C = 100 pF
Note
300
ns
MAX.
Unit
C is the load capacitance of SO1 output line.
(ii) 3-wire serial I/O mode (SCK1 ... external clock input)
Parameter
SCK1 cycle time
SCK1 high/low-level width
Symbol
Test Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
1 600
ns
t KH10,
4.5 V ≤ VDD ≤ 5.5 V
400
ns
t KL10
3.5 V ≤ VDD < 4.5 V
800
ns
tKCY10
SI1 setup time (to SCK1↑)
t SIK10
100
ns
SI1 hold time (from SCK1↑)
t KSI10
400
ns
SO1 output delay time (from SCK1↓)
tKSO10
C = 100 pF Note
SCK1 at rising or falling edge time tR10, tF10
Note
300
ns
1 000
ns
C is the load capacitance of SO1 output line.
39
µPD178004A, 178006A, 178016A, 178018A
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... internal clock
output)
Parameter
SCK1 cycle time
SCK1 high/low-level width
SI1 setup time (to SCK1↑)
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
1 600
ns
t KH11 ,
4.5 V ≤ VDD ≤ 5.5 V
tKCY11/2 – 50
ns
t KL11
3.5 V ≤ VDD < 4.5 V
tKCY11/2 – 100
ns
t SIK11
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
150
ns
400
ns
t KCY11
SI1 hold time (from SCK1↑)
t KSI11
SO1 output delay time (from SCK1↓)
t KSO11
C = 100 pF Note
300
ns
STB↑ from SCK1↑
t SBD
tKCY11/2 – 100
tKCY11/2 + 100
ns
Strobe signal high-level width
tSBW
t KCY11/ – 30
tKCY11 + 30
ns
Busy signal setup time
(to busy signal detection timing)
t BYS
100
ns
Busy signal hold time
t BYH
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
150
ns
(from busy signal detection timing)
SCK1↓ from busy inactive
Note
t SPS
2t KCY11
ns
C is the load capacitance of SO1 output line.
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... external clock
input)
Parameter
SCK1 cycle time
SCK1 high/low-level width
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
1 600
ns
t KH12 ,
4.5 V ≤ VDD ≤ 5.5 V
400
ns
t KL12
3.5 V ≤ VDD < 4.5 V
800
ns
t KCY12
SI1 setup time (to SCK1↑)
t SIK12
100
ns
SI1 hold time (from SCK1↑)
t KSI12
400
ns
SO1 output delay time (from SCK1↓)
t KSO12
C = 100 pF Note
SCK1 at rising or falling edge time t R12, t F12
Note
40
C is the load capacitance of SO1 output line.
300
ns
1 000
ns
µPD178004A, 178006A, 178016A, 178018A
AC TIMING TEST POINT (EXCLUDING X1 INPUT)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
TI Timing
1/fTI
tTIL
tTIH
TI1, TI2
Interrupt Input Timing
tINTL
tINTH
INTP0 to INTP6
RESET Input Timing
tRSL
RESET
41
µPD178004A, 178006A, 178016A, 178018A
SERIAL TRANSFER TIMING
3-Wire Serial I/O Mode:
tKCYm
tKLm
tKHm
tFn
tRn
SCK0, SCK1
tSIKm
SI0, SI1
tKSIm
Input Data
tKSOm
SO0, SI1
Output Data
Remark m = 1, 2, 9, 10
n = 2, 10
SBI Mode (Bus Release Signal Transfer):
tKCY3, 4
tKL3, 4
tKH3, 4
tF4
tR4
SCK0
tKSB
tSBL
tSBH
tSIK3, 4
tSBK
tKSI3, 4
SB0, SB1
tKSO3, 4
42
µPD178004A, 178006A, 178016A, 178018A
SBI Mode (Command Signal Transfer):
tKCY3, 4
tKL3, 4
tKH3, 4
tF4
tR4
SCK0
tSIK3, 4
tKSI3, 4
tSBK
tKSB
SB0, SB1
tKSO3, 4
2-Wire Serial I/O Mode:
tKCY5, 6
tKL5, 6
tKH5, 6
tR6
tF6
SCK0
tSIK5, 6
tKSI5, 6
tKSO5, 6
SB0, SB1
I2C Bus Mode:
tF8
tR8
tKCY7, 8
SCL
tKL7, 8
tKSI7, 8
tKH7, 8
tSIK7, 8
tKSO7, 8
tKSB
tKSB
tSBK
SDA0, SDA1
tSBH
tSBK
43
µPD178004A, 178006A, 178016A, 178018A
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function:
SO1
SI1
D2
D2
D1
D1
D0
D7
D0
D7
tKSI11, 12
tKH11, 12
tF12
tSIK11, 12
tKSO11, 12
SCK1
tR12
tKL11, 12
STB
tSBD
tSBW
tKCY11, 12
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function (Busy Processing):
SCK1
7
8
9 Note
10 Note
tBYS
10 + n Note
tBYH
1
tSPS
BUSY
(Active high)
Note
44
The signal is not actually driven low here; it is shown as such to indicate the timing.
µPD178004A, 178006A, 178016A, 178018A
A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = 4.5 to 5.5 V)
Parameter
Symbol
Test Conditions
Resolution
MIN.
TYP.
MAX.
Unit
8
8
8
bit
±3.0
LSB
44.4
µs
Conversion total
error
Conversion time
t CONV
22.2
Sampling time
t SAMP
15/fXX
Analog input
voltage
VIAN
0
µs
VDD
V
MAX.
Unit
Remarks 1. fXX: System clock frequency (f X/2)
2. fX: System clock oscillation frequency
PLL CHARACTERISTICS (TA = –40 to +85 °C, V DD = 4.5 to 5.5 V)
Parameter
Operating
Frequency
Symbol
Test Conditions
MIN.
TYP.
f IN1
VCOL Pin MF Mode Sine wave input VIN = 0.1 V p-p
0.5
3
MHz
f IN2
VCOL Pin HF Mode Sine wave input VIN = 0.2 Vp-p
9
55
MHz
f IN3
VCOH Pin VHF Mode Sine wave input VIN = 0.15 Vp-p
60
160
MHz
MAX.
Unit
IFC CHARACTERISTICS (T A = –40 to +85 °C, V DD = 4.5 to 5.5 V)
Parameter
Operating
Symbol
MIN.
TYP.
f IN4
AMIFC Pin AMIF Count Mode
Sine wave input VIN = 0.1 Vp-p Note
0.4
0.5
MHz
f IN5
FMIFC Pin FMIF Count Mode
Sine wave input VIN = 0.1 Vp-p Note
10
11
MHz
f IN6
FMIFC Pin AMIF Count Mode
Sine wave input VIN = 0.1 Vp-p Note
0.4
0.5
MHz
Frequency
Note
Test Conditions
The condition of a sine wave input of VIN = 0.1 Vp-p is the standard value for operation of this device during
stand-alone operation, so in consideration of the effect of noise, it is recommended that operation be at
an input amplitude condition of V IN = 0.15 V p-p.
45
µPD178004A, 178006A, 178016A, 178018A
11. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14×14)
A
B
41
40
60
61
detail of lead end
C D
S
R
Q
21
20
80
1
F
J
G
I
H
M
K
P
M
N
L
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
17.2±0.4
0.677±0.016
B
14.0±0.2
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.2±0.4
0.677±0.016
F
0.825
0.032
G
0.825
0.032
H
0.30±0.10
0.012 +0.004
–0.005
I
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
K
1.6±0.2
L
0.8±0.2
0.063±0.008
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.7
0.106
Q
0.1±0.1
0.004±0.004
R
5°±5°
5°±5°
S
3.0 MAX.
0.119 MAX.
S80GC-65-3B9-4
46
µPD178004A, 178006A, 178016A, 178018A
12. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below.
For detail of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales representative.
Table 12-1. Surface Mounting Type Soldering Conditions
µ PD178004AGC-×××-3B9 : 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch)
µ PD178006AGC-×××-3B9 : 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch)
µ PD178016AGC-×××-3B9 : 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch)
µ PD178018AGC-×××-3B9 : 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch)
Recommended
Condition Symbol
Soldering Method
Soldering Conditions
Infrared reflow
Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above),
Number of times: Three times max.
IR35-00-3
VPS
Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above),
Number of times: Three times max.
VP15-00-3
Wave soldering
Solder bath temperature : 260 °C max., Duration : 10 sec. max., Number of times
: once, Preheating temperature : 120 °C max.
(package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300 °C max. Duration: 3 sec. max. (per pin row)
—
Caution Do not use different soldering method together (except for partial heating).
47
µPD178004A, 178006A, 178016A, 178018A
APPENDIX A. DIFFERENCES BETWEEN µPD178018A AND µPD178018 SUBSERIES
Product name
µ PD178004
Reference
frequency
7 types selectable by program
(1, 3, 5, 9, 10, 25, 50 kHz)
11 types selectable by program
(1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50 kHz)
EO0 pin output
format
Buffer type
EO1 pin output
format
Buffer type
EO1 pin highNot supported
impedance function
Note
µPD178018 Subseries
µPD178004A µPD178006A µ PD178016A µ PD178018A
µPD178P018A Note
Item
PLL
frequency
synthesizer
µ PD178018A Subseries
µ PD178006
µ PD178016
µ PD178018
µ PD178P018
Constant-current power supply type
Supported
Not supported
Under development
Remark The mask ROM of mask versions ( µ PD178018A and µ PD178018) is replaced with one-time PROM
or EPROM in the one-time PROM versions ( µPD178P018A and µ PD178P018).
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µPD178004A, 178006A, 178016A, 178018A
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the µ PD178018A Subseries.
Language Processing Software
RA78K/0 Notes 1, 2, 3, 4
CC78K/0
Notes 1, 2, 3, 4
DF178018
Notes 1, 2, 3, 4, 8
CC78K/0-L
Notes 1, 2, 3, 4
78K/0 Series common assembler package
78K/0 Series common C compiler package
µPD178018A Subseries common device file
78K/0 Series common C compiler library source file
PROM Writing Tools
PG-1500
PROM programmer
PG-178P018GC
Programmer adapters connected to a PG-1500
PA-178P018KK-T
PG-1500 controller Notes 1, 2
PG-1500 control program
Debugging Tools
IE-78000-R
In-circuit emulator common to 78K/0 Series
IE-78000-R-A
In-circuit emulator common to 78K/0 Series (for the integration debugger)
IE-78000-R-BK
Break board common to 78K/0 Series
IE-178018-R-EM
Emulation board common to µPD178018A Subseries
IE-78000-R-SV3
Interface adapter and cable when using EWS as a host machine (for IE-78000-R-A)
IE-70000-98-IF-B
Interface adapter when using the PC-9800 Series (except notebooks) as a host machine
(for IE-78000-R-A)
IE-70000-98N-IF
Interface adapter and cable when using the PC-9800 Series notebook as a host machine
(for IE-78000-R-A)
IE-70000-PC-IF-B
Interface adapter when using IBM PC/ATTM as a host machine (for IE-78000-R-A)
EP-78230GC-R
Emulation probe common to µPD78234 Subseries
EV-9200GC-80
Socket for mounting on target system board created for 80-pin plastic QFP (GC-3B9 type)
EV-9900
Jig used when removing the µPD178P018AKK-T from the EV-9200GC-80.
SM78K0
ID78K0
Notes 5, 6, 7
Notes 4, 5, 6, 7
SD78K/0
Notes 1, 2
DF178018
Notes 1, 2, 4, 5, 6, 7, 8
78K/0 Series common system simulator
Integration debugger for IE-78000-R-A
IE-78000-R screen debugger
µPD178018A Subseries device file
49
µPD178004A, 178006A, 178016A, 178018A
Real-Time OS
RX78K/0 Notes 1, 2, 3, 4
MX78K0
78K/0 Series real-time OS
Notes 1, 2, 3, 4
Notes 1.
2.
3.
4.
5.
6.
7.
8.
78K/0 Series OS
PC-9800 Series (MS-DOS TM) based
IBM PC/AT and compatible (PC DOSTM /IBM-DOSTM /MS-DOS) based
HP9000 Series 300 TM based
HP9000 Series 700 TM (HP-UXTM ) based, SPARCstationTM (SunOSTM) based, EWS4800 Series
(EWS-UX/V) based
PC-9800 Series (MS-DOS + WindowsTM ) based
IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based
NEWS TM (NEWS-OSTM ) based
Under development
Fuzzy Inference Development Support System
FE9000 Note 1/FE9200 Note 2
FT9080
FI78K0
Note 1
/FT9085
Notes 1, 3
FD78K0
Notes 1, 3
Note 3
Fuzzy knowledge data creation tool
Translator
Fuzzy inference module
Fuzzy inference debugger
Notes 1. PC-9800 Series (MS-DOS) based
2. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based
3. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS) based
Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party
development tools.
2. The RA78K/0, CC78K/0, SD78K/0, ID78K/0, SM78K/0 and RX78K/0 are used in combination with
the DF178018.
50
µPD178004A, 178006A, 178016A, 178018A
APPENDIX C. RELATED DOCUMENTS
Device Documents
Document No.
(Japanese)
Document No.
(English)
µ PD178018A Subseries User’s Manual
To be prepared
To be prepared
78K/0 Series User’s Manual—Instruction
U12326J
U12326E
78K/0 Series Instruction Set
U10904J
—
78K/0 Series Instruction Table
U10903J
—
Title
µ PD178018A Subseries Special Function Register Table
78K/0 Series Application Note
To be prepared
Basics (II)
U10121J
—
U10121E
Development Tool Documents (User’s Manual)
Document No.
(Japanese)
Title
RA78K Series Assembler Package
Operation
EEU-809
EEU-1399
Language
EEU-815
EEU-1404
EEU-817
EEU-1402
RA78K Series Structured Assembler Preprocessor
RA78K0 Assembler Package
Document No.
(English)
Operation
U11802J
U11802E
Assembly Language
U11801J
U11801E
Structured Assembly
U11789J
U11789E
Operation
EEU-656
EEU-1280
Language
EEU-655
EEU-1284
Operation
U11517J
U11517E
Language
U11518J
U11518E
Programming Know-how
EEA-618
EEA-1208
Language
CC78K Series C Compiler
CC78K/0 C Compiler
CC78K/0 C Compiler Application Notes
CC78K Series Library Source File
U12322J
PG-1500 PROM Programmer
U11940J
EEU-1335
—
PG-1500 Controller PC-9800 Series (MS-DOS) Based
EEU-704
EEU-1291
PG-1500 Controller IBM PC Series (PC DOS) Based
EEU-5008
U10540E
IE-78000-R
U11376J
U11376E
IE-78000-R-A
U10057J
U10057E
IE-78000-R-BK
EEU-867
EEU-1427
IE-178018-R-EM
U10668J
U10668E
EP-78230
EEU-985
EEU-1515
SM78K0 System Simulator Windows Based
Reference
U10181J
U10181E
SM78K Series System Simulator
External Parts User
open Interface
Specifications
U10092J
U10092E
ID78K0 Integrated Debugger EWS Based
Reference
U11151J
U11151E
ID78K0 Integrated Debugger PC Based
Reference
U11539J
U11539E
ID78K0 Integrated Debugger Windows Based
Guide
U11649J
U11649E
SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based
Introduction
EEU-852
U10539E
Reference
U10952J
—
SD78K/0 Screen Debugger IBM PC/AT (PC DOS) Based
Introduction
EEU-5024
EEU-1414
Reference
U11279J
U11279E
Caution The contents of the above documents are subject to change without notice. Please ensure that
the latest versions are used in design work, etc.
51
µPD178004A, 178006A, 178016A, 178018A
Related Documents for Embedded Software (User’s Manual)
Title
78K/0 Series Realtime OS
78K/0 Series OS MX78K0
Document No.
Document No.
(Japanese)
(English)
Basics
U11537J
—
Installation
U11536J
—
Basics
U12257J
—
Fuzzy Knowledge Data Creation Tool
EEU-829
EEU-1438
78K/0, 78K/II, 87AD Series
EEU-862
EEU-1444
78K/0 Series Fuzzy Inference Development Support System—Fuzzy Inference Module
EEU-858
EEU-1441
78K/0 Series Fuzzy Inference Development Support System
EEU-921
EEU-1458
Fuzzy Inference Development Support System—Translator
—Fuzzy Inference Debugger
Other Documents
Title
Document No.
Document No.
(Japanese)
(English)
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Guides on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability and Quality Control
C10983J
C10983E
Electrostatic Discharge (ESD) Test
MEM-539
Semiconductor Device Quality Assurance Guide
C11893J
MEI-1202
Microcomputer-related Product Guide (Products by other Manufacturers)
U11416J
—
—
Caution The contents of the above documents are subject to change without notice. Ensure that the
latest versions are used in design work, etc.
52
µPD178004A, 178006A, 178016A, 178018A
[MEMO]
53
µPD178004A, 178006A, 178016A, 178018A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred.
Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices
must be stored and transported in an anti-static container, static shielding bag
or conductive material. All test and measurement tools including work bench
and floor should be grounded. The operator should be grounded using wrist
strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS device
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
54
µPD178004A, 178006A, 178016A, 178018A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
55
µPD178004A, 178006A, 178016A, 178018A
Purchase of NEC I2 C components conveys a license under the Philips I 2C Patent Rights to use these components in an I2 C
system, provided that the system conforms to the I2 C Standard Specification as defined by Philips.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be
prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country.
Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
56