DATA SHEET MOS INTEGRATED CIRCUIT µPD17P203A, 17P204 4-BIT SINGLE-CHIP MICROCONTROLLER WITH STATIC RAM AND 3-CHANNEL TIMER FOR INFRARED REMOTE CONTROLLER DESCRIPTION µPD17P203A and µPD17P204 are variations of µPD17203A and µPD17204 respectively and are equipped with a one-time PROM instead of an internal mask ROM. µPD17P203A and µPD17P204 are suitable for evaluating a program when developing µPD17203A and µPD17204 systems respectively because the program can be written by the user. When reading this document, also refer to the µPD17203A and µPD17204 Data Sheets. FEATURES • 17K architecture: General-purpose register format • Pin-compatible (except for PROM programming function): µPD17P203A with µPD17203A µPD17P204 with µPD17204 • Internal one-time PROM: 4096 x 16 bits (µPD17P203A) 7936 x 16 bits (µPD17P204) • Static RAM: 16 Kbits (µPD17P203A) 8 Kbits (µPD17P204) • Power supply voltage: 2.9 to 5.5 V (at TA = –20 to +75°C, fX = 4MHz) 2.0 to 5.5 V (at TA = –20 to +75°C, fXT = 32kHz) The features of each product is shown in the following table: Item µPD17P203A-001 µPD17P204-001 Pull-up resistor of RESET pin Pull-up resistor of P0A and P0B pins Main clock oscillator circuit Subclock oscillator circuit µPD17P203A-002 µPD17P204-002 Not provided Provided Provided Not provided µPD17P203A-003 µPD17P204-003 µPD17203A µPD17204 Not provided On request (mask option) Provided µPD17P203A and µPD17P204 are different from µPD17203A and µPD17204 respectively in the power supply voltage and the operating ambient temperature. Therefore, use µPD17P203A and µPD17P204 only for the system evaluation. This document explains µPD17P204 as a typical product where no specification is made. The information in this document is subject to change without notice. Document No. IC-2851A (O. D. No. IC-8303B) Date Published June 1995 P Printed in Japan The mark ★ shows major revised points. © 1992 µPD17P203A, 17P204 ORDERING INFORMATION Part Number 2 Package µPD17P203AGC-001-3BH 52-pin plastic QFP (14 × 14 mm) µPD17P203AGC-002-3BH 52-pin plastic QFP (14 × 14 mm) µPD17P203AGC-003-3BH 52-pin plastic QFP (14 × 14 mm) µPD17P204GC-001-3BH 52-pin plastic QFP (14 × 14 mm) µPD17P204GC-002-3BH 52-pin plastic QFP (14 × 14 mm) µPD17P204GC-003-3BH 52-pin plastic QFP (14 × 14 mm) µPD17P203A, 17P204 PIN CONFIGURATION (TOP VIEW) P1C0/SCK P1B3/TM2OUT P1B2/TM1OUT P1B1/TM0OUT P1B0 P1A3 P1A2 P1A1 P1A0 P0D3 52 1 P1C1/SO LED P1C2/SI P1C3 (1) Normal operation mode 51 50 49 48 47 46 45 44 43 42 41 40 39 P0D2 2 38 P0D1 VXRAM 3 37 P0D0 VDD 4 36 P0C3 XIN 5 35 P0C2 XOUT 6 34 P0C1 GND0 7 33 GND4 RESET 8 32 P0C0 WDOUT 9 31 P0B3 28 P0B0 25 27 26 P0A3 P0A2 13 14 GND1 GND5 15 16 17 18 19 20 21 22 23 24 P0A0 12 INT VREG TM0IN P0B1 CMPOUT 29 GND3 11 CMPIN+ XTOUT VREF P0B2 AMPOUT 30 GND2 10 AMPIN– XTIN P0A1 µPD17P203AGC-001-3BH µPD17P203AGC-002-3BH µPD17P203AGC-003-3BH µPD17P204GC-001-3BH µPD17P204GC-002-3BH µPD17P204GC-003-3BH REM AMPIN– : Operational amplifier input RESET : Reset input AMPOUT : Operational amplifier output SCK : Serial clock input/output CMPIN+ : Comparator input SI : Serial data input CMPOUT : Comparator output SO : Serial data output GND0-GND5 : Ground TM0IN : Timer 0 input INT : External interrupt input TM0OUT : Timer 0 output LED : Remote controller transmission TM1OUT : Timer 1 output TM2OUT : Timer 2 output output indicator P0A0-P0A3 : I/O port 0A VDD : Power supply P0B0-P0B3 : I/O port 0B VREG : Voltage regulator output P0C0-P0C3 : I/O port 0C VREF : Reference voltage output P0D0-P0D3 : I/O port 0D VXRAM : Static RAM (XRAM) power supply P1A0-P1A3 : I/O port 1A WDOUT : Overrun detection output P1B0-P1B3 : I/O port 1B XIN, XOUT : Main clock oscillation use P1C0-P1C3 : I/O port 1C XTIN, XTOUT : Subclock oscillation use REM : Remote controller transmission output 3 µPD17P203A, 17P204 D3 (L) (2) PROM programming mode 52 1 D2 2 38 D1 GND 3 37 D0 VDD 4 36 D7 CLK 5 35 D6 (Open) 6 34 D5 GND0 7 33 GND4 (L) 8 32 D4 (Open) 9 31 MD3 30 MD2 11 29 MD1 12 28 MD0 (L) 51 50 49 48 47 46 45 44 43 42 41 µPD17P203AGC-001-3BH µPD17P203AGC-002-3BH µPD17P203AGC-003-3BH µPD17P204GC-001-3BH µPD17P204GC-002-3BH µPD17P204GC-003-3BH 40 39 (Open) 10 Caution 22 23 24 25 27 26 (L) (L) 21 VPP 20 (L) 19 (Open) 18 GND3 17 (L) 16 (Open) 15 GND2 13 14 GND1 GND5 (L) (Open) Those enclosed in parentheses indicate the processing of the pins not used in PROM programming mode. L : Ground these pins through a resistor (470Ω). Open : Do not connect anything to these pins. CLK : PROM clock input MD0-MD3 : PROM mode selection D0-D7 : PROM data I/O VDD : Power supply VPP : Program power supply GND, GND0-GND5 : Ground 4 µPD17P203A, 17P204 BLOCK DIAGRAM V REG Power Supply Circuit P0A0 P0A1 P0A2 P0A3 P0A P0B0/MD0 P0B1/MD1 P0B2/MD2 P0B3/MD3 P0B P0C0/D4 P0C1/D5 P0C2/D6 P0C3/D7 V DD V XRAM V REF GND 0 GND 1 GND 2 GND 3 GND 4 GND 5 RF RAM 336 × 4 bits P0C SYSTEM REG. TM0IN CMPOUT P0D0/D0 P0D1/D1 P0D2/D2 P0D3/D3 Remote Control Receiver ALU P0D CMPIN + AMPOUT AMPIN – P1A0 P1A1 P1A2 P1A3 P1B0 P1B1/TM0OUT P1B2/TM1OUT P1B3/TM2OUT P1A One Time PROM P1B 4096 × 16 bits (µPD17P203A) 7936 × 16 bits (µPD17P204) Timer0/ Counter Program Counter Timer1/ Counter Stack Timer2/ Counter P1C0/SCK P1C1/SO P1C2/SI P1C3 Instruction Decoder Remote Control Transmitter 5 × 12 bits (µPD17P203A) 7 × 13 bits (µPD17P204) Interrupt Controller P1C LED INT/V PP RESET XRAM Serial I/O REM WDOUT 4096 × 4 bits (µPD17P203A) 2048 × 4 bits (µPD17P204) CPU Clock Clock Stop X IN/CLK Main clock X OUT Watch Timer Divider CPU Clock Subclock XT IN XT OUT 5 µPD17P203A, 17P204 CONTENTS 1. ★ ★ PIN FUNCTIONS ..................................................................................................................... 7 1.1 NORMAL OPERATION MODE ..................................................................................................... 7 1.2 PROM PROGRAMMING MODE ................................................................................................... 9 1.3 PIN I/O CIRCUITS .......................................................................................................................... 9 1.4 PROCESSING OF UNUSED PINS ................................................................................................ 12 1.5 NOTES ON USING RESET AND INT PINS ................................................................................. 13 2. DIFFERENCES BETWEEN MASK ROM PRODUCTS AND ONE-TIME PROM PRODUCTS .............................................................................................................................. 14 3. ONE-TIME PROM (PROGRAM MEMORY) WRITING, READING, AND VERIFICATION ............................................................................................................... 15 3.1 OPERATION MODE FOR WRITING, READING, AND VERIFICATION OF PROGRAM MEMORY .......................................................................... 15 3.2 PROGRAM MEMORY WRITE PROCEDURE ................................................................................ 16 3.3 PROGRAM MEMORY READ PROCEDURE ................................................................................. 17 4. ELECTRICAL SPECIFICATIONS ............................................................................................. 18 5. PACKAGE DRAWINGS ........................................................................................................... 23 6. RECOMMENDED SOLDERING CONDITIONS ...................................................................... 24 APPENDIX A. MICROCONTROLLERS FOR LEARNING REMOTE CONTROLLER ............. 25 APPENDIX B. DEVELOPMENT TOOLS ..................................................................................... 26 6 µPD17P203A, 17P204 1. PIN FUNCTIONS 1.1 NORMAL OPERATION MODE Pin No. Symbol 1 LED 2 (1/2) Output Format At Reset Outputs NRZ signal in synchronization with infrared remote controller signal. Remains low while remote control carrier is output CMOS push-pull High-level output REM Outputs active-high infrared remote control signal CMOS push-pull Low-level output 3 VXRAM Supplies power to XRAM – – 4 VDD Positive power – – 5 6 XIN XOUT Connect 4-MHz ceramic oscillator for main clock oscillation – (Oscillation stop) 7 GND0 Ground – – RESET Inputs low-active system reset signal. While this pin remains low level, oscillation of main clock stops. Pull-up resistor can also be connected by mask option (µPD17P203A-001 and µPD17P204-001 only). – – 9 WDOUT Outputs signal for detecting overrun. This pin outputs a low-level when an overflow in the watchdog timer or an overflow/underflow in the stack is detected. Connect this pin to the RESET pin. N-ch open drain High impedance 10 11 XTIN XTOUT Connect 32-kHz crystal oscillator across these pins. When option not using subclock is selected, main clock is divided and is supplied to watch timer. – (Oscillation) 12 VREG Outputs signal from voltage regulator for subclock oscillator circuit. Connect external 0.1-µF capacitor. – – 13 GND5 Ground – – 14 GND1 Ground of operation amplifier – – 15 AMPIN- Inverted input of operational amplifier – Input 16 GND2 Ground of operational amplifier – – 17 AMPOUT Output of operational amplifier – Output 18 VREF Outputs reference voltage of 1/2VDD. Connect external 0.1-µF capacitor. – – 19 CMPIN+ Non-inverted input of comparator. Output of this comparator can be obtained from CMPOUT. – Input 20 GND3 Ground of operational amplifier – – 8 Remark Function ★ GND1-GND3 are the ground pins of the operational amplifier. Keep all these pins at the same potential to stabilize the operation of the operational amplifier. 7 µPD17P203A, 17P204 (2/2) Pin No. Symbol 21 CMPOUT Function Output Format At Reset Comparator output. Externally connect CMPOUT and TM0IN when using microcontroller as teaching remote controller – Output Clock input to timer 0. Input clock is sampled by internal clock and then input to envelope signal generator circuit, as well as to timer 0. By using timer 0 with timer 1, frequency of clock input to this pin can be measured. – Input – Input CMOS push-pull Input N-ch open drain Input – – N-ch open drain Input 22 TM0IN 23 INT External interrupt signal input pin 24 to 27 P0A0 to P0A3 28 to 31 P0B0 to P0B3 Constitute 4-bit I/O port, which can be set in input or output mode in 4-bit units. Pull-up resistor can be connected by mask option (µPD17P203A-001, -002 and µPD17P204-001, -002 only). When one or more of these pins goes low in standby mode standby mode is released. 32 34 to 36 P0C0 P0C1 to P0C3 Constitute 4-bit I/O port, which can be set in input or output mode in 4-bit units. 33 GND4 Ground 37 to 40 P0D0 to P0D3 Constitute 4-bit I/O port, which can be set in input or output mode in 4-bit units. 41 to 44 P1A0 to P1A3 Constitute 4-bit I/O port, which can be set in input or output mode in bitwise. Pull-up registor can be connected through program. N-ch open drain Input 45 46 P1B0 P1B1/ TM0OUT P1B2/ TM1OUT P1B3/ TM2OUT Port 1B or timer output • P1B0-P1B3 - 4-bit I/O port - Can be set in input/output mode in bitwise - Pull-up resistor can be connected through program • TM0OUT-TM2OUT - Timer output N-ch open drain Input (P1B0-P1B3) P1C0/SCK P1C1/SO P1C2/SI P1C3 Port 1C or serial interface I/O • P1C0-P1C3 - 4-bit I/O port - Can be set in input/output mode in bitwise • SCK, SO, SI - SCK : serial clock I/O - SO : serial clock data output - SI : serial clock data input CMOS push-pull Input (P1C0-P1C3) 47 48 49 50 51 52 Caution For “A” standard products, note that standby mode is released when one or more of P0C and P0D pins goes high in standby mode. 8 µPD17P203A, 17P204 1.2 PROM PROGRAMMING MODE Pin No. Symbol Function Output Format At Reset Ground – – 3 7 13 14 16 20 33 GND GND0 GND5 GND1 GND2 GND3 GND4 4 VDD Positive power – – 5 CLK Address updating clock input – Input 23 VPP Supplies program voltage. Apply 12.5V to this pin – – 28 to 31 MD0 to MD3 Selects PROM programming mode – Input 32, 34 to 36 D4 to D7 CMOS push-pull Input 37 to 40 D0 to D3 1.3 8-bit data I/O PIN I/O CIRCUITS This section shows the I/O circuits of the µPD17P204 pins in simplified schematic diagrams. (1) P0A0-P0A3, P0B0/MD0-P0B3/MD3 V DD Data Output latch P-ch V DD Pull-up resistor Note N-ch Output disable Input buffer Note µPD17P203A-001, -002 and µPD17P204-001, -002 only. 9 µPD17P203A, 17P204 (2) P0C0/D4-P0C3/D7, P0D0/D0-P0D3/D3 Data Output latch N-ch Output disable Input buffer (3) P1A0-P1A3, P1B0-P1B3/TM2OUT V DD Data Pull-up resistor Data Output latch P-ch N-ch Output disable Input buffer 10 µPD17P203A, 17P204 (4) P1C0/SCK-P1C3 V DD Data Pull-up resistor P-ch V DD Data Output latch P-ch N-ch Output disable Input buffer (5) RESET V DD Pull-up resistor Note Input buffer Note µPD17P203A-001 and µPD17P204-001 only 11 µPD17P203A, 17P204 ★ 1.4 PROCESSING OF UNUSED PINS The following are recommended to process unused pins. Table 1-1. Processing of Unused Pins Pin Recommended Connection INT, TM0IN Connect to VDD or GND P0A0-P0A3, P0B0-P0B3 Input: Connect each pin to VDD through resistor Output: Open (high-level output) P0C0-P0C3, P0D0-P0D3 P1A0-P1A3, P1B0-P1B3 Input: Connect each pin to VDD or GND through resistor Output: Open (low-level output) P1C0-P1C3 Input: Connect each pin to VDD or GND through resistor Ouput: Open LED Open REM Open WDOUT Connect to GND XIN 12 XOUT Connect to VDD XTIN Connect to GND XTOUT Connect to VREG AMPIN– Connect to GND or AMPOUT AMPOUT, CMPOUT Open CMPIN+ Connect to GND VREF Open µPD17P203A, 17P204 1.5 NOTES ON USING RESET AND INT PINS (NORMAL OPERATION MODE ONLY) ★ In addition to the functions shown in 1. PIN FUNCTIONS, the RESET and INT pins also have a function to set a test mode (for IC testing) in which the internal operations of the µPD17P204 are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during normal operation, the µPD17P204 may be set in the test mode if a noise exceeding VDD is applied. For example, if the wiring length of the RESET or INT pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. • Connect diode with low VF between VDD and RESET/INT pin • Connect capacitor between VDD and RESET/INT pin VDD VDD VDD Diode with low VF RESET, INT VDD RESET, INT 13 µPD17P203A, 17P204 2. DIFFERENCES BETWEEN MASK ROM PRODUCTS AND ONE-TIME PROM PRODUCTS The µPD17P203A and µPD17203 are identical in the CPU functions and internal hardware peripherals except for that the µPD17P204 is provided with a PROM, which can be written by the user, in the place of the mask ROM of the µPD17204. The only differences between the two microcontrollers are therefore the program memory and mask option. The relation between the µPD17P204 and µPD17204 is the same as the relation between the µPD17P203A and µPD17203. Note that the µPD17P203A and µPD17P204 is slightly different from the µPD17203A and µPD17204 respectively in electrical characteristics, such as supply voltage and supply current. The following shows the differences between µPD17P203A and µPD17203A; µPD17P204 and µPD17204. For the CPU functions and internal hardware peripherals of the µPD17203A and µPD17P204, therefore, refer to the Data Sheet of the µPD17203A and µPD17204. Product Item µPD17P203A-001 µPD17P203A-002 µPD17P203A-003 • One-time PROM • 0000H-0FFFH • 4096x16 bits Program memory Pull-up resistor of RESET pin • Mask ROM • 0000H-0FFFH • 4096x16 bits Not provided Pull-up resistor of P0A and P0B pins Provided Provided Not provided Main clock oscillator circuit Subclock oscillator circuit Not provided Not provided VDD = 2.9 to 5.5 V (at 4MHz)Note (TA = –20 to 75°C) Package Product µPD17P204-001 µPD17P204-002 Pull-up resistor of P0A and P0B pins Provided • Mask ROM • 0000H-1EFFH • 7936x16 bits Provided Not provided Main clock oscillator circuit Subclock oscillator circuit Vpp pin, PROM program pins 14 µPD17204 Not provided Pull-up resistor of RESET pin Note (at 4MHz) µPD17P204-003 • One-time PROM • 0000H-1EFFH • 7936x16 bits Program memory Package VDD = 2.2 to 5.5 V 52-pin plastic QFP Item Power supply (TA = –20 to 75°C) On request (mask option) Provided Provided Vpp pin, PROM program pins Power supply voltage µPD17203A Not provided On request (mask option) Provided Provided VDD = 2.9 to 5.5 V (at 4MHz)Note Not provided VDD = 2.2 to 5.5 V (at 4MHz) 52-pin plastic QFP For details on the power supply voltage, refer to 4. ELECRICAL SPECIFICATIONS. µPD17P203A, 17P204 3. ONE-TIME PROM (PROGRAM MEMORY) WRITING, READING, AND VERIFICATION The program memory of 4096 x 16 bits (µPD17P203A) and 7936 x 16 bits (µPD17P204) one-time PROM are provided. The following table lists the pins to be used for this PROM writing, reading or verification. In PROM mode, no address input pin is used. Instead, the address is updated by the clock for input from the CLK pin. Pin Name 3.1 Function VPP Applies program voltage. CLK Inputs address update clock. MD0-MD3 Selects operation mode. D0-D7 Inputs and outputs 8-bit data. OPERATION MODE FOR WRITING, READING, AND VERIFICATION OF PROGRAM MEMORY If +6 V is applied to the VDD and +12.5 V to the VPP pin after µPD17P204 has been placed in the reset status for a fixed time (VDD = 5V, RESET = 0V), µPD17P204 enters program memory write, read, or verify mode. The MD0 to MD3 pins are used to set the operation modes listed in the following table. Leave the pins not used for program memory writing, reading, or verification open or ground through pull-down resistors. Operating Mode Specification Operating Mode VPP +12.5 V VDD +6 V MD0 MD1 MD2 MD3 H L H L Program memory address 0 clear mode L H H H Write mode L L H H Read/verify mode H x H H Program inhibit mode x: L or H 15 µPD17P203A, 17P204 3.2 PROGRAM MEMORY WRITE PROCEDURE The program memory write procedure is as follows. High-speed program memory write is possible. (1) Ground the unused pins through pull-down resistors. The CLK pin must be low. (2) Supply 5 V to the VDD pin. The VPP pin must be low. (3) After waiting for 10 microseconds, supply 5 V to the VPP pin. (4) Operate the MD0 to MD3 pins to set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Write data in 1-millisecond write mode. (8) Set program inhibit mode. (9) Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been written, repeat steps (7) to (9). (10) Write additional data for (the number of times data was written (X) in steps (7) to (9)) times 1 milliseconds. (11) Set program inhibit mode. (12) Supply a pulse to the CLK pin four times to update the program memory address by 1. (13) Repeat steps (7) to (12) to the last address. (14) Set program memory address 0 clear mode. (15) Change the voltages of VDD and VPP pins to 5 V. (16) Turn off the power supply. Steps (2) to (12) are illustrated below. X-time repetition Reset Write Additional data write Verify Address increment VPP VPP VDD GND VDD+1 VDD VDD GND CLK D0-D7 MD0 MD1 MD2 MD3 16 Hi-Z Hi-Z Data input Hi-Z Data output Hi-Z Data input µPD17P203A, 17P204 3.3 PROGRAM MEMORY READ PROCEDURE (1) Ground the unused pins through pull-down resistors. The CLK pin must be low. (2) Supply 5 V to the VDD pin. The VPP pin must be low. (3) After waiting for 10 microseconds, supply 5 V to the VPP pin. (4) Operate the MD0 to MD3 pins to set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the CLK pin four times. (8) Set program inhibit mode. (9) Set program memory address 0 clear mode. (10) Change the voltages of VDD and VPP pins to 5 V. (11) Turn off the power supply. Steps (2) to (9) are illustrated below. VPP VPP VDD GND VDD+1 VDD VDD GND 1 cycle CLK D0-D7 Hi-Z Data output Data output Hi-Z MD0 MD1 “L” MD2 MD3 17 µPD17P203A, 17P204 4. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Item Symbol Supply voltage VDD Input voltage VI IOH1 IOH2 IOH3 High-level output current IOH4 IOH5 IOH6 IOL1 IOL2 Low-level output current IOL3 IOL4 Conditions • • • REM pin • • • • • 1 pin (except for REM pin) •• • • • • Total (except for REM pin) •• • • • • • 1 pin • • • • • • Total • • • Ratings Unit –0.3 to +7.0 V –0.3 to VDD + 0.3 V –30 mA –20 mA Peak value –7.5 mA Effective valueNote –5.0 mA Peak value –22.5 mA –15.0 mA Peak value 7.5 mA Effective valueNote 5.0 mA Peak value 30 mA 20 mA Peak value Effective Effective Effective valueNote valueNote valueNote Operating ambient temperature TA –20 to +75 °C Storage temperature Tstg –40 to +125 °C Note Effective value = Peak value x √ Duty Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. RECOMMENDED OPERATING RANGE (TA = –20 to +75˚C) Item Symbol VDD1 Conditions VDD2 VDD3 TYP. MAX. Unit 2.7 3.0 5.5 V 2.9 3.0 5.5 V 4.75 5.0 5.5 V 2.0 3.0 5.5 V 1.0 4.0 8.0 MHz When the system clock is fX = 4 MHz, TA = –20 to 55°C Supply voltage MIN. When the system clock is fX = 4 MHz When the system clock is fX = 6 MHz, TA = –20 to 50°C VDD4 Main clock oscillation frequency fX Subclock oscillation frequency fXT When the system clock is fXT = 32 kHz 32.768 kHz CAPACITANCE (TA = 25°C, VDD = 0 V) Item Input capacitance 18 Symbol Conditions MIN. TYP. MAX. Unit CIN INT, RESET pins 10 pF CPIN Other than INT, RESET pins 10 pF µPD17P203A, 17P204 DC CHARACTERISTICS (VDD = VXRAM = 3 V, TA = –20 to +75°C, fX = 4 MHz, fXT = 32 kHz) Item Symbol Conditions MIN. TYP. MAX. Unit VIH1 RESET, INT pins 2.4 3.0 V VIH2 Other than RESET, INT pins 2.1 3.0 V VIL1 RESET, INT pins 0 0.6 V VIL2 Other than RESET, INT pins 0 0.9 V IIH1 INT VIH = 3 V 0.2 µA IIH2 TM0IN VIH = 3 V 0.2 µA IIH3 RESET VIH = 3 V 0.2 µA IIH4 P0A-P0D VIH = 3 V 0.2 µA IIH5 P1A-P1C VIH = 3 V 0.2 µA IIL1 INT VIL = 0 V –0.2 µA IIL2 TM0IN VIL = 0 V –0.2 µA High-Level Input Voltage Low-Level Input Voltage High-Level Input Current IIL3 RESET IIL4 Low-Level Input Current VIL = 0 V, w/pull-up resistors IIL5 P0A,P0B IIL6 IIL7 –60 –8 –15 P0C,P0D VIL = 0 V P1A-P1C IIL9 VIL = 0 V, w/o pull-up resistors VIL = 0 V, w/pull-up resistors –0.2 µA –120 µA –0.2 µA –30 µA –0.2 µA –0.2 µA –30 –60 –120 µA –2.0 –4.0 mA IOH1 P0A,P0B VOH = 2.7 V –0.6 IOH2 P1C VOH = 2.7 V –0.6 –2.0 –4.0 mA IOH3 REM VOH = 1 V –7.0 –15.0 –25.0 mA IOH4 LED VOH = 2.7 V –0.3 –1.0 –2.0 mA IOH5 CMPOUT VOH = 2.7 V –0.3 –1.0 –2.0 mA IOL1 P0A,P0B,P1C VOL = 0.3 V 0.5 1.5 2.5 mA IOL2 P0C,P0D,P1B VOL = 0.3 V 0.5 1.5 2.5 mA IOL3 P1A VOL = 0.3 V 1.5 4.5 7.5 mA IOL4 REM VOL = 0.3 V 0.5 1.5 2.5 mA IOL5 LED,WDOUT VOL = 0.3 V 0.5 1.5 2.5 mA IOL6 CMPOUT VOL = 0.3 V 0.5 1.5 2.5 mA VREF C = 0.1 µF, R = 82 KΩ 0.8 1.1 1.6 V IDD1 0.5 2.0 4.0 mA IDD2 Generates both XT and X Operation mode Generates XT only 400 600 µA IDD3 Generates both XT and X 2.0 mA 20 30 µA 5.0 7.0 µA 0.2 1.0 µA Low-Level Output Current VREF Output Voltage –30 VIL = 0 V, w/o pull-up resistors VIL = 0 V, w/pull-up resistors IIL8 High-Level Output Current VIL = 0 V, w/o pull-up resistors Supply Current IDD4 HALT mode Generates XT only IXRAM1 Operation mode, VXRAM = 3 V IXRAM2 HALT mode, VXRAM = 3 V, TA = 25°C XRAM Supply Current 3.0 ★ 19 µPD17P203A, 17P204 XRAM LOW SUPPLY VOLTAGE DATA HOLDING CHARACTERISTICS (TA = –20 to +75°C, VDD ≤ VXRAMDR) Item Data Holding Voltage Symbol Conditions VXRAMDR MIN. TYP. 1.3 MAX. Unit 5.5 V MAX. Unit DC PROGRAMMING CHARACTERISTICS (TA = 25°C, VDD = 6.0±0.25 V, VPP = 12.5±0.3 V) Item Symbol Conditions TYP. VIH1 Other than CLK 0.7 VDD VDD V VIH2 CLK VDD –0.5 VDD V VIL1 Other than CLK 0 0.3 VDD V VIL2 CLK 0 0.4 V Input Leakage Current ILI VIN = VIL or VIH 10 µA High-Level Output Voltage VOH IOH = –1 mA Low-Level Output Voltage VOL IOL = 1.6 mA VDD Supply Current IDD VPP Supply Current IPP High-Level Input Voltage Low-Level Input Voltage MD0 = VIL, MD1 = VIH Cautions 1. VPP must not exceed +13.5 V, including the overshoot. 2. Apply VDD before VPP and disconnect it after VPP. 20 MIN. VDD –1.0 V 0.4 V 30 mA 30 mA µPD17P203A, 17P204 AC PROGRAMMING CHARACTERISTICS (TA = 25°C, VDD = 6.0±0.25 V, VPP = 12.5±0.3 V) Item Symbol Note 1 Conditions MIN. TYP. MAX. Unit Address Setup TimeNote 2 (vs.MD0↓) tAS tAS 2 µs MD1 Setup Time (vs. MD0↓) tM1S tOES 2 µs Data Setup Time (vs. MD0↓) tDS tDS 2 µs tAH tAH 2 µs µs Address Hold TimeNote 2 (vs.MD0↑) Data Hold Time (vs. MD0↑) tDH tDH 2 MD0 ↑→ Data Output Float Delay Time tDF tDF 0 VPP Setup Time (vs. MD3↑) tVPS tVPS 2 VDD Setup Time (vs. MD3↑) tVDS tVCS 2 Initial Program Pulse Width tPW tPW 0.95 Additional Program Pulse Width tOPW tOPW 0.95 MD0 Setup Time (vs. MD1↑) tMOS tCES 2 tDV tDV MD0 ↓→ Data Output Delay Time µs 1.0 1.05 ms 21.0 ms µs 1 µs 2 µs 2 µs µs tM1H tOEH MD1 Recovery Time (vs. MD0↓) tM1R tOR Program Counter Reset Time tPCR – 10 tXH,tXL – 0.125 tM1H + tM1R ≥ 50 µs ns µs MD0 = MD1 = VIL MD1 Hold Time (vs. MD0↑) CLK Input High-/Low- Level Width 130 µs 4.19 MHz CLK Input Frequency fX – Initial Mode Set Time tI – 2 µs MD3 Setup Time (vs. MD1↑) tM3S – 2 µs MD3 Hold Time (vs. MD1↓) tM3H – 2 µs MD3 Setup Time (vs. MD0↓) tM3SR – When data is read from program memory 2 µs AddressNote 2 → Data Output Delay Time tDAD tACC When data is read from program memory → Data Output Hold Time tHAD tOH When data is read from program memory 0 MD3 Hold Time (vs. MD0↑) tM3HR – When data is read from program memory 2 µs MD3 ↓→ Data Output Float Delay Time tDFR – When data is read from program memory 2 µs Reset Setup Time tRES 10 µs AddressNote 2 Notes 2 µs 130 ns 1. These symbols are the corresponding µPD27C256 (maintenance product) symbols. 2. The internal address is incremented by 1 at the third falling edge of CLK (with four clocks constituting as one cycle). The internal address is not connected to any pin. 21 µPD17P203A, 17P204 PROGRAM MEMORY WRITE TIMING tRES VPP VDD tVPS VPP VDD GND VDD+1 VDD GND tVDS tXH CLK D0-D7 Hi-Z Hi-Z Data input tDS tDH t1 Hi-Z Data output tDV Data input tDF Hi-Z tXL tDH tAH tDS Data input tAS MD0 tPW tM1R tM0S tOPW MD1 tPCR tM1S tM1H MD2 tM3H tM3S MD3 PROGRAM MEMORY READ TIMING tRES tVPS VPP VPP VDD GND VDD VDD+1 VDD GND tVDS tXH CLK tXL D0-D7 Hi-Z Data output tDV t1 MD0 MD1 “L” tPCR MD2 tM3SR MD3 22 tHAD tDAD Hi-Z Data output tM3HR tDFR Hi-Z µPD17P203A, 17P204 ★ PACKAGE DRAWINGS 52 PIN PLASTIC QFP ( 14) A B 39 40 27 26 F 52 1 G R Q S C detail of lead end D 5. 14 13 H I M J M P K N L NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.2±0.2 0.677±0.008 B 14.0±0.2 0.551 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.2±0.2 0.677±0.008 F 1.0 0.039 G 1.0 0.039 H 0.40±0.10 0.016 +0.004 –0.005 I 0.20 0.008 J 1.0 (T.P.) 0.039 (T.P.) K 1.6±0.2 0.063±0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q R 0.125±0.075 5°±5° 0.005±0.003 5°±5° S 3.0 MAX. 0.119 MAX. S52GC-100-3BH-2 23 µPD17P203A, 17P204 ★ 6. RECOMMENDED SOLDERING CONDITIONS Soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document “Semiconductor device mounting technology manual” (IEI-1207). For other soldering methods, please consult with NEC personnel. Table 6-1. Soldering Conditions of Surface Mount Type µPD17P203AGC-001-3BH : 52-pin plastic QFP (14 × 14 mm) µPD17P203AGC-002-3BH : 52-pin plastic QFP (14 × 14 mm) µPD17P203AGC-003-3BH : 52-pin plastic QFP (14 × 14 mm) µPD17P204GC-001-3BH : 52-pin plastic QFP (14 × 14 mm) µPD17P204GC-002-3BH : 52-pin plastic QFP (14 × 14 mm) µPD17P204GC-003-3BH : 52-pin plastic QFP (14 × 14 mm) Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. (210˚C min), Number of times: 2 max., Days: 7 daysNote (after that, prebaking is necessary for 20 hours at 125˚C) <Caution> (1) Start second reflow after device temperature (which has risen because of first reflow) has returned to room temperature. (2) Do not clean flux with water after first reflow. IR35-207-2 VPS Package peak temperature: 215˚C, Time: 40 seconds max. (200˚C min), Number of times: 2 max., Days: 7 daysNote (after that, prebaking is necessary for 20 hours at 125˚C) <Caution> (1) Start second reflow after device temperature (which has risen because of first reflow) has returned to room temperature. (2) Do not clean flux with water after first reflow. VP15-207-2 Pin part heating Pin temperature: 300˚C max., Time: 3 seconds max. (per side of device) —— Note The number of days the device can be stored after the dry pack was opened, under storage conditions of 25˚C and 65% RH max. Caution Do not use two or more soldering methods in combination (except the pin partial heating method). 24 µPD17P203A, 17P204 APPENDIX A. MICROCONTROLLERS FOR LEARNING REMOTE CONTROLLER Product Item ROM Capacity µPD17203A µPD17P203A µPD17204 µPD17P204 4096 x 16 bits (mask ROM) 4096 x 16 bits (one-time PROM) 7936 x 16 bits (mask ROM) 7936 x 16 bits (one-time PROM) 336 x 4 bits RAM Capacity 4096 x 4 bits Static RAM Capacity 2048 x 4 bits Carrier Generator for Infrared Remote Controller Provided Receiver Preamplifier for Infrared Remote Controller Provided I/O Ports 28 External Interrupt (INT) 1 8-bit timer: 3 channels Timer 4 channels Provided (WDOUT output) Watchdog Timer 1 channel Serial Interface 5 levels (interrupt nesting: 3 levels) 7 levels (interrupt nesting: 3 levels) Stack STOP and HALT modes Standby Function Instruction Execution Time (supply voltage) TA = –20 to +75°C Main System Clock 4 µs at 4 MHz (VDD = 2.2 to 5.5V) (VDD = 2.9 to 5.5VNote) (VDD = 2.2 to 5.5V) (VDD = 2.9 to 5.5VNote) Sub-System Clock Package Note Watch timer: 1 channel 488 µs at 32.768 kHz (VDD = 2.0 to 5.5 V) 52-pin plastic QFP The supply voltage varies depending on the operating ambient temperature. For details, refer to 4. ELECTRICAL SPECIFICATIONS. 25 µPD17P203A, 17P204 ★ APPENDIX B. DEVELOPMENT TOOLS The following tools are readily available for µPD17P203A and µPD17P204 program development. Hardware Name In-circuit emulators IE-17K IE-17K-ETNote 1 EMU-17KNote 2 Outline The IE-17K, IE-17K-ET, and EMU-17 are in-circuit emulators that can be commonly used with the 17K series products. The IE-17K and IE-17K-ET are connected to the host machine, which is a PC-9800 series product or IBM PC/ATTM, via RS-232-C. The EMU-17K is inserted into an expansion slot of a PC-9800 series product. When these in-circuit emulators are used in combination with a system evaluation board (SE board) dedicated to each model of the device, they operate as the emulator dedicated to that model. A more sophisticated debugging environment can be created by using the man-machine interface software, SIMPLEHOSTTM. The EMU-17K has a function that allows you to check the contents of the data memory real-time. SE board (SE-17204) The SE-17204 is an SE board for the µPD17203A, 17P203A, 17204 and 17P204. It may be used alone to evaluated a system, or in combination with an in-circuit emulator for debugging. Emulation Probe (EP-17203GC) The EP-17203GC is an emulation probe for the µPD17203A, 17P203A, 17204 and 17P204. It connects an SE board and the user system. When used with the EV-9200G-52 this probe connects the SE board and the target system. Conversion socket (EV-9200G-52Note 3) The EV-9200G-52 connects the EP-17203GC and the target system. PROM programmer (AF-9703Note 4, AF-9704Note 4 AF-9705Note 4, AF9706Note 4) The AF9703, AF9704, AF9705, and AF9706 are PROM programmers that can program the µPD17P203A and 17P204. When connected with programmer adapter AF-9808A, this PROM programmer can program the µPD17P203A and 17P204. Program adapter (AF-9808BNote 4) The AF-9808A is an adapter for programming the µPD17P203AGC and 17P204GC and is used in combination with the AF-9703, AF-9704, AF-9705, and AF-9706. Notes 1. Low-cost model: external power supply type 2. This is a product from I.C., Corp. For details, consult I.C. 3. One EV-9200G-52 is supplied with the EP-17203GC. Five EV-9200G-52s are optionally available as a set. 4. These are products from Ando Electric. For details, consult Ando Electric. 26 µPD17P203A, 17P204 Software Outline Machine Name AS17K is an assembler that can be used in common with the 17K series products. When developing the program of the µPD17P203A and 17P204, AS17K is used in combination with a device file (AS17203, AS17204). 17K series assembler (AS17K) AS17203 is a device file for µPD17203A, and 17P203A, and it is used in combination with an assembler commonly used for the 17K series (AS17K). Device file (AS17203) AS17204 is a device file for µPD17204 and 17P204, and it is used in combination with an assembler for the 17K series (AS17K). Device file (AS17204) Support software (SIMPLEHOST) Host OS Media PC-9800 series MS-DOSTM IBM PC/AT Supply Order Code 5” 2DH µS5A10AS17K 3.5” 2HD µS5A13AS17K 5” 2HC µS7B10AS17K 3.5” 2HC µS7B13AS17K 5” 2HD µS5A10AS17203 PC DOSTM PC-9800 series MS-DOS IBM PC/AT PC DOS PC-9800 series MS-DOS IBM PC/AT PC DOS 3.5” 2HD µS5A13AS17203 5” 2HC 3.5” 2HC µS7B13AS17203 5” 2HD PC-9800 series is developed by using an incircuit emulator and a personal computer. IBM PC/AT µS5A10AS17204 3.5” 2HD µS5A13AS17204 5” 2HC SIMPLEHOST is a software package that enables manmachine interface on the WindowsTM when a program µS7B10AS17203 µS7B10AS17204 3.5” 2HC µS7B13AS17204 5” 2HD µS5A10IE17K 3.5” 2HD µS5A13IE17K 5” 2HC µS7B10IE17K 3.5” 2HC µS7B13IE17K MS-DOS Windows PC DOS Remark The corresponding OS versions are as follows: OS Version MS-DOS Ver. 3.30 to Ver. 5.00ANote PC DOS Ver. 3.1 to Ver. 5.0Note Windows Ver. 3.0 to Ver. 3.1 Note Ver. 5.00/5.00A of MS-DOS and Ver. 5.0 of PC DOS have a task swap function, but this function cannot be used with this software. 27 µPD17P203A, 17P204 [MEMO] 28 µPD17P203A, 17P204 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 29 µPD17P203A, 17P204 [MEMO] SIMPLEHOST is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11