µPD75112(A), 75116(A) 4-Bit Single Chip-Microcomputer Data Sheet Description The µPD75116(A) is one of the 4-bit single-chip microcomputer 75X series. The µPD75116(A) is a product with the extended ROM capacity of the µPD75108(A). In addition of high-speed operations, it can manipulate data in units of 1, 4 and 8 bits. In particular, the I/O operation of the µPD75116 have been improved by a wide variety of bit control instructions. The µPD75116 is provided with interface inputs/outputs with peripheral circuits having different power voltages, and analog inputs and suitable for controlling automobile electrical equipment, etc. For the µPD75116(A), an on-chip pin-compatible one-time PROM product (µPD75P116) is separately available for system development evaluation. Functions are described in detail in the following User’s Manual, which should be read when carrying out design work. µPD751×× Series User’s Manual: IEM-992 Ordering Code Qualty Grade Package µPD75112CW(A)-××× 64-pin plastic shrink DIP (750 mil) µPD75112GF(A)-×××-3BE 64-pin plastic QFP (14 × 20 mm) 64-pin plastic shrink DIP µPD75116CW(A)-××× (750 mil) µPD75116GF(A)-×××-3BE 64-pin plastic QFP (14 × 20 mm) Special Special Special Special Remarks: ××× is a ROM code number. Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Unless there are any particular functional differences, the µPD75116(A) is described in this document as a representative product. Features • Higher reliability than µPD75116 • Architecture "75X" equivalent to 8-bit microcomputer • Minimum instruction execution time (high-speed operation): 0.95 µs (when operated at 4.19 MHz and 5 V) • Instruction execution variable function: 0.95µs/1.91µs/ 15.3 µs (when operated at 4.19 MHz) • Many input/output ports: 58 • 3-channel on-chip 8-bit timers • 8-bit on-chip serial interface • Multi-interruptible vector interrupt function Applications Automobile electrical equipment, etc. The information in this document is subject to change without notice. The mark Document No. IC-2811A (O. D. No. IC-8261A) Date Published March 1994 P Printed in Japan ★ shows major revised points. ©NEC Corporation 1990 µPD75112(A), 75116(A) Defferences between µPD75112(A), 75116(A) and µPD75112, 75116 Product Name µPD75112(A), 75116(A) Item Quality grade Special Electrical specifications µPD75112, 75116 Standard Absolute maximum ratings Different high-level output current and low-level output current DC characteristics Different low-level output voltage Direct LED drive Not possible Possible Outline of Functions Item 2 Description No. of basic instruction 43 Min. instruction execution time 0.95 µs/1.91 µs/15.3 µs (when operated at 4.19 MHz), switchable at 3 levels On-chip memory ROM 12160 × 8 (µPD75112(A)), 16256 × 8 (µPD75116(A)) RAM 512 × 4 General register 4 bits × 8 × 4 banks (memory mapping) Accumulator Three accumulated in compliance with controlled date lengths •1-bit accumulator (CY), 4-bit accumulator (A), 8-bit accumulator (XA) Input/output port 58 in total • CMOS input pin : 10 • CMOS input/output pin (LED direct drive enable) : 32 • Intermediate withstand voltage N-ch open drain : 12 input/output pin (bit-wise pull-up resistor inscorporation possible) • Comparator input pin (4-bit accuracy) : 4 Timer/counter • 8-bit timer/event counter × 2 • 8-bit basic interval timer (applicable to watchdog timer) Serial interface • 8-bits • First LSB/first MSB switchable • Two transfer modes (transmit and receiver/receive dedicated mode) Vector interrupt External : 3, Test input External : 2 Standby • STOP/HALT mode Operating temperature range -40 to +85°C Operating voltage 2.7 to 6.0 V Others • On-chip power-on reset circuit (mask option) • On-chip bit contol memory (bit sequential buffer) Package • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 20 mm) Internal : 4 µPD75112(A), 75116(A) CONTENTS 1. Pin Configuration (Top View)............................................................................................... 4 2. Block Diagram......................................................................................................................... 6 3. Pin Functions......................................................................................................................... 3.1 3.2 3.3 3.4 3.5 7 Port Pins...................................................................................................................................................... 7 Non-Port Pins............................................................................................................................................... 8 Pin Input/Output Circuits............................................................................................................................ 9 Recommended Connection of Unused Pins............................................................................................. 10 Caution Relating to Use of P00/INT4 Pin and RESET Pin........................................................................ 10 4. Memory Configuration............................................................................................................. 11 5. Peripheral Hardware Functions.............................................................................................. 14 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Digital Input/Output Port......................................................................................................................... 14 Clock Generator......................................................................................................................................... 14 Clock Output Circuit.................................................................................................................................. 16 Basic Interval Timer.................................................................................................................................... 16 Timer/Event Counter................................................................................................................................. 17 Serial Interface............................................................................................................................................ 19 Programmable Threshold Port (Analog Input Port)............................................................................... 21 Bit Sequential Buffer................................................................................................................................... 22 Power-On Flag (Mask Option).................................................................................................................... 22 6. Interrupt Functions.................................................................................................................. 23 7. Standby Functions ............................................................................................................... 25 8. Reset Functions..................................................................................................................... 26 9. Instruction Set....................................................................................................................... 29 10. Mask Option Selection.......................................................................................................... 37 11. Electrical Specifications........................................................................................................ 38 12. Package Information ............................................................................................................ 48 13. Recommended Soldering Conditions ................................................................................. 51 APPENDIX A. Diffeences between µPD751××(A) Series Products and Related PROM Products.............................................................................. 52 APPENDIX B. Development Tools ............................................................................................ 53 APPENDIX C. Related Documentations ................................................................................... 54 3 µPD75112(A), 75116(A) 1. Pin Configuration (Top View) 64-Pin Plastic Shrink DIP (750 mil) 1 64 V SS P12/INT2 2 63 P90 P11/INT1 3 62 P91 P10/INT0 4 61 P92 PTH03 5 60 P93 PTH02 6 59 P80 PTH01 7 58 P81 PTH00 8 57 P82 TI0 9 56 P83 TI1 10 55 P70 P23 11 54 P71 P22/PCL 12 53 P72 P21/PTO1 13 52 P73 P20/PTO0 14 51 P60 P03/SI 15 50 P61 49 P62 48 P63 µPD75112CW(A)-××× µPD75116CW(A)-××× 4 P13/INT3 P02/SO 16 P01/SCK 17 P00/INT4 18 47 X1 P123 19 46 X2 P122 20 45 RESET P121 21 44 P50 P120 22 43 P51 P133 23 42 P52 P132 24 41 P53 P131 25 40 P40 P130 26 39 P41 P143 27 38 P42 P142 28 37 P43 P141 29 36 P30 P140 30 35 P31 NC 31 34 P32 V DD 32 33 P33 µPD75112(A), 75116(A) P130 P143 P142 P141 P140 NC V DD P33 P32 P31 P30 P43 P42 64-Pin Plastic QFP (14 × 20 mm) 64 63 62 61 60 59 58 57 56 55 54 53 52 2 50 P132 3 49 P133 P52 4 48 P120 P51 5 47 P121 P50 6 46 P122 RESET 7 45 P123 X2 8 44 P00/INT4 X1 9 43 P01/SCK 42 P02/SO 41 P03/SI 40 P20/PTO0 P40 P53 µPD75112GF(A)-×××-3BE P131 1 µPD75116GF(A)-×××-3BE 51 P41 P63 10 P62 11 P61 12 P60 13 39 P21/PTO1 P73 14 38 P22/PCL P72 15 37 P23 P71 16 36 T11 P70 17 35 T10 P83 18 34 PTH00 P82 19 33 PTH01 PTH02 PTH03 P10/INT0 P11/INT1 P12/INT2 V SS P13/INT3 P90 P91 P92 P93 P80 P81 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name ★ P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83 P90-P93 P120-P123 P130-P133 P140-P143 : : : : : : : : : : : : : Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8 Port9 Port12 Port13 Port14 SCK SO SI PTO0, PTO1 PCL PTH00-PTH03 INT0, INT1, INT4 INT2, INT3 TI0, TI1 X1, X2 RESET NC VDD VSS : : : : : : : : : : : : : : Serial Clock Serial Output Serial Input Programmable Timer Output Programmable Clock Programmable Threshold Input External Vectored Interrupt Input External Test Input Timer Input Clock Oscillation Reset No Connection Positive Power Supply Ground 5 INTBT PROGRAM CY ALU COUNTER (14) TIMER/EVENT COUNTER #0 TI0 PTO0/P20 PORT0 4 P00-P03 PORT1 4 P10-P13 PORT2 4 P20-P23 PORT3 4 P30-P33 PORT4 4 P40-P43 PORT5 4 P50-P53 PORT6 4 P60-P63 PORT7 4 P70-P73 PORT8 4 P80-P83 PORT9 4 P90-P93 PORT12 4 P120-P123 PORT13 4 P130-P133 PORT14 4 P140-P143 SP (8) BANK INTT0 TI1 TIMER/EVENT COUNTER #1 PTO1/P21 GENERAL REG. PROGRAM INTT1 MEMORY SERIAL INTERFACE 12160 × 8 BITS ( µPD75112(A)) INTSIO 16256 × 8 BITS ( µPD75116(A)) SI/P03 SI/P02 ROM DECODE RAM AND SCK/P01 DATA MEMORY CONTROL 512 × 4 BIT INT0/P10 INT1/P11 INTERRUPT INT2/P12 CONTROL INT3/P13 fX/2 N INT4/P00 PTH00-PTH03 4 PROGRAMMABLE THRESHOLD PORT # 0 CLOCK OUTPUT CONTROL PCL/P22 CLOCK DIVIDER CLOCK GENERATOR X1 X2 CPU CLOCK STAND BY CONTROL Φ VDD VSS RESET µPD75112(A), 75116(A) BASIC INTERVAL TIMER 2. Block Diagram 6 BIT SEQ. BUFFER(16) µPD75112(A), 75116(A) 3. Pin Functions 3.1 Port Pins Function Pin Name Input/ Output Dual Function Pin P00 Input INT4 P01 Input/output SCK F P02 Input/output SO E P03 Input SI B P10 Input INT0 P11 INT1 P12 INT2 P13 INT3 P20 Input/output PTO0 P21 PTO1 P22 PCL 4-bit input port (PORT0) 8-Bit I/O At Reset I/O Circuit Type *1 × Input B 4-bit input port (PORT1) 4-bit input/output port (PORT2) × Input B Input E Input E Input E Input E Input E Input E Input E Input E Input*2 M P23 P30 to P33 Input/output Programmable 4-bit input/output port (PORT3) Bit-wise input/output setting enable P40 to P43 Input/output 4-bit input/output port (PORT4) P50 to P53 Input/output 4-bit input/output port (PORT5) P60 to P63 Input/output Programmable 4-bit input/output port (PORT6) Bit-wise input/output setting enable P70 to P73 Input/output 4-bit input/output port (PORT7) P80 to P83 Input/output 4-bit input/output port (PORT8) P90 to P93 Input/output 4-bit input/output port (PORT9) P120 to P123 Input/output N-ch open drain 4-bit input/ output port (PORT12) Bit-wise pull-up resistor incorporation enable (mask option) 2 V withstand for open drain P130 to P133 Input/output N-ch open drain 4-bit input/ output port (PORT13) Bit-wise pull-up resistor incorporation enable (mask option) 12 V withstand for open drain Input*2 M P140 to P143 Input/output N-ch open drain 4-bit input/output port (PORT14) Bit-wise pull-up resistor incorporation enable (mask option) 12 V withstand for open drain Input*2 M ● ● ● ● * 1: Circles indicate Schmitt trigger inputs. 2: High impedance for open drain High level for on-chip pull-up resistors 7 µPD75112(A), 75116(A) 3.2 Non-Port Pins Input/Output Dual Function Pin Function At Reset I/O Circuit Type*1 PTH00 to PTH03 Input Threshold voltage ariable 4-bit analogy input port. N TI0 Input External event pulse input for the timer/event counter or edge detect vector interrupt input. 1-bit input enable. B TI1 PTO0 Input/output P20 Timer/event counter output. Input E P21 PTO1 SCK Input/output P01 Serial clock input/output. Input F SO Input/output P02 Serial data output. Input E SI Input P03 Serial data input. Input B INT4 Input P00 Edge detect vector interrupt input (for detecting both rising and falling edges). Input B INT0 Input P10 Edge detect vector interrupt input (detected edge selectable). Input B Edge detect testable input (for rising edge detection). Input B Clock output. Input E P11 INT1 INT2 Input INT3 PCL P13 Input/output P22 Crystal/ceramic connect pin (system clock oscillation). In case with the external clock, input a signal to X1 and the antiphase to X2. X1, X2 RESET P12 Input System reset input (low level active). NC*2 No Connection VDD Positive power supply. VSS GND potential. * 1: Circles indicate Schmitt trigger inputs. 2: When the PWB is shared with the µPD75P116, connect the NC pin to VDD directly. 8 B µPD75112(A), 75116(A) 3.3 Pin Input/Output Circuits µPD75116(A) pin input/output crcuit are shown in schematic form. Figure 3-1 Pin Input/Output Circuits Type A Type F VDD data IN/OUT Type D P-ch output disable IN Type B N-ch Input/output circuit consisting of a Type D push-pull output and a Type B Schmitt-triggered input. CMOS specified input buffer Type B Type M IN VDD Pull-Up Register (Mask Option) Schmitt triggered-input with hysteresis characteristics IN/OUT Type D data N-ch (+6 V Withstand) data VDD output disable P-ch OUT output disable N-ch Middle-High Voltage Input Buffer (+6 V Withstand) Push-pull output which can be set at output high impedance (with both P-ch an N-ch set to OFF) Type N Comparator Type E IN data + IN/OUT Type D – output disable Type A VREF (Threshold Voltage) Input/output circuit consisting of a Type D push-pull output and a Type A input buffer 9 µPD75112(A), 75116(A) 3.4 Recommended Connection of Unused Pins Pin PTH00 to PTH03 Recommended Connecting Method Connect to VSS or VDD 3.5 Caution Relating to Use of P00/INT4 Pin and RESET Pin In addition to the functions described in sections 3.1 and 3.2, the P00/INT4 pin and the RESET pin have the function to set the IC test mode for testing the µPD75116(A) internal operations. TI0 TI1 P00 Connect to VSS P01 to P03 Connect to VSS or VDD P10 to P13 Connect to VSS P20 to P23 Input state : Connect to VSS or VDD Output state : Leave open P30 to P33 When a voltage larger than VDD is applied to one of these two pins, the test mode is set. Thus, if noise exceeding VDD is applied even during normal operations, the test mode is set and normal operations may be discontinued. For example, if a cable from the P00/INT4 or RESET pin is too long, inter-wiring noise may be applied to the pin, the pin voltage may become larger than VDD, causing malfunctioning. P40 to P43 Thus, carry out wiring to minimize inter-wiring noise. If the noise cannot be suppressed completely, carry out the following countermeasure against noise using an externally mounted component. P50 to P53 P60 to P63 P70 to P73 o Connect a diode with low VF (max 0.3 V)between VDDs P80 to P83 VDD P90 to P93 Diode with low VF P120 to P123 VDD P130 to P133 P00/INT4, RESET P140 to P143 RESET Connect to VDD*1 NC Leave open or connect to VDD*2 o Connect acapacitor between VDDs *1: Only when a power-on reset generator is built in by mask option, connect t VDD. 2: When the PWB is shared with the µPD75P116, connect the NC pin to VDD directly. VDD VDD P00/INT4, RESET 10 µPD75112(A), 75116(A) • 0020H to 007FH: Table area to be referred to by the GETI instruction • Data Memory • Data area 512 × 4 bits (000H to 1FFH) • Peripheral hardware area 128 × 4 bits (F80H to FFFH) 4. Memory Configuration • Program Memory (ROM) 12160 × 8 bits (0000H to 2F7FH): µPD75112(A) 16256 × 8 bits (0000H to 3F7FH): µPD75116(A) • 0000H to 0001H: Vector table for writing the program start address by reset • 0002H to 000BH: Vector table for writing the program start address by interrupt Figure 4-1 Program Memory Map (µPD75112(A)) Address 7 0 6 0000H MBE RBE Internal Reset Start Address (High-Order 6 Bits) 0002H MBE RBE INTBT/INT4 Start Address Internal Reset Start Address (Low-Order 8 Bits) INTBT/INT4 Start Address (High-Order 6 Bits) (Low-Order 8 Bits) 0004H MBE RBE INT0/INT1 Start Address 0006H MBE RBE INTSIO Start Address (High-Order 6 Bits) INTSIO Start Address (Low-Order 8 Bits) INT0/INT1 Start Address 0008H 000AH (High-Order 6 Bits) (Low-Order 8 Bits) MBE RBE INTT0 Start Address (High-Order 6 Bits) INTT0 Start Address (Low-Order 8 Bits) MBE RBE INTT1 Start Address (High-Order 6 Bits) INTT1 Start Address (Low-Order 8 Bits) ≈ ≈ CALL !addr Instruction Subroutin Entry Address CALLF ! faddr Instruction Entry Address BRCB ! caddr Instruction Branch Address 0020H GETI Instruction Reference Table 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H ≈ ≈ ≈ ≈ ≈ ≈ BRCB !caddr Instruction Branch Address ≈ ≈ BRCB !caddr Instruction Branch Address BR !addr Instruction Branch Address BR $addr Instruction Relative Branch Address (-15 to +16) Branch Address Subroutine Entry Address by GETI Instruction 2F7FH Remarks: In all other cases, the program can be branched by the BR PCDE and BR PCXA instructions to an address with only the lower 8 bits of PC changed. 11 µPD75112(A), 75116(A) Figure 4-2 Program Memory Map (µPD75116(A)) Address 7 0000H 0 6 MBE RBE Internal Reset Start Address (High-Order 6 Bits) 0002H MBE RBE INTBT/INT4 Start Address 0004H MBE RBE INT0/INT1 Start Address Internal Reset Start Address (Low-Order 8 Bits) INTBT/INT4 Start Address INT0/INT1 Start Address 0006H 0008H 000AH (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) MBE RBE INTSIO Start Address (High-Order 6 Bits) INTSIO Start Address (Low-Order 8 Bits) MBE RBE INTT0 Start Address (High-Order 6 Bits) INTT0 Start Address (High-Order 6 Bits) MBE RBE INTT1 Start Address (High-Order 6 Bits) INTT1 Start Address (Low-Order 8 Bits) ≈ ≈ CALL !addr Instruction Subroutin Entry Address CALLF ! faddr Instruction Entry Address 0020H BRCB ! caddr Instruction Branch Address GETI Instruction Reference Table 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H ≈ ≈ ≈ ≈ ≈ ≈ BRCB !caddr Instrucion Branch Address ≈ ≈ BRCB !caddr Instrucion Branch Address ≈ ≈ BRCB !caddr Instruction Branch Address 3F7FH Remarks: In all other cases, the program can be branched by the BR PCDE and BR PCXA instructions to an address with only the lower 8 bits of PC changed. 12 BR !addr Instruction Branch Address BR $addr Instruction Relative Branch Address (-15 to –1 +2 to +16) Branch Address Subroutine Entry Address by GETI Instruction µPD75112(A), 75116(A) Figure 4-3 Data Memory Map Data Memory Memory Bank 000H General Regoster Area (32 × 4) 01FH Bank 0 Stack Area 256 × 4 Data Area Static RAM (512 × 4) 0FFH 100H 256 × 4 Bank 1 1FFH Not Incorporated F80H Peripheral Hardware Area 128 × 4 Bank 15 FFFH 13 µPD75112(A), 75116(A) 5. Peripheral Hardware Functions 5.1 Digital Input/Output Port The digital input/output port has the following tree types. • CMOS input (PORT0, 1) : 8 • CMOS input/output (PORT 2 to PORT 9) : 32 • N-ch open-drain input/output (PORT 12 to PORT 14): 12 Total 52 Table 5-1 Functions of Digital Ports Port (Code) Functions Operations and Features Remarks Share the pins with SI, SO, SCK and INT0 to 4. PORT0 PORT1 4-bit input Read or test always enable irrespectively of the operating mode of dual-function pins. PORT3 PORT6 4-bit input/ output Can be set bit-wise to the input or output mode. PORT2 PORT4 PORT5 PORT7 PORT8 PORT9 PORT12 PORT13 PORT14 4-bit input/ output (N-ch opendrain, 12 V withstand voltage) Can be set in 4-bit units to the input or output mode. Ports 4 and 5, 6 and 7, 8 and 9 can form pairs and data can be input/output in 8-bit units. Port 2 shares the pin with PTO0, PTO1 and PCL. Can be set in 4-bit units the input or output mode. Ports 12 and 13 can form a pair and data can be input/output in 8bit units. On-chip pull-up registers can be specified bit-wise by mask option. 5.2 Clock Generator The clock generator is a circuit which supplies the CPU and peripheral hardware with various clocks and controls the CPU operating mode. The instruction execution time can be changed. • 0.95 µs/1.91 µs/15.3 µs (at 4.19 MHz operation) 14 µPD75112(A), 75116(A) Figure 5-1 Block Diagram of Clock Generator ★ • Basic Interval Timer (BT) • Clock Generator • Timer/Event Counter • Serial Interface • Clock Output Circuit 1/8 to 1/4096 System Clock Oscillator fxx or Frequency Divider fx 1/2 1/16 Oscillation Stop Frequency Divider Selector 1/4 PCC Φ • CPU • Clock Output Circuit PCC0 PCC1 Internal Bus 4 HALT F/F PCC2 S HALT* PCC3 STOP* R PCC2, PCC3 Crear STOP F/F Q Q Wait Release Signal from BT S RES(Internal Reset) Signal R Remarks 1: 2: 3: 4: 5: 6: Standby Release Signal from the Interrupt Control Circuit fXX=crystal/ceramic oscillator frequency. fX=external clock frequency. Φ=CPU clock *indicates instruction execution. PCC (processor clock control register) 1 clock cycle (tCY) of Φ is 1 michine cycle of the instruction. For tCY, see the AC characteristics in the 11."Electrical Specifications". 15 µPD75112(A), 75116(A) 5.3 Clock Output Circuit The clock output circuit is a circuit to generate clock pulses from the P22/PCL pin. It is used to supply the peripheral LSIs with clock pulses. •Clock output (PCL):Φ, 524 kHz, 262 kHz (at 4.19 MHz operation) The clock output cicuit configuration is shown as the following. Figure 5-2 Clock Output Circuit Configuration From the Clock Generator Φ fxx/2 3 fxx/2 4 Output Buffer Selector P22/PCL PORT2.2 CLOM3 0 P22 Output Latch CLOM1 CLOM0 CLOM 4 Internal Bus 5.4 Basic Interval Timer The basic interval timer has the following functions; • Interval timer operation to generate reference time interrupts • Watchdog timer application to detect program overrun • Wait time selection and count when the standby mode is released • Count content read 16 PMGB Bit 2 Port 2 Input/ Output Mode Specification Bit µPD75112(A), 75116(A) Figure 5-3 Basic Interval Timer Configuration From the Clock Generator Clear Clear fxx/2 5 fxx/2 7 fxx/2 9 3 3 *SET1 BT Interrupt Request Flag BT fxx/2 12 BTM3 Set Basic Interval Timer (8-Bit Frequency Divider) MPX BTM2 BTM1 IRQBT Vector Interrupt Request Signal Wait Release Signal When the Standby Mode is Released BTM0 BTM 8 4 Internal Bus Remark: * indicates instruction execution. 5.5 Timer/Event Counter The µPD75116(A) has a two-channel on-chip timer/ event counters. Channels 0 and 1 of the timer/event counter have the same configuration and functions. They differ only in the selectable count pulse (CP) and the function of supplying clocks to the serial interface. The timer/event counter has the following functions: • Programmable interval timer operation • Output of square wave having any selected frequency to PTOn pin • Event counter operation • Use of TIn pin as an external interrupt input pin • Output of TIn pin input divided by N to PTOn pin (frequency divider operation) • Serial shift clock supply to the serial interface circuit (channel 0 only) • Count status read function 17 *1 SET 1 TMn 8 8 TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0 TMODn TOEn TO Enable Flag Modulo Register (8) TIn PORT2.n P2n Output Latch Match TOUT F/F Comparator (8) 8 PGMB Bit 2 Port2 Input/ Output Mode *3 To Serial Interface TOFn 8 Input Buffer TOn TO Selector Output Buffer P2n/PTOn Tn TIn *2 From Clock Generator Count Register (8) Edge Detector CP MPX INTTn IRQTn Set Signal Clear TMn1 Timer Operation Start RES * 1: SET1: Instruction execution 2: Refer to Figure 5-1 3: Only channel 0 of the time/event counter can output a signal to the serial interface TMn0 IRQTn Clear Signal µPD75112(A), 75116(A) 8 Figure 5-4 Block Diagram of Timer/Event Counter (n=0, 1) 18 Internal Bus µPD75112(A), 75116(A) 5.6 Serial Interface The µPD75116(A) incorporates the clock synchronous 8-bit serial interface. The serial interface has the following two modes. • Operation stop mode • 3-wire serial I/O mode (MSB/LSB top switching possible) Connection with the µPD75116(A) and the 75X series, 78K series and various I/O devices is possible in the 3wire serial I/O mode. 19 8 SIO0 SET1 * SIO7 SIOM SIO P03/SI SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0 Shift Register (8) P02/SO Over Flow Serial Clock Counter (3) INTSIO IRQSIO Set Signal Clear IRQSIO Clear Signal Serial Start P01/SCK R Q Φ S fxx/2 MPX 4 fxx/210 TOF 0 (From Timer Channel 0) *: SET1: Instruction execution µPD75112(A), 75116(A) 8 8 Figure 5-5 Block Diagram of Serial Interface 20 Internal Bus µPD75112(A), 75116(A) 5.7 ProgrammableThreshold Port (Analog Input Port) The µPD75116(A) is equipped with 4-bit analog input pins (PTH00 to PTH03) capable of changing the threshold voltage. These pins are configured as shown in Figure 5-6. Sixteen threshold voltage (VREF) values (VDD × 0.5 -VDD × 16 15.5 ) are available and analog signals can be directly 16 input. The analog input port can also be used as a digital 7.5 signal input port by selecting VDD × 16 for VREF. Figure 5-6 Block Diagram of Programmable Threshold Port Input Buffer PTH00 + – PTH01 Programmable Threshold Port Input Latch (4) + – PTH02 + – PTH03 + Internal Bus – Operation Stop PTH0 VDD PTHM7 1 R 2 PTHM6 R PTHM5 R MPX VREF PTHM4 8 PTHM3 PTHM2 1 R 2 4 PTHM1 PTHM0 PTHM 21 µPD75112(A), 75116(A) 5.8 Bit Sequential Buffer ... 16 bit The bit sequential buffer is a special data memory for bit control. Since this buffer can easily operate bits by sequentially changing address and bit specifications, it can be conveniently be used for bit-wise processing of data having long bit lengths. Figure 5-7 Bit Sequential Buffer Format Address Bit FC3H 3 Symbol L Register 2 1 FC2H 0 3 BSB3 L=F 2 1 FC1H 0 3 BSB2 L=C L=B 2 1 3 BSB1 L=8 L=7 INCS L Remarks: In pmen. @L addressing, the specified bit moves in accordance with the L register. 5.9 Power-On Flag (Mask Option) The power-on flag (PONF) is only set (1) when the power-on reset circuit is activated and the power-on reset signal is generated (see Figure 8-1). PONF is mapped on bit 0 at address FD1H of the data memory space and is manipulated by a bit manipulation instruction However, it cannot be set(1) by the SET1 instruction. 2 1 0 BSB0 L=4 L=3 DECS L 22 FC0H 0 L=0 µPD75112(A), 75116(A) 6. Interrupt Functions There are seven types of interrupt sources for the µPD75116(A) to allow multi-interruption with priority. The µPD75116(A) is also provided with two types of edge detection testable inputs. The µPD75116 interrupt control circuit has the following functions; • Hardware controlled vector interrupt function which enables to control by the interrupt enable flag (IE×××) and the interrupt master enable flag (IME) whether an interrupt should be enabled. • Interrupt start address can be set freely. • Multiple interrupt function which enables to specify priority by the interrupt priority select register (IPS). • Interrupt request flag (IRQ×××) test function (interrupt generation can be checked by the software). • Standby mode release (the interrupt to be released can be selected by the interrupt enable flag). 23 2 2 IM1 IM0 INT BT INT4 /P00 INT0 /P10 INT1 /P11 INT2 /P12 INT3 /P13 Edge Detection Circuit Edge Detection Circuit Edge Detection Circuit Interrupt Enable Flag (IE × × ×) IRQBT (IME) 2 IPS IST Decoder IRQ4 IRQ0 IRQ1 Priority Control Circuit INTSIO IRQSIO INTT0 IRQT0 INTT1 IRQT1 Edge Detection Circuit Edge Detection Circuit 4 9 Vector Table Address Generator IRQ2 IRQ3 Interrupt Request Flag Standby Release Signal µPD75112(A), 75116(A) Figure 6-1 Block Diagram of Interrupt Control Circuit 24 Internal Bus µPD75112(A), 75116(A) 7. Stanby Functions Two types of standby modes (STOP and HALT modes) are available for the µPD75116(A) to decrease power consumption during standby for program. Table 7-1 Operation Statuses in Standby Mode STOP Mode HALT Mode Set instruction STOP instruction HALT instruction Operation status Clock generator Clock oscillation stop Only CPU clock Φ stop Basic interval timer Operation stop Operation (IRQBT set at reference time intervals) Serial interface Operation enabled only when external SCK input and TO0 clock are set for serial clocks (when timer/event counter 0 is set to external TI0 input) is selected Operation enabled when aclock other than Φ is specified for the serial clock Timer/event counter Operation enabled only when TIn pin input is specified for the count clock Operation enabled Clock output circuit Operation stop Clock other than CPU clock Φ enabled for output CPU Operation stop Operation stop Release signal Interrupt request signal enabled by interrupt enable flag or RESET input 25 µPD75112(A), 75116(A) 8. Reset Functions The reset signal (RES) generator is configured as shown in Figure 8-1. Figure 8-1 Reset Signal Generator RESET Internal Reset Signal (RES) Mask Option Power-On Reset Circuit SWB SWA Power-On Flag(PONF) *: 26 PONF setting (1) by SET1 instruction is not possible. Bit Control Instruction Execution * Internal Bus µPD75112(A), 75116(A) The power-on reset circuit generates the internal reset signal by rising of supply voltage. This pulse is used in the three ways according to the specification of mask option of SWA and SWB shown in Figure 8-1 (refer to "10. Mask Option Selection"). Reset operations are shown in Figures 8-2 and 8-3. Figure 8-2 Reset Operation by Power-on Reset Supply Voltage Wait * (Approx. 31.3 ms:4.19 MHz) 0V Internal Reset Signal (RES) HALT Mode Operating Mode Internal Reset Operation Figure 8-3 Reset Operation by Reset Input Wait * (Approx. 31.3 ms:4.19 MHz) RESET Input Operation or Standby Mode HALT Mode Operating Mode Internal Reset Operation *: The wait time does not include a time from the generation of RES signal to the start of oscillation. Each hardware status after reset operation is shown in Table 8-1. 27 µPD75112(A), 75116(A) Table 8-1 Hardware Statuses after Reset Hardware Lower 6 bits of address 0000H of the program memory are set to PC13 to PC8 and the content of address 0001H is set to PC7 to PC0. Program counter (PC) PWS RESET Input in Standby Mode RESET Input in Power-On Reset or Operation same as left Hold Undefined Skip flag (SK0 to SK2) 0 0 Interrupt status flag (IST0, 1) 0 0 Bank enable flags (MBE, RBE) Bits 6 and 7 of address 0000H of the program memory are set to RBE and MBE, respectively. Carry flag (CY) same as left Undefined Undefined Hold *1 Undefined General registers (X, A, H, L, D, E, B, C) Hold Undefined Bank select registers (MBS, RBS) 0, 0 0, 0 Undefined Undefined 0 0 0 0 FFH FFH 0 0 0, 0 0, 0 Hold Undefined Mode register (SIOM) 0 0 Clock generator, clock output circuit Processor clock control register (PCC) 0 0 Clock output mode register (CLOM) 0 0 Interrupt Interrupt request flag (IRQ×××) Reset (0) Reset (0) Interrupt enable flag (IE×××) 0 0 Priority select resister (IPS) 0 0 INT0, 1 mode resisters (IM0, IM1) 0, 0 0, 0 Output buffer Off Off Output latch Clear (0) Clear (0) 0 0 Undefined Undefined 0 0 Hold 1 or undefined *2 0 0 Stack pointer (SP) Data memory (RAM) Basic interval timer Counter (BT) Mode register (BTM) Timer/ event counter (n = 0, 1) Counter (Tn) Modulo register (TMODn) Mode register (TMn) TOEn, TOFn Serial interface Digital port Shift register (SIO) Input/output mode registers (PMGA, PMGB, PMGC) Analog port PTH00 to PTH03 input latches Mode register (PTHM) Power-on flag (PONF) Bit sequential buffers (BSB0 to BSB3) * 1: Power-on reset ................... 1 RESET input in operation ... Undefined 2: Data at addresses 0F8H to 0FDH of the data memory becomes undefined due to RESET input. 28 µPD75112(A), 75116(A) 9. Instruction Set Description Method Identifier (1) Operand identifier and description method reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L In the operand column of each instruction, describe the corresponding operand in accordance with the description method for the operand identifier of the instruction (refer to the "RA75X Assembler Package User's Manual Language Volume" (EEU-730) for details). If more than one description method is available, select one of them. Capital alphabetic letters, plus and minus signs are key words. Describe them as they are. rp rp1 rp2 rp’ rp’1 XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA’, BC’, DE’, HL’ BC, DE, HL, XA’, BC’, DE’, HL’ rpa rpa1 HL, HL+, HL-, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or label* 2-bit immediate data or label fmem FB0H to FBFH and FF0H to FFFH immediate data or labels FC0H to FFFH immediate data or labels In the case of immediate data, describe appropriate numeric values or labels. Symbols of various registers and flags can be described as labels instead of mem, fmem, pmem, bit, etc. (Refer to the "µPD751×× Series User’s Manual (IEM922)" for details). Labels which can be described are limited for fmem and pmem. pmem addr µPD75112(A) 0000H to 2F7FH immediate data or labels µPD75116(A) 0000H to 3F7FH immediate data or labels caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20H to 7FH immediate data (bit = 0) or labels PORTn IE××× RBn MBn PORT0 to PORT9, PORT12 to PORT14 IEBT, IESIO, IET0, IET1, IE0 to IE4 RB0 to RB3 MB0, MB1, MB15 *: In the case of 8-bit data processing, only even address can be described for “mem”. 29 µPD75112(A), 75116(A) (2) Legend in the description of operations A B C D E H L X XA BC DE HL XA’ BC’ DE’ HL’ PC SP CY PSW MBE RBE PORTn IME IPS IE××× RBS MBS PCC . (×× ) ××H 30 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : A register; 4-bit accumulator B register C register D register E register H register L register X register Register pair (XA); 8-bit accumulator Register pair (BC) Register pair (DE) Register pair (HL) Extended register pair (XA’) Extended register pair (BC’) Extended register pair (DE’) Extended register pair (HL’) Program counter Stack pointer Carry flag; bit accumulator Program status word Memory bank enable flag Register bank enable flag Port n (n = 0 to 9, 12 to 14) Interrupt mask enable flag Interrupt priority select register Interrupt enable flag Register bank select register Memory bank select register Processor clock control register Address and bit division Content addressed by ×× Hexadecimal data µPD75112(A), 75116(A) (3) Description of symbols in the addressing area column *1 MB=MBE•MBS (MBS=0, 1, 15) *2 MB=0 *3 MBE=0 : MB=0 (00H-7FH) MB=15 (80H-FFH) MBE=1 : MB=MBS (MBS=0, 1, 15) *4 MB=15, fmem=FB0H-FBFH, FF0H=FFFH *5 MB=15, pmem=FC0H-FFFH *6 addr=0000H-2F7FH (µPD75112(A)) =0000H-3F7FH (µPD75116(A)) *7 addr=(Current PC) -15 to (Current PC) +16 *8 caddr=0000H-0FFFH (PC13, PC12=00B =1000H-1FFFH (PC13, PC12=01B =2000H-2F7FH (PC13, PC12=10B =2000H-2FFFH (PC13, PC12=10B =3000H-3F7FH (PC13, PC12=11B *9 faddr=0000H-07FFH *10 taddr=0020H-007FH Data Memory Addressing : : : : : µPD75112(A), 116(A)) or µPD75112(A), 116(A)) or µPD75112(A)) or µPD75116(A)) or µPD75116(A)) Remarks 1: MB indicates an accessible memory bank. 2: In *2, MB = 0 irrespectively of MBE and MBS. 3: In *4 and *5, MB = 15 irrespectively of MBE and MBS. 4: *6 to *10 indicate addressable areas. Program Memory Addressing One machine cycle is equal to one cycle (=tCY)of CPU clock. Three values are available for the one machine cycle by PCC setting. (4) Description of machine cycle column S indicates the number of machine cycles required for the instruction having skip function to execute skip operation. The value of S varies as follows: • When no skip ............................................. S = 0 • When 1-byte or 2-byte instruction is skipped ................................................. S = 1 • When 3-byte instruction (BR !addr, CALL !addr instructions) is skipped ............................. S = 2 Note: GETI instruction is skipped in one-machine cycle. 31 µPD75112(A), 75116(A) Instructions Transfer Mnemonic MOV XCH Table Reference Bit Transfer 32 MOVT MOV1 No. of Bytes Machine Cycle A, #n4 1 1 A←n4 reg1, #n4 2 2 reg1←n4 XA, #n8 2 2 XA←n8 Stack A HL, #n8 2 2 HL←n8 Stack B rp2, #n8 2 2 rp2←n8 A, @HL 1 1 A←(HL) *1 A, @HL+ 1 2+S A←(HL), then L←L+1 *1 L=0 A, @HL- 1 2+S A←(HL), then L←L-1 *1 L=FH A, @rpa1 1 1 A←(rpa1) *2 XA, @HL 2 2 XA←(HL) *1 @HL, A 1 1 (HL)←A *1 @HL, XA 2 2 (HL)←XA *1 A, mem 2 2 A←(mem) *3 XA, mem 2 2 XA←(mem) *3 mem, A 2 2 (mem)←A *3 mem, XA 2 2 (mem)←XA *3 A, reg 2 2 A←reg XA, rp' 2 2 XA←rp' reg1, A 2 2 reg1←A rp'1 XA 2 2 rp'1←XA A, @HL 1 1 A↔(HL) *1 A, @HL+ 1 2+S A↔(HL), then L←L+1 *1 L=0 A, @HL- 1 2+S A↔(HL), then L←L-1 *1 L=FH A, @rpa1 1 1 A↔(rpa1) *2 XA, @HL 2 2 XA↔(HL) *1 A, mem 2 2 A↔(mem) *3 XA, mem 2 2 XA↔(mem) *3 A, reg1 1 1 A↔reg1 XA, rp' 2 2 XA↔rp' XA, @PCDE 1 3 XA←(PC13-8+DE)ROM XA, @PCXA 1 3 XA←(PC13-8+XA)ROM CY, fmem. bit 2 2 CY←(fmem.bit) *4 CY, pmem. @L 2 2 CY←(pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem. bit 2 2 CY←(H+mem3-0.bit) *1 fmem. bit, CY 2 2 (fmem.bit)←CY *4 pmem. @L, CY 2 2 (pmem7-2+L3-2.bit(L1-0))←CY *5 @H+mem. bit, CY 2 2 (H+mem3-0.bit)←CY *1 Operand Operation Addressing Area Skip Condition Stack A µPD75112(A), 75116(A) Instructions Mnemonic Arithmetic ADDS A, #n4 1 1+S A←A+n4 Carry XA, #n8 2 2+S XA←XA+n8 Carry A, @HL 1 1+S A←A+(HL) XA, rp' 2 2+S XA←XA+rp' Carry rp'1, XA 2 2+S rp'1←rp'1+XA Carry A, @HL 1 1 A, CY←A+(HL)+CY XA, rp' 2 2 XA, CY←XA+rp'+CY rp'1, XA 2 2 rp'1, CY←rp'1+XA+CY A, @HL 1 1+S A←A−(HL) XA, rp' 2 2+S XA←XA-rp' borrow rp'1, XA 2 2+S rp'1←rp'1-XA borrow A, @HL 1 1 A, CY←A-(HL)-CY XA, rp' 2 2 XA, CY←XA-rp'-CY rp'1, XA 2 2 rp'1, CY←rp'1-XA-CY A, #n4 2 2 A←A∧n4 A, @HL 1 1 A←A∧(HL) XA, rp' 2 2 XA←XA∧rp' rp'1, XA 2 2 rp'1←rp'1∧XA A, #n4 2 2 A←A∨n4 A, @HL 1 1 A←A∨(HL) XA, rp' 2 2 XA←XA∨rp' rp'1, XA 2 2 rp'1←rp'1∨XA A, #n4 2 2 A←A∀n4 A, @HL 1 1 A←A∀(HL) XA, rp' 2 2 XA←XA∀rp' rp'1, XA 2 2 rp'1←rp'1∀XA RORC A 1 1 CY←A 0, A3←CY, An-1←An NOT A 2 2 A←A INCS reg 1 1+S reg←reg+1 reg=0 rp1 1 1+S rp1←rp1+1 rp1=00H @HL 2 2+S (HL)←(HL)+1 *1 (HL)=0 mem 2 2+S (mem)←(mem)+1 *3 (mem)=0 reg 1 1+S reg←reg-1 reg=FH rp' 2 2+S rp'←rp'-1 rp'=FFH reg, #n4 2 2+S Skip if reg=n4 reg=n4 @HL, #n4 2 2+S Skip if (HL)=n4 *1 (HL)=n4 A, @HL 1 1+S Skip if A=(HL) *1 A=(HL) SUBC AND OR XOR DECS Compare Addressing Area Machine Cycle SUBS Increase/ Decrease Operation No. of Bytes ADDC Accumulator Operation Operand SKE *1 Skip Condition Carry *1 *1 borrow *1 *1 *1 *1 33 µPD75112(A), 75116(A) Instructions Compare Carry Flag Operation 34 No. of Bytes Machine Cycle XA, @HL 2 2+S Skip if XA=(HL) A, reg 2 2+S Skip if A=reg A=reg XA, rp' 2 2+S Skip if XA=rp' XA=rp' SET1 CY 1 1 CY←1 CLR1 CY 1 1 CY←0 SKT CY 1 1+S NOT1 CY 1 1 Mnemonic SKE Operand Operation Skip if CY=1 CY←CY Addressing Area *1 Skip Condition XA=(HL) CY=1 µPD75112(A), 75116(A) Instructions Memory Bit Manipulation Mnemonic SET1 CLR1 SKT SKF SKTCLR AND1 OR1 XOR1 Branch BR Operand No. of Bytes Operation Machine Cycle Addressing Area Skip Condition mem. bit 2 2 (mem.bit)←1 *3 fmem. bit 2 2 (fmem.bit)←1 *4 pmem. @L 2 2 (pmem7-2+L3-2.bit(L1-0))←1 *5 @H+mem. bit 2 2 (H+mem3-0.bit)←1 *1 mem. bit 2 2 (mem.bit)←0 *3 fmem. bit 2 2 (fmem.bit)←0 *4 pmem. @L 2 2 (pmem7-2+L3-2.bit(L1-0))←0 *5 @H+mem. bit 2 2 (H+mem3-0.bit)←0 *1 mem. bit 2 2+S Skip if (mem.bit)=1 *3 (mem.bit)=1 fmem. bit 2 2+S Skip if (fmem.bit)=1 *4 (fmem.bit)=1 pmem. @L 2 2+S Skip if (pmem7-2+L3-2.bit(L1-0))=1 *5 (pmem.@L)=1 @H+mem. bit 2 2+S Skip if (H+mem3-0.bit)=1 *1 (@H+mem.bit)=1 mem. bit 2 2+S Skip if (mem.bit)=0 *3 (mem.bit)=0 fmem. bit 2 2+S Skip if (fmem.bit)=0 *4 (fmem.bit)=0 pmem. @L 2 2+S Skip if (pmem7-2+L3-2.bit(L1-0))=0 *5 (pmem.@L)=0 @H+mem. bit 2 2+S Skip if (H+mem3-0.bit)=0 *1 (@H+mem.bit)=0 fmem. bit 2 2+S Skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem. @L 2 2+S Skip if (pmem7-2+L3-2.bit(L1-0)) =1 and clear *5 (pmem.@L)=1 @H+mem. bit 2 2+S Skip if (H+mem3-0.bit)=1 and clear *1 (@H+mem.bit)=1 CY, fmem. bit 2 2 CY ←CY∧(fmem.bit) *4 CY, pmem. @L 2 2 CY ←CY∧(pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem. bit 2 2 CY ←CY∧(H+mem3-0.bit) *1 CY, fmem. bit 2 2 CY ←CY∨(fmem.bit) *4 CY, pmem. @L 2 2 CY ←CY∨(pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem. bit 2 2 CY ←CY∨(H+mem3-0.bit) *1 CY, fmem. bit 2 2 CY ←CY∀(fmem.bit) *4 CY, pmem. @L 2 2 CY ←CY∀(pmem7-2+L3-2.bit(L1-0 )) *5 CY, @H+mem. bit 2 2 CY ←CY∀(H+mem3-0.bit) *1 PC13-0 ←addr (Most appropriate instruction is selected by assembler from among BR !addr, BRCB !caddr and BR $addr) *6 addr !addr 3 3 PC13-0 ←addr *6 $addr 1 2 PC13-0 ←addr *7 BRCB !caddr 2 2 PC13-0←PC13, 12+caddr11-0 *8 BR PCDE 2 3 PC13-0 ←PC13-8+DE PCXA 2 3 PC13-0 ←PC13-8+XA 35 µPD75112(A), 75116(A) Instructions Subroutine Stack Control Mnemonic Addressing Area 3 (SP-4)(SP-1)(SP-2)←PC11-0 (SP-3)←MBE, RBE, PC13, 12 PC13-0←addr, SP←SP-4 *6 CALLF !faddr 2 2 (SP-4)(SP-1)(SP-2)←PC11-0 (SP-3)←MBE, RBE, PC13, 12 PC13-0←00, faddr, SP←SP-4 *9 RET 1 3 MBE, RBE, PC13, 12←(SP+1) PC11-0←(SP)(SP+3)(SP+2) SP←SP+4 RETS 1 3+S RETI 1 3 PC13, 12←(SP+1) PC11-0←(SP)(SP+3)(SP+2) PSW←(SP+4)(SP+5), SP←SP+6 rp 1 1 (SP-1)(SP-2)←rp, SP←SP-2 BS 2 2 (SP-1)←MBS, (SP-2)←RBS, SP←SP-2 rp 1 1 rp←(SP-1)(SP), SP←SP-2 BS 2 2 MBS←(SP+1), RBS←(SP), SP←SP+2 2 2 IME (IPS.3)←1 2 2 IE×××←1 2 2 IME (IPS.3)←0 IE××× 2 2 IE×××←0 A, PORTn 2 2 A←PORTn XA, PORTn 2 2 XA←PORTn+1, PORTn (n=4, 6, 8, 12) PORTn, A 2 2 PORTn←4 PORTn, XA 2 2 PORTn+1, PORTn←XA (n=4, 6, 8, 12) HALT 2 2 Set HALT Mode (PCC.2←1) STOP 2 2 Set STOP Mode (PCC.3←1) NOP 1 1 No Operation RBn 2 2 RBS←n(n=0-3) MBn 2 2 MBS←n taddr 1 3 • TBR Instruction PC13-0←(taddr)4-0+(taddr+1) EI DI IN*1 OUT*1 Special Operation 3 IE××× CPU Control Machine Cycle !addr POP Input/Output No. of Bytes CALL PUSH Interrupt Control Operand SEL GETI*2 MBE, RBE, PC13, 12←(SP+1) PC11-0←(SP)(SP+3)(SP+2) SP←SP+4, then skip unconditionally Skip Condition Unconditional (n=0-9, 12-14) (n=2-9, 12-14) (n=0, 1, 15) *10 • TCALL Instruction (SP-4)(SP-1)(SP-2)←PC11-0 (SP-3)←MBE, RBE, PC13, 12 PC13-0←(taddr)5-0+(taddr+1) SP←SP-4 • When not TBR and TCALL instructions, (taddr) and (taddr+1) instructions are executed. * 1: MBE=0 or 1 and MBS=15 must be set for execution of IN/OUT instruction. , 2: TBR and TCALL instructions are assembler pseudo-instructions for GETI instruction table definition. 36 Depends on the instruction referred to. µPD75112(A), 75116(A) 10. Mask Option Selection The following mask options are available for the ★ µPD75116(A). Whether or not they should be incorporated can be selected. (1) Pins Mask Option Pin P120 to P123 Bit-wise pull-up resistor incorporation enable P130 to P133 P140 to P143 (2) Power-on reset circuit and power-on flag (PONF) One of the following three settings can be selected. Mask Option Specification Switch Selection (See Figure 8-1) Internal Reset Signal (RES) Power-on Reset Circuit Power-on Flag (PONF) SWA SWB Incorporated Incorporated ON ON Generated automatically Not incorporated Incorporated ON OFF Not generated automatically Not incorporated Not incorporated OFF OFF 37 µPD75112(A), 75116(A) 11. Electrical Specifications Absolute Maximum Ratings (Ta = 25 °C) Parameter Symbol Power supply voltage VDD Input voltage VI1 VI2 *1 Test Conditions Except for ports 12 to 14 Ports 12 to 14 On-chip pull-up resistor Open drain Output voltage VO Output current high IOH 1 pin All pins Output current low IOL *2 1 pin Total current of ports 0, 2 to 4, 12 to 14 Ratings Unit –0.3 to +7.0 V –0.3 to VDD +0.3 V –0.3 to VDD +0.3 V –0.3 to +13 V –0.3 to VDD +0.3 V Peak value –10 mA Effective value –5 mA Peak value –30 mA Effective value –15 mA Peak value 10 mA Effective value 5 mA Peak value 50 mA Effective value 25 mA Peak value 50 mA Effective value 25 mA Operation temperature Topt –40 to +85 °C Storage temperature Tstg –65 to +150 °C * 1: When applying a voltage larger than 10 V to ports 12, 13 and 14 each, set the power impedance (pull-up resistor) to 50 kΩ or more. 2: Calculate each effective value using the following expression: [Effective value]=[Peak value] × √duty Note: Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. 38 µPD75112(A), 75116(A) Operating Voltage ★ (Ta = –40 to +85 °C) Parameter MIN. MAX. Unit CPU*1 *2 6.0 V Programmable threshold port (comparator input) 4.5 6.0 V Power-on reset circuit*3 4.5 6.0 V Other hardware*1 2.7 6.0 V Test Conditions * 1: Except system clock oscillator, programmable threshold port and power-on reset circuit 2: Operating voltage range depends on the cycle time. See the AC Characteristics. 3: Whether or not it should be incorporated can be selected by mask options. See the Power-On Reset Circuit Characteristics (Mask Option). 39 µPD75112(A), 75116(A) Oscillate Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) Oscillator Recommended Constant Ceramic oscillation X1 Parameter Oscillator frequency (fXX)*1 VDD = oscillation voltage range Oscillation stabilizing time*2 Oscillation voltage range MIN. C2 Crystal oscillator C2 External clock Unit 5.0*3 MHz ms 4 4.19 5.0*3 MHz Oscillation stabilizing time*2 VDD = 4.5 to 6.0 V 10 ms 30 ms X1 input frequency (fX)*1 2.0 5.0*3 MHz X1 input high and low level widths (tXH, tXL) 100 250 ns X2 µPD74HCU04 * 1: Oscillator frequency and X1 input frequency indicate only characteristics of the oscillator. Refer to AC characteristics for the instruction execution time. 2: The oscillation stabilizing time is necessary for oscillation to stabilize after VDD reaches oscillation voltage range MIN. or the STOP mode is released. 3: When the oscillator frequency is 4.19 MHz < fXX ≤ 5.0 MHz, PCC=0011 should not be selected as instruction execution time. If PCC=0011 is selected, 1 machine cycle becomes less than 0.95 µs, with the result that the specified MIN. value of 0.95 µs cannot be observed. 40 MAX. X2 C1 X1 TYP. 2.0 2.0 Oscillator frequency (fXX)*1 X1 MIN. X2 C1 ★ Test Condition Note: When using the main system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. • Wiring should be as short as possible. • Wiring should not cross other signal lines. • Wiring should not be placed close to a varying high current. • The potential of the oscillator capacitor ground should be the same as VSS. Do not ground wiring to a ground pattern in which a high current flows. • Do not fetch a signal from the oscillator. ★ µPD75112(A), 75116(A) DC Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) Parameter Input voltage high Input vltage low Output voltage high Symbol Test Conditions MIN. 0.7VDD VDD V VIH2 Ports 0, 1, TI0, 1, RESET 0.8VDD VDD V VIH3 Ports 12 to 14 On-chip pull-upresistor 0.7VDD VDD V Open drain 0.7VDD 12 V VDD–0.5 VDD V VIH4 X1, X2 VIL1 Except for ports listed below 0 0.3VDD V VIL2 Ports 0, 1, TI0, 1, RESET 0 0.2VDD V VIL3 X1, X2 0 0.4 V VOH VDD = 4.5 to 6.0 V, IOH = –1 mA VOL VDD = 4.5 to 6.0 V VDD–1.0 V VDD–0.5 V Ports 0, 2 to 9, IOL = 5 mA 0.25 1.0 V Ports 12 to 14, IOL = 5 mA 0.40 1.0 V 0.4 V 0.5 V Except for ports listed below 3 µA X1, X2 20 µA IOL = 400µA ILIH1 VIN = VDD ILIH2 Input leakage current low ILIH3 VIN = 12 V Ports 12 to 14 (for open drain) 20 µA ILIL1 VIN = 0 V Except for X1, X2 –3 µA X1, X2 –20 µA ILIL2 Output leakage current high Output leakage current low On-chip pull-up resistor ILOH1 VOUT = VDD Except for ports listed below 3 µA ILOH2 VOUT = 12 V Ports 12 to 14 (for open drain) 20 µA ILOL VOUT = 0 V –3 µA 70 kΩ 80 kΩ RL Ports 12 to 14 VDD=5 V ±10% 15 40 10 Supply current*1 Unit Except for ports listed below VDD = 4.5 to 6.0V, IOL = 1.6 mA Input leakage current high MAX. VIH1 IOH = –100µA Output voltage low TYP. IDD1 4.19 MHz crystal oscillation C1 = C2 = 22 pF 3 9 mA VDD=3 V ±10%*3 0.55 1.5 mA VDD=5 V ±10% 600 1800 µA VDD=3 V ±10% 200 600 µA 0.1 10 µA HALT mode IDD2 IDD3 VDD=5 V ±10%*2 STOP mode, VDD = 3 V ±10% * 1: Current for the on-chip pull-up resistor, power-on reset circuit (mask option) and comparator circuit is not included. 2: When operated in the hgh-speed mode with the processor clock control resistor (PCC) set tp 0011. 3: When operated in the low-speed mode with the PCC set to 0000. 41 µPD75112(A), 75116(A) Capacitance (Ta = 25 °C, VDD = 0 V) Parameter Symbol Input capacitance Output capacitance Input/output capacitance Test Conditions CIN TYP. MIN. f = 1 MHz 0 V for pins except the measured pins COUT CIO MAX. Unit 15 pF 15 pF 15 pF TYP. MAX. Unit ±100 mV Comparator Characteristics (Ta = –40 to +85 °C, VDD = 4.5 to 6.0 V) Parameter Symbol Comparison accuracy VACOMP Test Conditions MIN. Threshold voltage VTH 0 V DD V PTH input voltage VIPTH 0 VDD V Comparator circuit consumption Set PTHM7 to "1". 1 mA Power-On Reset Circuit Characteristics (Mask Option) (Ta = –40 to +85 °C) Parameter Symbol Power-on reset operating voltage high VDDH Power-on reset operating voltage low Test Conditions MIN. TYP. MAX. Unit 4.5 6.0 V VDDL 0 0.2 V Supply voltage rise time tr 10 *1 µs Supply voltage off time toff 1 Power-on reset circuit current consumption*2 IDDPR VDD = 5 V ±10% 10 100 µA VDD = 2.5 V 2 20 µA *1: 217/fXX (31.3 ms when fXX = 4.19MHz) 2: Current flow upon power-on reset or with an on-chip power-on flag VDDH VDD VDDL toff Note: Start the power supply smoothly. 42 s tr µPD75112(A), 75116(A) AC Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) Parameter Symbol CPU clock cycle time* (min. instruction execution time = 1 machine cycle) tCY TI0, TI1 input frquency fTI TI0, TI1 input high and low-level widths SCK cycle time SCK high and low-level widths tTIH, tTIL tKCY tKH, tKL Test Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V TYP. MAX. Unit 0.95 32 µs 3.8 32 µs 0 1 MHz 0 275 kHz 0.48 µs 1.8 µs Input 0.8 µs Output 0.95 µs Input 3.2 µs Output 3.8 µs Input 0.4 µs tKCY/2-50 ns 1.6 µs tKCY/2-50 ns VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. Output Input Output SI setup time (to SCK↑) tSIK 100 ns SI hold time (from SCK↑) tKSI 400 ns S0 output delay time from SCK↓ tKSO INT0 to INT4 High and low-level widths RESET low-level sidth VDD = 4.5 to 6.0 V 300 ns 1000 ns tINTH, tINTL 5 µs tRSL 5 µs 43 µPD75112(A), 75116(A) *: The cycle time of the CPU clock (Φ ) is determined by the input frequency of the ceramic crystal oscillator and the setting of the processor clock control register (PCC). The cycle time (tCY) for VDD is shown below. tCY vs. VDD [V] 40 32 7 6 5 Cycle Time tCY [ µ s] 4 Operation Guaranteed Range 3 2 1 0.5 0 1 2 3 4 Supply Voltage VDD [V] AC Timing Test Point (Except for Ports 0, 1, TI0, TI1, X1, X2 and RESET) 0.7 VDD 0.3 VDD Test Points 0.7 VDD 0.3 VDD Clock Timing 1/fX tXL X1 Input 44 tXH VDD – 0.5 0.4 5 6 µPD75112(A), 75116(A) TI0 and TI1 Input Timing 1/fTI tTIL tTIH 0.8 VDD TI0, TI1 0.2 VDD Serial Transfer Timing tKCY tKL tKH 0.8 VDD SCK 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKSO SO Output Data Interrupt Input Timing tINTL INT0-INT4 tINTH 0.8 VDD 0.2 VDD 45 µPD75112(A), 75116(A) RESET Input Timing tRSL RESET 0.2 VDD Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (Ta = –40 to +85 °C) Parameter Test Conditions Symbol Data retention supply voltage VDDDR Data retention supply current*1 VDDDR Release signal set time tSREL tWAIT Oscillation stabilization wait time*2 MIN. 2.0 VDDDR = 2.0 V 0.1 Release by RESET Release by interrupt request 46 Wait Time (fXX=4.19 MHz Valu´s in Parentheses) BTM2 BTM1 BTM0 0 0 0 220/fXX (approx. 250 ms) 0 1 1 217/fXX (approx. 31.3 ms) 1 0 1 215/fXX (approx. 7.82 ms) 1 1 1 213/fXX (approx. 1.95 ms) MAX. Unit 6.0 V 10 µA µs 0 * 1: Current for the on-chip pull-up resistor, power-on circuit (mask option) and comparator circuit is not included. 2: The oscillation stabilizing time is intended to stop the CPU to prevent any unstable operation at the start of oscillation. 3: Depends on the following setting of the basic interval timer mode register (BTM). BTM3 TYP. 217/fX ms *3 ms µPD75112(A), 75116(A) Data Retention Timing (STOP Mode Release by RESET) Internal Reset Operation HALT Mode STOP Mode Operating Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT Mode STOP Mode Operating Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 47 µPD75112(A), 75116(A) 12. Packing Information 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K H G J I L F D N M NOTE B C M ITEM MILLIMETERS R INCHES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. A 58.68 MAX. 2.311 MAX. B 1.78 MAX. 0.070 MAX. 2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0 0.669 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P64C-70-750A,C-1 48 µPD75112(A), 75116(A) 64 PINPlastic PLASTIC 64-Pin QFP QFP (14 × (14×20) 20) (Unit: mm) ★ A B 33 32 64 1 20 19 detail of lead end F Q 5°±5° D C S 51 52 G H I M J M P K N L P64GF-100-3B8,3BE,3BR-1 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.6 ± 0.4 0.929 ± 0.016 B 20.0 ± 0.2 0.795+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 1.0 0.039 H 0.40 ± 0.10 0.016 +0.004 –0.005 I 0.20 0.008 J 1.0 (T.P.) 0.039 (T.P.) K 1.8 ± 0.2 0.071–0.009 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.12 0.005 P 2.7 0.106 Q 0.1 ± 0.1 0.004 ± 0.004 S 3.0 MAX. 0.119 MAX. +0.008 49 µPD75112(A), 75116(A) 13. Recommended Soldering Conditions ★ The µPD75112(A) and 75116(A) should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document “Surface Mount Technology Manual” (IEI-1207). For soldering methods and conditions other than those recommended below, contact our sales personnel. Table 13-1 Surface Mounting Type Soldering Conditions µPD75112GF(A)-×××-3BE : 64-pin plastic QFP (14 × 20mm) µPD75116GF(A)-×××-3BE : 64-pin plastic QFP (14 × 20mm) Soldering Method Recommended Condition Symbol Soldering Conditions Infrared reflow Package peak temperature: 230 °C Duration: 30 sec. max. (at 210°C above) Number of times: Once IR30-00-1 VPS Package peak temperature: 215 °C Duration: 40 sec. max. (at 200°C above) Number of times: Once VP15-00-1 Wave soldering Solder bath temperature: 260 °C max. Duration: 10 sec. max. Number of times: Once Preliminary heat temperature: 120 °C max. (Package surface temperature) WS60-00-1 Pin part heating Pin part temperature: 300 °C max. Duration: 3 sec. max. (per device side) Note: Use more than one soldering method should be avoided (except in the case of pin part). Table 13-2 Insertion Type Soldering Conditions µPD75112CW(A)-×××: 64-pin plastic shrink DIP (750 mil) µPD75116CW(A)-×××: 64-pin plastic shrink DIP (750 mil) Soldering Method Soldering Conditions Wave soldering (lead part only) Solder bath temperature: 260 °C max. Duration: 10 sec. max. Pin part heating Pin part temperature: 260 °C max. Duration: 10 sec. max. Note: Wave soldering is only for the lead part in order that jet solder can not contact with the chip. Notice A version of this product with improved recommended soldering conditions is available. For details (improvements such as infrared reflow peak temperature extension (235 °C, number of times: twice, relaxation of time limit), contact NEC sales 51 µPD75112(A), 75116(A) ★ APPENDIX A. Differences between µPD751××(A) Series Products and Related PROM Products Product Name µPD75104(A) Item µPD75106(A) ROM Configuration ROM (bit) 0000H to 177FH 6016 × 8 0000H to 1F7FH 8064 × 8 320 × 4 Bank 0: 256 × 4 Bank 1: 64 × 4 Instruction set µPD75P108B µPD75P116 PROM 0000H to 2F7FH 12160 × 8 0000H to 3F7FH 16256 × 8 512 × 4 Bank 0: 256 × 4 Bank 1: 256 × 4 High end (Only µPD75104(A) does not incorporate BR !addr instruction). 0000H to 1F7FH 8064 × 8 0000H to 3F7FH 16256 × 8 512 × 4 Bank 0: 256 × 4 Bank 1: 256 × 4 High end 58 Total Input/ output • CMOS input/output: 32 • +12 V withstand N-ch voltage open-drain input/output: 12 (Pull-up resistor can be on-chip by mask option.) Input • CMOS input/output: 10 • Comparator: 4 Power-on reset circuit µPD75116(A) Mask ROM 0000H to 0FFFH 4096 × 8 RAM (bit) I/O line µPD75108(A) µPD75112(A) • CMOS input/output: 32 • +12 V withstand N-ch open-drain input/ output: 12 Each pin can directly drive LED: 44 Can be on-chip by mask option None Power-on flag Supply voltage range 2.7 to 6.0 V 2.7 to 6.0 V 5 V±10% Pin connection Differs depending on package Differs depending on package (with VPP pin) Quality grade Special Standard Package 52 • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 20 mm) • 64-pin plastic • 64-pin plastic shrink DIP shrink DIP (750 mil) (750 mil) • 64-pin ceramic • 64-pin plastic QFP shrink DIP (with window) (14 × 20 mm) • 64-pin plastic QFP (14 × 20 mm) µPD75112(A), 75116(A) APPENDIX B. Development Tools The following tools are available for the development of systems for which the µPD75116(A) is used. Hardware IE-75000-R*1 IE-75001-R 75X series in-circuit emulator IE-75000-R-EM*2 Emulation board for IE-75000R and IE-75001-R. EP-75108CW-R Emulation probe for µPD75112CW(A) and 75116CW(A). EP-75108GF-R Emulation probe for µPD75112GF(A) and 75116GF(A). 64-pin conversion socket EV-9200G64 added. EV-9200G64 Software PG-1500 PROM programmer PA-75P108CW µPD75P116CW PROM programmer adapter connected to PG-1500 PA-75P116GF µPD75P116GF PROM programmer adapter connected to PG-1500 IE control program Host machine • PC-9800 series (MS-DOSTM Ver. 3.30 to 5.00A*3) • IBM PC/ATTM (PC DOSTM Ver. 3.1) PG-1500 controller RA75X relocatable assembler * 1: Maintenance product 2: Not incorporated in the IE-75001-R. 3: The task swap function, which is provided with Ver. 5.00/5.00A, is not available with this software. Remarks: For development tools manufactured by a third party, see the “75X Series Selection Guide” (IF-151)”. 53 µPD75112(A), 75116(A) ★ APPENDIX C. Related Documentations List of Device Related Documentations Document Number Document Name IEM-1260 User’s Manual — Instruction Application Table Application Note (I) Introductory Volume IEM-1139 (II) Remote Control Reception Volume IEM-1281 (III) Bar-Code Reader Volume IEM-1265 (IV) IC Control for MSK Transmission/Reception Volume IEA-1278 IF-1027 75X Series Selection Guide List of Development Tools Related Documentations Document Name Hardware Software Document Number IE-75000-R/IE-75001-R User’s Manual EEU-1416 IE-75000-R-EM User’s Manual EEU-1294 EP-75108CW-R User’s Manual EEU-1308 EP-75108GF-R User’s Manual EEU-1318 PG-1500 User’s Manual EEU-1335 RA75X Assembler Package User’s Manual Operation Volume EEU-1346 Language Volume EEU-1343 EEU-1291 PG-1500 Controller User’s Manual List of Other Related Documentations Document Name Package Manual IEI-1213 Surface Mount Technology Manual IEI-1207 Quality Grade on NEC Semiconductor Devices IEI-1209 NEC Semiconductor Device Reliability & Quality Control — Electrostatic Discharge (ESD) Test — Semiconductor Devices Quality Guarantee Guide Microcomputer Related Products Guide Other Manufactures Volume Note: The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. 54 Document Number MEI-1202 — µPD75112(A), 75116(A) 55 µPD75112(A), 75116(A) No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may ppear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual propety rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporations.