DATA SHEET MOS INTEGRATED CIRCUIT µPD75P216A 4-BIT SINGLE-CHIP MICROCOMPUTER The µPD75P216A is a One-Time PROM version of the µPD75216A. The µPD75P216A is suitable for smallscale production or experimental production in system development. Also see documents for the µPD75216A. FEATURES • The µPD75216A compatible • 16256 ✕ 8 bits of on-chip one-time PROM • Port 6 without pull-down resistor • High voltage output for display S0 to S8, T0 to T9: On-chip load resistor S9, T10 to T15: Open drain • Power-on reset circuit is not available • Single power supply (5 V ± 10 %) ORDERING INFORMATION Part Number µPD75P216ACW Package 64-pin plastic shrink DIP (750 mil) Quality Grade Standard Caution Pull-up resistor mask options are not available. Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. Document No. IC–2670A (O.D.No. IC-7625B ) Date Published July 1993 P Printed in Japan The mark shows revised points. 1 © NEC CORPORATION 1990 1992 µPD75P216A PIN CONFIGURATION (Top View) 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 µ PD75P216ACW S3 S2 S1 S0 P00/INT4 P01/SCK P02/SO P03/SI P10/INT0/VPP P11/INT1 P12/INT2 P13/TI0 P20 P21 P22 P23/BUZ P30/MD0 P31/MD1 P32/MD2 P33/MD3 P60 P61 P62 P63 P40 P41 P42 P43 PPO X1 X2 VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD S4 S5 S6 S7 S8 S9 NC VLOAD T15/S10 T14/S11 T13/S12/PH0 T12/S13/PH1 T11/S14/PH2 T10/S15/PH3 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 RESET P53 P52 P51 P50 XT2 XT1 INTBT TI0/P13 PROGRAM COUNTER (14) CY ALU PORT 0 4 P00–P03 PORT 1 4 P10–P13 PORT 2 4 P20–P23 PORT 3 4 P30/MD0– P33/MD3 PORT 4 4 P40–P43 PORT 5 4 P50–P53 PORT 6 4 P60–P63 SP (8) TIMER/EVENT COUNTER #0 BANK BLOCK DIAGRAM BASIC INTERVAL TIMER INTT0 PPO TIMER/PULSE GENERATOR INTTPG SI/P03 SO/P02 SCK/P01 SERIAL INTERFACE GENERAL REG. PROM PROGRAM MEMORY 16256 × 8BITS DECODE AND CONTROL RAM DATA MEMORY 512 × 4BITS 10 INTSIO FIP CONTROLLER/ DRIVER VPP/INT0/P10 INT1/P11 INT2/P12 4 T10/S15/PH3– T13/S12/PH0 2 T14/S11,T15/S10 INTERRUPT CONTROL 10 INT4/P00 T0–T9 S0–S9 fX/2N INTW WATCH TIMER CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN VLOAD CPU CLOCK φ STAND BY CONTROL INTKS BUZ/P23 XT1 XT2 X1 X2 V DD VSS RESET 4 PH0–PH3 3 µPD75P216A PORTH µPD75P216A CONTENTS 1. PIN FUNCTIONS ................................................................................................................................ 5 1.1 PORT PINS .................................................................................................................................................... 5 1.2 NON-PORT PINS .......................................................................................................................................... 6 1.3 TREATMENT OF UNUSED PINS ................................................................................................................ 8 2. DIFFERENCES BETWEEN THE µPD75P216A AND THE µPD75216A, µPD75208 ................. 9 3. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ..................................................10 3.1 PROM WRITE AND VERIFY OPERATION................................................................................................ 10 3.2 PROM WRITE PROCEDURE ...................................................................................................................... 11 3.3 PROM READ PROCEDURE ........................................................................................................................ 12 4. ELECTRICAL SPECIFICATIONS ...................................................................................................... 13 5. PACKAGE DRAWINGS .................................................................................................................... 22 6. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 23 APPENDIX DEVELOPMENT TOOLS ................................................................................................... 24 4 µPD75P216A 1. PIN FUNCTIONS 1.1 PORT PINS Pin name Input/ output Shared pin P00 Input INT4 P01 I/O SCK F P02 I/O SO G P03 Input SI B P10 Input INT0/VPP With noise elimination function P11 INT1 With noise elimination function P12 INT2 P13 TI0 P20 I/O — P21 — P22 — P23 BUZ Function 4-bit input port (PORT0). 8-bit I/O When reset I/O circuit type Note ✕ Input B ✕ Input B 4-bit I/O port (PORT2). ✕ Input E ✕ Input E 4-bit input port (PORT1). P30 - P33 I/O MD0 - MD3 Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. P40 - P43 I/O — 4-bit I/O port (PORT4). Can directly drive LEDs. Data input/output pins for the PROM write and verify (Four low-order bits). Input E P50 - P53 I/O — 4-bit I/O port (PORT5). Can directly drive LEDs. Data input/output pins for the PROM write and verify (Four high-order bits). Input E P60 - P63 I/O — Programmable 4-bit I/O port (PORT6). I/O can be specified bit by bit. Suitable for keyboard input. ✕ Input E PH0 Output T13/S12 4-bit P-ch open-drain output port Can withstand high voltage and high current (PORTH) ✕ PH1 T12/S13 PH2 T11/S14 PH3 T10/S15 Note The circle ( High impedance I-D ) indicates the Schmitt triggered input. 5 µPD75P216A 1.2 NON-PORT PINS Pin name Input/ output T0 - T9 Shared pin — T10/S15 T13/S12 Function Note 2 Note 3 Output S9 I-E For digit/segment output Can withstand high voltage and high current Static output is possible. High impedance I-D Note 2 For segment output Can withstand high voltage Low level I-E Output — TI0 Input P13 External event pulse input to timer event counter SCK I/O P01 Input and output to serial clock Input F SO I/O P02 Serial data output or serial data input and output Input G SI Input P03 Serial data input or normal input Input B P00 Edge detection vectored interrupt input (detected at both rising edge and falling edge) — B Edge detection vectored interrupt input with noise elimination function (edge-detection selectable) — B — B Input E — Crystal/ceramic resonator connection for main system clock generation. When external clock signal is used, it is applied to X1, and its reverse phase signal is applied to X2. — — — Crystal connection for subsystem clock generation. When external clock signal is used, it is applied to XT1 and XT2 is open. — — System reset input (low-level active) — B INT0 Input Input INT1 P10/V PP P11 Pulse output by timer/pulse generator High impedance PPO INT4 INT2 Input P12 Testable input for edge-detection (detected at rising edge) BUZ I/O P23 Fixed frequency output (For buzzer or system clock trimming) X1, X2 Input XT1 Input D B XT2 — RESET Input — MD0 - MD3 I/O P30 - P33 Operation mode selection during the PROM write/verify cycles. — E VPP P10/INT0 +12.5 V is applied as the programming voltage during the PROM write/verify cycles — B VLOAD — Pull-down resistor connection of FIP controller/driver — I-E VDD — Positive power supply +6 V is applied as the programming voltage during the PROM write/verify cycles — — VSS — GND potential — — — No connection — — NC Note 4 Note 1. 2. 3. 4. 6 Low level For segment output Can withstand high voltage Static output is possible — S0 -S8 I/O circuit type Note 1 For digit/segment output Can withstand high voltage and high current Unused pin can be used as PORTH. PH3-PH0 T14/S11, T15/S10 Used for digit output Can withstand high voltage and high current When reset The circle ( ) indicates the Schmitt triggered input. Pull-down resistor is incorporated. Open-drain output NC pin should be connected to VPRE when sharing print board with the µPD75216A. µPD75P216A Fig. 1-1 Pin Input/Output Circuit TYPE A TYPE F VDD data IN/OUT Type D output disable P-ch IN Type B N-ch I/O circuit consisting of Type D push-pull output and Type B Schmitt-triggered input CMOS level input buffer TYPE B TYPE G VDD P-ch output disable data P-ch IN/OUT IN N-ch Type B Schmitt-triggered input with hysteresis TYPE D I/O circuit which can switch push-pull output or N-ch open-drain output (off for P-ch) VDD TYPE I-D data VDD P-ch VDD OUT data output disable P-ch P-ch N-ch N-ch OUT Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) TYPE E TYPE I-E VDD data VDD IN/OUT Type D data output disable P-ch N-ch Type A P-ch OUT Pull-down resistor VLOAD I/O circuit consisting of Type D push-pull output and Type A input buffer. 7 µPD75P216A 1.3 TREATMENT OF UNUSED PINS Table 1-2 Recommended Connection for Unused Pins Pin P00/INT4 Recommended connection Connect to V SS P01/SCK P02/SO Connect to V SS or VDD P03/SI P10/INT0/VPP P11/INT1, P12/INT2 Connect to V SS P13/T10 P20 - P22 P23/BUZ P30/MD0 - P33/MD3 Input: Connect to VSS or VDD P40 - P43 Output: Open P50 - P53 P60 - P63 PPO S0 - S9 T15/S10, T14/S11 Open T0 - T9 T10/S15/PH3-T13/S12/PH0 8 XT1 Connect to VSS or VDD XT2 Open µPD75P216A 2. DIFFERENCES BETWEEN THE µPD75P216A AND THE µPD75216A, µPD75208 Table 2-1 Differences between the µPD75P216A and the µPD75216A, µPD75208 µPD75P216A Parameter One-time PROM ® FIP µPD75216A µPD75208 Mask ROM ROM 16256 × 8 bits (0000H – 3F7FH) 8064 × 8 bits (0000H – 1F7FH) RAM 512 × 4 bits 497 × 4 bits 9 – 16 segments 9 – 12 segments Controller Driver Pull-Down Registor Port 6 N/A S0 – S8, T0 – T9 On-chip S9, T10 – T15 N/A (Open-drain) Mask option Power-On Reset N/A Mask option P10/INT0/VPP P10/INT0 P30/MD0 – P33/MD3 P30 – P33 NC VPRE Operating Ambient Temperature –10 to +70 °C –40 to +85 °C Operating Supply Voltage 5 V ± 10 % 2.7 to 6.0 V Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (14 × 20 mm) Power-On Flag Pin Connection 9 µPD75P216A 3. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY The µPD75P216A contains 16256 × 8 bits of one-time PROM available of writing. The following table shows the pin functions during the write and verify cycles. Note that it is not necessary to enter an address, because the address is updated by pulsing the X1 clock pins. Table 3-1 Used Pin at PROM Write and Verify Pin name Caution 1. Function VPP Voltage application pin for write and verify (Normally VDD potential) X1, X2 Address-update clock input during write/verify. The inverted signal of the X1 should be input to the X2. MD0 - MD3 Operation mode selection pins for write and verify P40 - P43 (lower 4 bits) P50 - P53 (higher 4 bits) 8-bit data input/output pins for write and verify VDD Supply voltage application pin Normally 5 V ± 10 %; 6 V is applied during write/verify The pins which are not used during write or verify should be treated as follows • Port, XT1, RESET … Connect to VSS through pull-down resistors • S0 to S9, T0 to T15, PPO, VLOAD … Connect to VDD through pull-up resistors • XT2 … Open 2. The µPD75P216A do not have a UV erase window, thus the PROM contents cannot be erased with ultra violet ray. 3.1 PROM WRITE AND VERIFY OPERATION When +6 V and +12.5 V are applied to the VDD and VPP pins, respectively, the PROM is placed in the write/ verify mode. The operation is selected by the MD0 to MD3 pins, as shown in the table. Table 3-2 PROM Write and Verify Operation Operation mode specification Operation mode VPP VDD MD0 MD1 MD2 MD3 +12.5 +6 V H L H L Clear program memory address to 0 L H H H Write mode L L H H Verify mode H × H H Program inhibit mode ×: Don’t care. 10 µPD75P216A 3.2 PROM WRITE PROCEDURE PROM can be written at high speed using the following procedure: (see the following figure) (1) Pull unused pins to VSS through resistors. Set the X1 pin low. (2) Supply 5 volts to the VDD and VPP pins. (3) Wait for 10 µs. (4) Select the zero clear program memory address mode. (5) Supply 6 volts to the VDD and 12.5 volts to the VPP pins. (6) Select the program inhibit mode. (7) Write data in the 1 ms write mode. (8) Select the program inhibit mode. (9) Select the verify mode. If the data is correct, proceed to step (10). If not repeat steps (7), (8) and (9). (10) Perform one additional write (duration of 1ms × number of writes at (7) to (9)). (11) Select the program inhibit mode. (12) Apply four pulses to the X1 pin to increment the program memory address by one. (13) Repeat steps (7) to (12) until the end address is reached. (14) Select the zero clear program memory address mode. (15) Return the VDD and VPP pins back to + 5 volts. (16) Turn off the power. Fig. 3-1 Timing of Program Memory Write X repetition Write Verify Additional write Address increment VPP VPP VDD VDD+1 VDD VDD X1 P40-P43 P50-P53 Input data Output data Input data MD0 (P30) MD1 (P31) MD2 (P32) MD3 (P33) 11 µPD75P216A 3.3 PROM READ PROCEDURE The PROM contents can be read in the verify mode by using the following procedure: (see the following figure) (1) Pull unused pins to VSS through resistors. Set the X1 pin low. (2) Supply 5 volts to the VDD and VPP pins. (3) Wait for 10 µs. (4) Select the zero clear program memory address mode. (5) Supply 6 volts to the VDD and 12.5 volts to the VPP pins. (6) Select the program inhibit mode. (7) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one address. (8) Select the program inhibit mode. (9) Select the zero clear program memory address mode. (10) Return the VDD and VPP pins back to + 5 volts. (11) Turn off the power. Fig. 3-2 Timing of Program Memory Read VPP VPP VDD VDD+1 VDD VDD X1 P40-P43 P50-P53 Output data MD0 (P30) MD1 (P31) MD2 (P32) MD3 (P33) 12 ”L“ Output data µPD75P216A 4. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (Ta = 25 °C) Parameter Supply voltage Input voltage Output voltage High-level output current Symbol Conditions Ratings Unit VDD –0.3 to +7.0 V VLOAD VDD –40 to VDD + 0.3 V VPP –0.3 to +13.5 V VI –0.3 to V DD +0.3 V –0.3 to V DD +0.3 V VDD –40 to VDD + 0.3 V Single pin; other than display pins –15 mA Single pin; S0 – S9 –15 mA Single pin; T0 – T15 –30 mA Total of all pins other than diplay –20 mA –120 mA Single pin 17 mA Total of all pins 60 mA VO Other than display pins VOD Display pins IOH Total of all display pins Low level output current IOL Operating temperature Topt –10 to +70 °C Storage temperature Tstg –65 to +150 °C Operating Supply Voltage (Ta = –10 to + 70 °C) Parameter MIN. MAX. Unit 4.5 5.5 V Display controller 4.5 5.5 V Timer/pulse generator 4.5 5.5 V 4.5 5.5 V CPU Note Other hardwares Note Note Conditions Except system clock oscillation circuit, display controller, timer/pulse generator. 13 µPD75P216A Main System Clock Configurations (Ta = –10 to +70 °C, VDD = 5 V ± 10 %) Resonator Recommended constants Parameter Conditions Note 1 X1 Oscillation frequency (fXX) X2 Ceramic resonator Note 2 C1 C2 Oscillation stabilization time VDD = Oscillator operating voltage range MIN. TYP. 2.0 MAX. 5.0 After VDD reaches the minimum oscillator operating voltage range Note 3 4 Unit MHz ms Note 1 X1 Oscillation frequency (fXX) X2 Crystal resonator 2.0 4.19 5.0 Note 3 MHz Note 2 C1 C2 Oscillation stabilization time 10 ms Note 1 X1 X1 input frequency (fX) X2 External clock µ PD74HCU04 2.0 X1 input high- and low-level width (tXH, tXL ) 5.0 100 Note 3 MHz 250 ns Subsystem Clock Configurations (Ta = –10 to +70 °C, VDD = 5 V ± 10 %) Resonator Recommended constants Parameter Conditions MIN. TYP. MAX. Unit 32 32.768 35 kHz 1 2 s 32 100 kHz 10 32 µs Note 1 XT1 Crystal resonator Note 2 R C3 XT1 External clock Oscillation frequency (fXT) XT2 C4 XT2 Oscillation stabilization time XT1 input frequency (fXT) Open X1 input high- and low-level width (tXTH, tXTL ) Note 1. The oscillation frequency and input frequency only indicate the characteristics of the oscillation circuit. Refer to the AC characteristics for the instruction execution time. 2. The oscillation stabilization time is the time until the oscillation enters a stable state after the application of VDD or the release of STOP mode. 3. When the oscillation frequency is 4.19 < fX ≤ 5.0 MHz, PCC = 0011 should not be selected as the instruction execution time. If PCC = 0011 is selected, 1 machine cycle is less than the specified minimum value, which is 0.95 µ s. 14 µPD75P216A Capacitance (Ta = 25 °C, VDD = 0 V) Parameter Symbol Input capacitance Conditions MIN. TYP. CIN Other than display output Output capacitance COUT Display output Input/Output capacitance MAX. Unit 15 pF 15 pF 35 pF 15 pF MAX. Unit f = 1 MHz Unmeasured pins returned to 0 V CIO DC Characteristics (Ta = –10 to +70 °C, VDD = 5 V ± 10 %) Parameter High-level input voltage Low-level input voltage High-level output voltage Symbol Conditions VIH1 All except ports 0, 1, 6, X1, X2, XT1, RESET 0.7 VDD VDD V Port 0, 1 RESET 0.75 VDD VDD V VIH3 X1, X2, XT1 VDD–0.4 VDD V VIH4 Port 6 0.65 VDD VDD V VIL1 All except ports 0, 1, 6, X1, X2, XT1, RESET 0 0.3 VDD V VIL2 Port 0, 1, 6 RESET 0 0.2 VDD V VIL3 X1, X2, XT1 0 0.4 V VOH All outputs IOH = –1 mA VDD–1.0 IOH = –100 µA VDD–0.5 Port 4, 5 IOL = 15 mA All outputs IOL = 1.6 mA VOL High-level input leakage current ILIH1 ILIH2 X1, X2, XT1 Low-level input leakage current ILIL1 All except X1, X2, XT1 Low-level output leakage current VI = VDD VI = 0 V Note 1 2.0 V 0.4 V 3 µA 20 µA –3 µA –20 µA ILIL2 X1, X2, XT1 ILOH All outputs VO = VDD 3 µA ILOL1 All except display output VO = 0 V –3 µA ILOL2 Display outputs VO = VLOAD = VDD – 35 V –10 µA IOD Display outputs IDD1 4.19 MHz Crystal oscillator C1 = C2 = 15 pF IDD3 –3 –5.5 mA –15 –22 mA 25 70 135 kΩ 3.0 9.0 mA VOD = VDD – 2 V RL IDD2 Power supply current V All except X1, X2, XT1 T0 - T15 On-chip pull-down resistor V 0.4 S0 - S9 Display output current TYP. VIH2 Low-level output voltage High-level output leakage current MIN. VOD – VLOAD = 35 V Note 2 HALT mode Note 3 600 1 800 µA 100 300 µA IDD4 32.768 kHz Crystal oscillator HALT mode 40 100 µA IDD5 XT1 = 0 V STOP mode 0.5 20 µA Note 1. Does not include the current for the on-chip pull-down resistor (output circuit to S0 to S8, T0 to T9). 2. When the processor clock control register (PCC) is set to 0011 and operated in high-speed mode. 3. When the system clock control register (SCC) is set to 1001 to stop the main system clock, and when the sub-system clock is used. 15 µPD75P216A AC Characteristics (Ta = –10 to +70 °C, VDD = +5 V ±10%) Parameter Symbol Note 1 CPU clock time (minimum instruction execution time = 1 machine cycle) tCY TI0 input frequency fTI Conditions MIN. Main system clock 0.95 Subsystem clock 114 0 122 MAX. Unit 32 µs 125 µs 0.6 MHz 0.83 µs Input 0.8 µs Output 0.95 µs Input 0.4 µs tKCY/2-50 ns TI0 input high- and low-level width tTIH, tTIL SCK cycle time TYP. tKCY SCK high- and low-level width tKH, tKL Output SI setup time (to SCK ↑) tSIK 100 ns SI hold time (to SCK ↑) tKSI 400 ns SCK ↓ → SO output delay time tKSO Interrupt inputs high- and low-level width tINTH, tINTL 300 INT0 Note 2 µs INT1 2tCY µs 10 µs 10 µs INT2, 4 RESET low-level width ns tRSL Note 1. The CPU clock (ø) cycle time is decided by the oscillation frequency of the resonator, system clock control register (SCC), and processor clock control register (PCC). The figure to the right indicates cycle time (tCY) characteristics for supply voltage VDD when using the main system clock. 2. This is 2tCY or 128/fXX according to the interrupt mode register setting (IM0). tCY vs VDD (Main system clock) Cycle time tCY [ µ s] 50 Guaranteed operating range 10 5 1 0.5 0 1 2 3 4 5 Power supply voltage VDD [V] 16 6 µPD75P216A AC timing Test Point (Except X1, XT1) 0.75 VDD 0.75 VDD Test points 0.2 VDD 0.2 VDD Clock Timing 1/fX tXL tXH VDD – 0.4 V X1 input 0.4 V 1/fXT tXTL tXTH VDD – 0.4 V XT1 input 0.4 V TIO Timing 1/fTI tTIL tTIH TIO 17 µPD75P216A Serial Transfer Timing tKCY tKL tKH SCK tSIK tKSI Input data SI tKSO Output data SO Interrupt Input Timing tINTL INT0, 1, 2, 4 RESET Input Timing tRSL RESET 18 tINTH µPD75P216A Data Memory STOP Mode Low Voltage Data Retention Characteristics (Ta = –10 to +70 °C) Parameter Symbol Data retention voltage VDDDR Data retention current IDDDR Released signal SET time tSREL MIN. TYP. 2.0 VDDDR = 2.0 V 0.1 MAX. Unit 5.5 V 10 µA µs 0 Released by RESET input Note 1 Oscillation stabilization time Conditions 217/f X ms Note 2 ms tWAIT Released by interrupt request Note 1. The oscillation stabilization wait time is a period during which the CPU is kept inactive in order to avoid unstable operation at the start of oscillation. 2. Depends on the setting of the basic interval time mode register (BTM) (see the following table). BTM3 BTM2 BTM1 BTM0 Wait time ( ): fXX = 4.19 MHz 20 — 0 0 0 2 /fXX (approx. 250 ms) — 0 1 1 217/fXX (approx. 31.3 ms) — 1 0 1 215/fXX (approx. 7.82 ms) — 1 1 1 213/fXX (approx. 1.95 ms) Data Retention Timing (STOP mode is released by RESET input) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL Execution of STOP instruction RESET tWAIT Data Retention Timing (Standby release signal: STOP mode is released by interrupt signal) HALT mode Operation mode STOP mode Data retention mode VDD VDDDR tSREL Execution of STOP instruction Standby release signal (interrupt request) tWAIT 19 µPD75P216A DC Programming Characteristics (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V) Parameter Symbol High-level input voltage Low-level input voltage Conditions MIN. TYP. MAX. Unit VDD V VIH1 All except X1, X2 0.7 VDD VIH2 X1, X2 VDD–0.5 VDD V VIL1 All except X1, X2 0 0.3 VDD V 0 0.4 V 10 µA 0.4 V 30 mA 30 mA VIL2 X1, X2 Input leakage current IL1 VIN = V IL or VIH High-level output voltage VOH IOH = –1 mA Low-level output voltage VOL IOL = 1.6 mA VDD power supply current IDD VPP power supply current IPP VDD–1.0 V MD0 = VIL, MD1 = VIH Note 1. VPP should not exceed +22 V (including overshoot). 2. VDD should be applied before VPP and turned off after VPP. AC Programming Characteristics (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V) Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit (toMD0↓) tAS tAS 2 µs MD1 setup time (to MD0↓) tMIS tOES 2 µs Data setup time (to MD0↓) tDS tDS 2 µs (from MD0↑) tAH tAH 2 µs (from MD0↑) tDH tDH 2 µs Address setup time Address hold time Note 2 Note 2 Data hold time MD0 ↑ → data output float delay time tDF tDF 0 VPP setup time (to MD3↑) tVPS tVPS 2 VDD setup time (to MD3↑) tVDS tVCS 2 tPW tPW 0.95 Additional program pulse width tOPW tOPW 0.95 MD0 setup time tMOS tCES 2 Initialized program pulse width (to MD1↑) MD0 ↓ → data output delay time tDV tDV MD1 hold time (from MD0↑) tMIH tOEH (to MD0↓) tMIR tOR tPCR — tXH, tXL — 0.125 fX — MD1 recovery time Program counter reset time X1 input high- and low-level width X1 input frequency MD3 hold time MD3 setup time Note 2 tMIH + tMIR ≥ 50 µs ns µs µs 1.0 1.05 ms 21.0 ms µs 1 µs 2 µs 2 µs 10 µs µs 4.19 MHz tI — 2 µs tM3S — 2 µs (from MD1↓) tM3H — 2 µs (to MD0↓) tM3SR — During program read cycle 2 µs Initial mode set time MD3 setup time MD0 = MD1 = VIL 130 (to MD1↑) → Data output delay time µs tDAD tACC During program read cycle 2 Address Note 2 → Data output hold time tHAD tOH During program resd cycle 0 MD3 hold time tM3HR — During program read cycle 2 µs tDFR — During program read cycle 2 µs Address (from MD0↑) MD3 ↓ → data output float delay time 130 ns Note 1. Symbol of corresponding µPD27C256. 2. Internal address is incremented by 1 at the rising edge of the fourth X1 input. This address signal is not output to external pins. 20 µPD75P216A Program Memory Write Timing tVPS VPP VPP VDD tVDS VDD+1 VDD tXH VDD X1 tXL P40-P43 P50-P53 Output data Input data Input data tDS tI tOH tDV tDS tDF Input data tDH tAH tAS MD0 tPW tM1R tMOS tOPW MD1 tPCR tM1S tM1H MD2 tM3H tM3S MD3 Program Memory Read Timing tVPS VPP VPP VDD tVDS VDD+1 VDD VDD tXH X1 tXL tDAD tHAD P40-P43 P50-P53 Output data Output data tDV tI tDFR tM3HR MD0 MD1 tPCR MD2 tM3SR MD3 21 µPD75P216A 5. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K H G J I L F D N M NOTE M B C ITEM MILLIMETERS R INCHES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. A 58.68 MAX. 2.311 MAX. B 1.78 MAX. 0.070 MAX. 2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0 0.669 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P64C-70-750A,C-1 22 µPD75P216A 6. RECOMMENDED SOLDERING CONDITIONS The following conditions must be met when soldering this product. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (IEI-1207). Please consult with our sales offices in case other soldering process is used, or in case other soldering is done under different conditions. Table 6-1 Type of Through Hole Device µPD75P216ACW: 64-pin plastic shrink DIP (750 mil) Soldering process Soldering conditions Wave soldering (only lead part) Solder temperature: 260 °C or lower, Flow time: 10 seconds or less Partial heating method Pin temperature: 260 °C or lower, Time: 10 seconds or less Caution This wave soldering should be applied only to lead part, and don’t jet molten solder on the surface of package. 23 µPD75P216A APPENDIX DEVELOPMENT TOOLS The following development tools are provided for the development of a system which employs the µPD75P216A. Language processor RA75X relocatable assembler Host machine Part number OS PC-9800 series IBM PC series Distribution media MS-DOSTM Ver. 3.10 to Ver. 3.30C 3.5-inch 2HD µS5A13RA75X 5-inch 2HD µS5A10RA75X PC DOSTM (Ver. 3.1) 5-inch 2HC µS7B10RA75X PROM programming tools Hardware Software PG-1500 The PG-1500 PROM programmer is used together with an accessory board and optional programmer adapter. It allows the user to program a single chip microcomputer containing PROM from a standalone terminal or a host machine. The PG-1500 can be used to program typical 256K-bit to 4M-bit PROMs. PA-75P216ACW PROM programmer adapter dedicated to µPD75P216ACW. Connect the programmer adapter to PG-1500 for use. AF-9703 AF-9704 PROM programmer produced by Ando Electric Corp. AF-9789 Programmer adapter dedicated to the µPD75P216ACW Connect to AF-9703, AF-9704 for use UNISITE 2900 3900 PROM programmer produced by Data I/O Japan Corp. PPI-0601 Programmer adapter dedicated to the µPD75P216ACW Connect to UNISITE, 2900, 3900 for use PG-1500 controller This program enables the host machine to control the PG-1500 through the serial and parallel interfaces. Host machine Part number OS PC-9800 series IBM PC series 24 MS-DOS Ver. 3.10 to Ver. 3.30C PC DOS (Ver. 3.1) Distribution media 3.5-inch 2HD µS5A13PG1500 5-inch 2HD µS5A10PG1500 5-inch 2HC µS7B10PG1500 µPD75P216A Debugging tools Hardware IE-75000-R Note IE-75000-R-EM Software The IE-75000-R is an in-circuit emulator to debug the hardware and software at developing application system for 75X series. This emulator is used together with the emulation probe. For efficient debugging, the emulator is connected to the host machine and PROM programmer. The IE-75000-R-EM is an emulation board for the IE-75000-R and IE-75001-R. The IE-75000-R contains the emulation board. The emulation board is used together with the IE-75000-R or IE-75001-R to evaluate the µPD75P048. IE-75001-R The IE-75001-R is an in-circuit emulator to debug the hardware and software at developing application system for 75X series. This emulator is used together with the IE-75000-R-EM emulation board (option) and emulation probe. For efficient debugging, the emulator is connected to the host machine and PROM programmer. EP-75216ACW-R Emulation probe for the µPD75P216ACW. Connect this probe to the IE-75000-R or IE-75001-R and the IE-75000-R-EM for use. IE control program This program enables the host machine to control the IE-75000-R or IE-75001-R on the host machine through the RS-232-C interface. Host machine Part number OS PC-9800 series IBM PC series Notes MS-DOS Ver. 3.10 to Ver. 3.30C PC DOS (Ver. 3.1) Distribution media 3.5-inch 2HD µS5A13IE75X 5-inch 2HD µS5A10IE75X 5-inch 2HC µS7B10IE75X Provided only for maintenance purposes. Remark NEC is not responsible for the IE control program operation unless it runs on any host machine with the operation system listed above. 25 26 Configuration of Development Tools In-circuit emulator Emulation probe Centronics interface IE-75000-R IE-75001-R Note 1 RS-232-C Host machine EP-75216ACW-R EP-75216AGF-R IE-75000-R-EM IE control program Note 2 PG-1500 PC-9800 series controller IBM PC series (Symbol debugging possible) User system PROM version PROM programmer µ PD75P216ACW PG-1500 Relocatable assembler Programmer adapter PA-75P216ACW Notes 1. IE-75001-R is not provided with IE-75000-R-EM (option) 2. EV-9200GC-64 µPD75P216A µPD75P216A NOTES FOR CMOS DEVICES ➀ PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. ➁ HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pullup or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. ➂ STATUS BEFORE INITIAIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 27 µPD75P216A “µPD75216A USER’S MANUAL” (IEM-988F) is also prepared for this product (option). No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 ® FIP is a trademark of NEC Corporation. MS-DOS TM is a trademark of Microsoft Corporation. PC DOS TM is a trademark of IBM Corporation. 28