DATA SHEET MOS INTEGRATED CIRCUIT µPD78F0988A, 78F0988A(A) 8-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The µPD78F0988A and 78F0988A(A) are products in the µPD780988 Subseries in the 78K/0 Series that have flash memory in the place of the internal ROM of the µPD780988. Flash memory can be written or erased electrically with the device mounted on the board. Therefore, the µPD78F0988A and µPD78F0988A(A) are ideal for evaluation in system development, small-scale production, or systems likely to be upgraded frequently. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD780988 Subseries User’s Manual: 78K/0 Series Instruction User’s Manual: U13029E U12326E FEATURES • • • • • Pin-compatible with mask ROM version (except VPP pin) Flash memory: 60 KBNote 1 Internal high-speed RAM: 1024 bytes Internal expansion RAM: 1024 bytesNote 2 Operable in the same supply voltage range as the mask ROM version (VDD = 4.0 to 5.5 V) Notes 1. 2. The capacity of the flash memory can be changed with the internal memory size switching register (IMS). The capacity of the internal expansion RAM can be changed with the internal expansion RAM size switching register (IXS). Remark For the differences between the flash memory versions and the mask ROM versions, refer to 1. DIFFERENCES BETWEEN µPD78F0988A AND MASK ROM VERSIONS. ORDERING INFORMATION Part Number µPD78F0988ACW µPD78F0988AGC-AB8 µPD78F0988AGC-8BS µPD78F0988AGC(A)-AB8 µPD78F0988AGC(A)-8BS Package Quality Grade 64-pin plastic SDIP (19.05 mm (750)) Standard (for general electrical equipment) 64-pin plastic QFP (14 × 14) Standard (for general electrical equipment) 64-pin plastic LQFP (14 × 14) Standard (for general electrical equipment) 64-pin plastic QFP (14 × 14) Special (for high-reliability electrical equipment) 64-pin plastic LQFP (14 × 14) Special (for high-reliability electrical equipment) For details of the quality grade and its application fields, refer to Quality Grades on NEC Semiconductor Devices (C11531E). The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U15801EJ1V0DS00 (1st edition) Date Published October 2001 N CP(K) Printed in Japan © 2001 µPD78F0988A, 78F0988A(A) 78K/0 SERIES LINEUP The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin µ PD78075B µ PD78078 µ PD78070A 100-pin 80-pin 80-pin µ PD780058 µ PD78058F 80-pin µPD78054 µPD780065 64-pin µ PD780078 64-pin 64-pin 64-pin µ PD780034A µ PD780024A µPD78014H 64-pin µPD78018F µ PD78083 80-pin 42-/44-pin EMI-noise reduced version of the µPD78078 µPD78078Y µPD78054 with added timer and enhanced external interface µ PD78070AY ROMless version of the µ PD78078 µ PD78078Y with enhanced serial I/O and limited function µ PD780018AY µ PD780058Y µ PD78058FY µ PD78054 with enhanced serial I/O EMI-noise reduced version of the µ PD78054 µPD78018F with enhanced UART and D/A converter and enhanced I/O µPD780024A with increased RAM capacity. µPD780034A with added timer and enhanced serial I/O µ PD780078Y µ PD780034AY µ PD780024A with enhanced A/D converter µ PD780024AY µ PD78018F with enhanced serial I/O EMI-noise reduced version of the µPD78018F µ PD78054Y µ PD78018FY Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V) Inverter control 64-pin µPD780988 On-chip inverter controller and UART. EMI-noise reduced. VFD drive 78K/0 Series 100-pin µ PD780208 µ PD78044F with enhanced I/O and VFD C/D. Display output total: 53 80-pin µ PD780232 µPD78044H For panel control. On-chip VFD and C/D. Display output total: 53 80-pin 80-pin µPD78044F Basic subseries for VFD drive. Display output total: 34 µ PD78044F with added N-ch open-drain I/O. Display output total: 34 LCD drive 120-pin µ PD780338 120-pin µ PD780328 µPD780318 µ PD780308 µPD78064B µPD78064 120-pin 100-pin 100-pin 100-pin µ PD780308 with enhanced display function and timer. Segment signal output: 40 pins max. µ PD780308 with enhanced display function and timer. Segment signal output: 32 pins max. µ PD780308 with enhanced display function and timer. Segment signal output: 24 pins max. µPD780308Y µ PD78064 with enhanced SIO, and increased ROM, RAM capacity EMI-noise reduced version of the µ PD78064 µ PD78064Y Basic subseries for LCD drive, on-chip UART Bus interface supported 100-pin 80-pin µ PD780948 µ PD78098B On-chip CAN controller µPD78054 with added IEBusTM controller. 80-pin µPD780702Y On-chip IEBus controller 80-pin µPD780703Y µPD780833Y On-chip CAN controller 80-pin 64-pin µPD780816 On-chip controller compliant with J1850 (Class 2) Specialized for CAN controller function Meter control 100-pin µPD780958 For industrial meter control 80-pin µPD780852 µPD780828B On-chip automobile meter controller/driver For automobile meter driver. On-chip CAN controller 80-pin Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same. 2 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) The major functional differences between the subseries are shown below. Function Subseries Name ROM Capacity (Bytes) Timer 8-Bit 16-Bit Watch WDT A/D µPD78075B 32 K to 40 K 4 ch Control µPD78078 µPD78070A 8-Bit 10-Bit 8-Bit 1 ch 1 ch 1 ch 8 ch A/D – Serial Interface I/O VDD External MIN. Expansion Value 88 1.8 V 61 2.7 V D/A 2 ch 3 ch (UART: 1 ch) 48 K to 60 K – µPD780058 24 K to 60 K 2 ch 3 ch (time-division UART: 1 ch) 68 1.8 V µPD78058F 48 K to 60 K 3 ch (UART: 1 ch) 69 2.7 V µPD78054 √ 16 K to 60 K 2.0 V µPD780065 40 K to 48 K – µPD780078 48 K to 60 K 2 ch µPD780034A 8 K to 32 K 1 ch – µPD780024A 8 ch 8 ch 4 ch (UART: 1 ch) 60 2.7 V 3 ch (UART: 2 ch) 52 1.8 V 3 ch (UART: 1 ch) 51 2 ch 53 1 ch (UART: 1 ch) 33 – µPD78014H µPD78018F 8 K to 60 K µPD78083 8 K to 16 K – Inverter control µPD780988 16 K to 60 K 3 ch Note VFD drive µPD780208 32 K to 60 K 2 ch – – 1 ch – 8 ch – 3 ch (UART: 2 ch) 47 4.0 V √ 1 ch 1 ch 1 ch 8 ch – – 2 ch 74 2.7 V – µPD780232 16 K to 24 K 3 ch – – 4 ch 40 4.5 V µPD78044H 32 K to 48 K 2 ch 1 ch 1 ch 8 ch 68 2.7 V 54 1.8 V 1 ch µPD78044F 16 K to 40 K LCD drive µPD780338 48 K to 60 K 3 ch 2 ch 2 ch 1 ch 1 ch – 10 ch 1 ch 2 ch (UART: 1 ch) µPD780328 62 µPD780318 70 µPD780308 48 K to 60 K 2 ch 1 ch 8 ch – – µPD78064B 32 K µPD78064 3 ch (time-division UART: 1 ch) – 57 2.0 V 79 4.0 V √ 69 2.7 V – 2 ch (UART: 1 ch) 16 K to 32 K Bus µPD780948 60 K 2 ch interface supported µPD78098B 40 K to 60 K 2 ch 1 ch 1 ch 8 ch – 1 ch – 3 ch (UART: 1 ch) 2 ch µPD780816 32 K to 60 K 2 ch Meter control µPD780958 48 K to 60 K 4 ch 2 ch – 1 ch – Dash board control µPD780852 32 K to 40 K 3 ch 1 ch 1 ch 1 ch 5 ch Note – 12 ch – 2 ch (UART: 1 ch) 46 4.0 V – – 2 ch (UART: 1 ch) 69 2.2 V – – – 3 ch (UART: 1 ch) 56 4.0 V – µPD780828B 32 K to 60 K 59 16-bit timer: 2 channels 10-bit timer: 1 channel Data Sheet U15801EJ1V0DS 3 µPD78F0988A, 78F0988A(A) OVERVIEW OF FUNCTIONS Item Internal Flash memory Function 60 KBNote 1 memory High-speed RAM Expansion RAM Memory space General-purpose register Instruction cycle 1024 bytes 1024 bytesNote 2 64 KB 8 bits × 32 registers (8 bits × 8 registers × 4 banks) On-chip instruction execution time variable function 0.24 µs/0.48 µs/0.96 µs/1.9 µs/3.8 µs (@ 8.38 MHz operation with system clock) Instruction set • 16-bit operation • Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits) • Bit manipulation (set, reset, test, Boolean operation) • BCD adjust, etc. I/O ports Total: 47 • CMOS inputs: 8 • CMOS I/O: 39 Real-time output ports • 8 bits × 1 or 4 bits × 2 • 6 bits × 1 or 4 bits × 1 A/D converter • 10-bit resolution × 8 channels • Power supply voltage: AVDD = 4.0 to 5.5 V Serial interface • UART mode: 2 channels • 3-wire serial I/O mode: 1 channel Timer • 16 bit timer/event counter: 2 channels • 8-bit timer/event counter: 3 channels • 10-bit inverter control timer: 1 channel • Watchdog timer: 1 channel Timer output 11 (general-purpose outputs: 5, inverter control outputs: 6) Vectored Maskable Internal: 16, external: 8 interrupt Non-maskable Internal: 1 sources Software 1 Power supply voltage VDD = 4.0 to 5.5 V Operating ambient temperature TA = –40 to +85°C Package • 64-pin plastic SDIP (19.05 mm (750))Note 3 • 64-pin plastic QFP (14 × 14) • 64-pin plastic LQFP (14 × 14) Notes 1. The capacity of the flash memory can be changed with the internal memory size switching register (IMS). 2. The capacity of the internal expansion RAM can be changed with the internal expansion RAM size 3. Standard quality grade products only. switching register (IXS). 4 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) PIN CONFIGURATION (TOP VIEW) • 64-Pin Plastic SDIP (19.05 mm (750)) µPD78F0988ACW P40/AD0 1 64 P67/ASTB P41/AD1 2 63 P66/WAIT P42/AD2 3 62 P65/WR P43/AD3 4 61 P64/RD P44/AD4 5 60 P37/RTP7 P45/AD5 6 59 P36/RTP6 P46/AD6 7 58 P35/RTP5 P47/AD7 8 57 P34/RTP4 P50 9 56 P33/RTP3 P51/SCK 10 55 P32/RTP2 P52/SI 11 54 P31/RTP1 P53/SO 12 53 P30/RTP0 P54/TI000/TO00/INTP4 13 52 P01/INTP1 P55/TI010/INTP5 14 51 P00/INTP0/TOFF7 P56/TI001/TO01/INTP6 15 50 VSS1 P57/TI011/INTP7 16 49 X1 VSS0 17 48 X2 VDD0 18 47 TEST TO70 19 46 P03/INTP3/ADTRG TO71 20 45 P02/INTP2 TO72 21 44 RESET TO73 22 43 AVDD TO74 23 42 AVREF TO75 24 41 P10/ANI0 P20/RxD00 25 40 P11/ANI1 P21/TxD00 26 39 P12/ANI2 P22/RxD01 27 38 P13/ANI3 P23/TxD01 28 37 P14/ANI4 P24/TI50/TO50 29 36 P15/ANI5 P25/TI51/TO51 30 35 P16/ANI6 P26/TI52/TO52 31 34 P17/ANI7 VDD1 32 33 AVSS Cautions 1. In the normal operation mode, connect the VPP pin directly to VSS0. 2. In the flash memory writing mode, connect the VPP pin to VSS0 via a 10 kΩ pull-down resistor. 3. The 64-pin plastic SDIP (19.05 mm (750)) package is not provided for special quality grade products. Remark When the µPD78F0988A and 78F0988A(A) are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended. Data Sheet U15801EJ1V0DS 5 µPD78F0988A, 78F0988A(A) • 64-pin plastic QFP (14 × 14) µPD78F0988AGC-AB8, 78F0988AGC(A)-AB8 • 64-pin plastic LQFP (14 × 14) P34/RTP4 P35/RTP5 P36/RTP6 P37/RTP7 P64/RD P65/WR P66/WAIT P67/ASTB P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 µPD78F0988AGC-8BS, 78F0988AGC(A)-8BS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P50 1 48 P33/RTP3 P51/SCK 2 47 P32/RTP2 P52/SI 3 46 P31/RTP1 P53/SO 4 45 P30/RTP0 P54/TI000/TO00/INTP4 5 44 P01/INTP1 P55/TI010/INTP5 6 43 P00/INTP0/TOFF7 P56/TI001/TO01/INTP6 7 42 VSS1 P57/TI011/INTP7 8 41 X1 VSS0 9 40 X2 VDD0 10 39 TEST TO70 11 38 P03/INTP3/ADTRG TO71 12 37 P02/INTP2 TO72 13 36 RESET TO73 14 35 AVDD TO74 15 34 AVREF TO75 16 33 P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVSS VDD1 P26/TI52/TO52 P25/TI51/TO51 P24/TI50/TO50 P23/TxD01 P22/RxD01 P21/TxD00 P20/RxD00 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Cautions 1. In the normal operation mode, connect the VPP pin directly to VSS0. 2. In the flash memory writing mode, connect the VPP pin to VSS0 via a 10 kΩ pull-down resistor. Remark When the µPD78F0988A and 78F0988A(A) are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended. 6 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) Address/data bus RxD00, RxD01: Receive data ADTRG: AD trigger input SCK: Serial clock ANI0 to ANI7: Analog input SI: Serial input ASTB: Address strobe SO: Serial output AVDD: Analog power supply TI000, TI001, AVREF: Analog reference voltage TI010, TI011, AVSS: Analog ground TI50 to TI52: INTP0 to INTP7: External interrupt input TO00, TO01, P00 to P03: Port 0 TO50 to TO52, P10 to P17: Port 1 TO70 to TO75: P20 to P26: Port 2 TOFF7: Timer output off P30 to P37: Port 3 TxD00, TxD01: Transmit data P40 to P47: Port 4 VDD0, VDD1: Power supply P50 to P57: Port 5 VPP: Programming power supply P64 to P67: Port 6 VSS0, VSS1: Ground RD: Read strobe WAIT: Wait RESET: Reset WR: Write strobe Real-time port X1, X2: Crystal AD0 to AD7: RTP0 to RTP7: Data Sheet U15801EJ1V0DS Timer input Timer output 7 µPD78F0988A, 78F0988A(A) BLOCK DIAGRAM TI000/TO00/INTP4/P54 TI010/INTP5/P55 TI001/TO01/INTP6/P56 TI011/INTP7/P57 16-bit timer/ event counter 00 8-bit timer/ event counter 50 TO51/TI51/P25 8-bit timer/ event counter 51 P10 to P17 Port 2 P20 to P26 Port 3 P30 to P37 Port 4 P40 to P47 Port 5 P50 to P57 Port 6 P64 to P67 Flash memory 78K/0 CPU core (60 KB) Real-time output port TxD00/P21 RxD00/P20 UART00 TxD01/P23 RxD01/P22 UART01 RAM (1024 bytes) SCK/P51 SI/P52 Port 1 8-bit timer/ event counter 52 Watchdog timer RTP0/P30 to RTP7/P37 P00 to P03 16-bit timer/ event counter 01 TO50/TI50/P24 TO52/TI52/P26 Port 0 SIO3 SO/P53 ANI0/P10 to ANI7/P17 ADTRG/INTP3/P03 AVDD AVSS AVREF INTP0/TOFF7/P00 INTP1/P01 and INTP2/P02 INTP3/ADTRG/P03 INTP4/TI000/TO00/P54 INTP5/TI010/P55 INTP6/TI001/TO01/P56 INTP7/TI011/P57 A/D converter AD0/P40 to AD7/P47 RD/P64 External access WR/P65 WAIT/P66 Interrupt control ASTB/P67 RESET TO70 to TO75 8 Real-time pulse unit VDD0, VDD1 VSS0, VSS1 VPP Data Sheet U15801EJ1V0DS System control X1 X2 µPD78F0988A, 78F0988A(A) CONTENTS 1. DIFFERENCES BETWEEN µPD78F0988A AND MASK ROM VERSIONS ................................... 10 2. DIFFERENCES BETWEEN µPD78F0988A AND µPD78F0988 ...................................................... 11 3. PIN FUNCTIONS ................................................................................................................................ 12 3.1 Port Pins .................................................................................................................................................... 12 3.2 3.3 Non-Port Pins ........................................................................................................................................... 13 Pin I/O Circuits and Recommended Connection of Unused Pins .................................................... 15 4. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ........................................................... 17 5. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) ............................................. 18 6. FLASH MEMORY PROGRAMMING ................................................................................................. 19 6.1 6.2 Selection of Communication Mode ....................................................................................................... 19 Flash Memory Programming Functions ............................................................................................... 20 6.3 Connection of Flashpro III ...................................................................................................................... 20 7. ELECTRICAL SPECIFICATIONS ...................................................................................................... 22 8. PACKAGE DRAWINGS ..................................................................................................................... 38 9. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 41 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................. 42 APPENDIX B. RELATED DOCUMENTS ................................................................................................ 48 Data Sheet U15801EJ1V0DS 9 µPD78F0988A, 78F0988A(A) 1. DIFFERENCES BETWEEN µPD78F0988A AND MASK ROM VERSIONS The µPD78F0988A is a product with a flash memory which enables on-board writing, erasing and rewriting of programs. Except for flash memory specifications, the same functions as those of mask ROM versions can be obtained by setting the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS). Table 1-1 shows the differences between the flash memory version (µPD78F0988A) and mask ROM versions (µPD780982, 780983, 780984, 780986, 780988). Table 1-1. Differences Between µPD78F0988A and Mask ROM Versions µPD78F0988A Item Mask ROM Versions Internal ROM structure Flash memory Mask ROM Internal ROM capacities 60 KB µPD780982: µPD780983: µPD780984: µPD780986: µPD780988: 16 24 32 48 60 Internal expansion RAM capacities 1024 bytes µPD780982: µPD780983: µPD780984: µPD780986: µPD780988: None None None 1024 bytes 1024 bytes Change of internal ROM capacity with internal memory size switching register (IMS) AvailableNote 1 Not available Change of internal expansion RAM capacity with internal expansion RAM size switching register (IXS) AvailableNote 2 Not available TEST pin Not provided Provided VPP pin Provided Not provided KB KB KB KB KB Notes 1. Flash memory capacity becomes 60 KB by RESET input. 2. Internal expansion RAM capacity becomes 0 bytes by RESET input. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM versions. In addition, when replacing the µPD78F0988 with the µPD78F0988A, be sure to also conduct sufficient evaluation with the µPD78F0988A. 10 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) 2. DIFFERENCES BETWEEN µPD78F0988A AND µPD78F0988 The differences between the µPD78F0988A and µPD78F0988 (old version) are shown in Table 2-1. Table 2-1. Differences Between µPD78F0988A and µPD78F0988 Part Number µPD78F0988A µPD78F0988 (Old Version) Item Flash memory area Two areas 0: 0 to 1FFFH 1: 2000H to EFFFH Quality grade • Standard • Special (64-pin plastic QFP (14 × 14), 64-pin plastic LQFP (14 × 14)) Three areas 0: 0 to 1FFFH 1: 2000H to 7FFFH 2: 8000H to EFFFH Data Sheet U15801EJ1V0DS • Standard 11 µPD78F0988A, 78F0988A(A) 3. PIN FUNCTIONS 3.1 Port Pins Pin Name P00 I/O I/O Function Port 0 After Reset Input Alternate Function INTP0/TOFF7 P01 4-bit I/O port INTP1 P02 Input/output can be specified in 1-bit units. INTP2 P03 Use of an on-chip pull-up resistor can be specified by INTP3/ADTRG software setting. P10 to P17 Input Port 1 Input ANI0 to ANI7 Input RxD00 8-bit input only port P20 I/O Port 2 P21 7-bit I/O port TxD00 P22 Input/output can be specified in 1-bit units. RxD01 P23 Use of an on-chip pull-up resistor can be specified by TxD01 P24 software setting. TI50/TO50 P25 TI51/TO51 P26 P30 to P37 TI52/TO52 I/O Port 3 Input RTP0 to RTP7 Input AD0 to AD7 8-bit I/O port Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by software setting. P40 to P47 I/O Port 4 8-bit I/O port Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by software setting. P50 I/O Port 5 Input — P51 8-bit I/O port SCK P52 Input/output can be specified in 1-bit units. SI P53 LEDs can be driven directly. SO P54 Use of an on-chip pull-up resistor can be specified by INTP4/TI000/TO00 P55 software setting. INTP5/TI010 P56 INTP6/TI001/TO01 P57 INTP7/TI011 P64 P65 I/O Port 6 Input 4-bit I/O port RD WR P66 Input/output can be specified in 1-bit units. WAIT P67 Use of an on-chip pull-up resistor can be specified by ASTB software setting. 12 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) 3.2 Non-Port Pins (1/2) Pin Name INTP0 I/O Input Function After Reset Alternate Function External interrupt request input for which the valid edge Input P00/TOFF7 INTP1 (rising edge, falling edge, or both rising and falling Input P01 INTP2 edges) can be specified Input P02 Input P03/ADTRG INTP3 INTP4 Input P54/TI000/TO00 INTP5 Input P55/TI010 INTP6 Input P56/TI001/TO01 INTP7 Input P57/TI011 External count clock input to 8-bit timer/event counter 50 Input P24/TO50 TI51 External count clock input to 8-bit timer/event counter 51 Input P25/TO51 TI52 External count clock input to 8-bit timer/event counter 52 Input P26/TO52 TI000 External count clock input to 16-bit timer/event counter 00 Input P54/INTP4/TO00 Input P55/INTP5 Input P56/INTP6/TO01 Input P57/INTP7 8-bit timer/event counter 50 output Input P24/TI50 TO51 8-bit timer/event counter 51 output Input P25/TI51 TO52 8-bit timer/event counter 52 output Input P26/TI52 TO00 16-bit timer/event counter 00 output Input P54/INTP4/TI000 TO01 16-bit timer/event counter 01 output Input P56/INTP6/TI001 RTP0 to RTP7 Output Real-time output port that outputs pulses in synchronization Input P30 to P37 TI50 Input Capture trigger input to capture register (CR000, CR010) of 16-bit timer/event counter 00 TI010 Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00 TI001 External count clock input to 16-bit timer/event counter 01 Capture trigger input to capture register (CR001, CR011) of 16-bit timer/event counter 01 TI011 Capture trigger input to capture register (CR001) of 16-bit timer/event counter 01 TO50 Output with trigger signals outputs from the real-time pulse unit TxD00 Output Asynchronous serial interface serial data output TxD01 RxD00 Input Asynchronous serial interface serial data input RxD01 Input P21 Input P23 Input P20 Input P22 SCK I/O Serial interface serial clock input/output Input P51 SI Input Serial interface serial data input Input P52 SO Output Serial interface serial data output Input P53 ANI0 to ANI7 Input A/D converter analog input Input P10 to P17 ADTRG External trigger signal input to the A/D converter Input P03/INTP3 TO70 to TO75 Output Timer output for the 3-phase PWM inverter control Hi-Z TOFF7 Input Timer output (TO70 to TO75) stop external input Input AD0 to AD7 I/O Address/data bus for expanding memory externally Input P40 to P47 RD Output Strobe signal output for reading from external memory Input P64 Strobe signal output for writing to external memory Input P65 WAIT Input Wait insertion at external memory access Input P66 ASTB Output Strobe output that externally latches address information Input P67 Input WR – P00/INTP0 output to ports 4 and 5 to access external memory AVREF AVDD Input – A/D converter reference voltage input – – A/D converter analog power supply – – Data Sheet U15801EJ1V0DS 13 µPD78F0988A, 78F0988A(A) 3.2 Non-Port Pins (2/2) Pin Name AVSS I/O – Function After Reset Alternate Function A/D converter ground potential – – RESET Input System reset input – – X1 Input Connecting crystal resonator for system clock oscillation – – – – X2 – VDD0 – Positive power supply for ports – – VSS0 – Ground potential for ports – – VDD1 – Positive power supply except for ports – – VSS1 – Ground potential except for ports – – VPP – High-voltage application during program write/verify. – – In the normal operation mode, connect directly to VSS0. 14 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin I/O Circuits Pin Name P00/INTP0/TOFF7 I/O Circuit Type 8-C I/O I/O Recommended Connection of Unused Pins Input: Independently connect to VSS0 via a resistor. Output: Leave open P01/INTP1 P02/INTP2 P03/INTP3/ADTRG P10/ANI0 to P17/ANI7 25 Input Independently connect to VDD0 or VSS0 via a resistor. P20/RxD00 8-C I/O Input: P21/TxD00 P22/RxD01 5-H 8-C Leave open. P23/TxD01 5-H P24/TI50/TO50 8-C Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open. P25/TI51/TO51 P26/TI52/TO52 P30/RTP0 to P37/RTP7 5-H P40/AD0 to P47/AD7 P50 P51/SCK 8-C P52/SI 5-H P53/SO P54/INTP4/TI000/TO00 P55/INTP5/TI010 P56/INTP6/TI001/TO01 P57/INTP7/TI011 P64/RD P65/WR P66/WAIT P67/ASTB TO70 to TO75 4 Output RESET 2 Input AVDD – AVREF – – Connect to VDD0. Connect to VSS0. AVSS VPP Connect directly to VSS0. Data Sheet U15801EJ1V0DS 15 µPD78F0988A, 78F0988A(A) Figure 3-1. Pin I/O Circuits Type 2 Type 8-C VDD0 Pullup enable P-ch VDD0 Data IN P-ch IN/OUT Output disable N-ch VSS0 Schmitt-triggered input with hysteresis characteristics Type 4 Type 25 VDD0 Data P-ch P-ch Comparator + OUT Output disable – N-ch VSS0 VREF (threshold voltage) N-ch VSS0 Push-pull output that enables high-impedance output Input enable (both P-ch and N-ch are off) Type 5-H Pullup enable Data VDD0 P-ch VDD0 P-ch IN/OUT Output disable N-ch VSS0 Input enable 16 Data Sheet U15801EJ1V0DS IN µPD78F0988A, 78F0988A(A) 4. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used. By setting this register, the internal memory of the µPD78F0988A and µPD78F0988 can be mapped in the same manner as that of a mask ROM version with a different internal memory (ROM and RAM) capacity. IMS is set with an 8-bit memory manipulation instruction. IMS is set to CFH by RESET input. Figure 4-1. Format of Internal Memory Size Switching Register 7 IMS 6 5 RAM2 RAM1 RAM0 4 0 3 2 1 0 ROM3 ROM2 ROM1 ROM0 Address After reset R/W FFF0H CFH R/W ROM3 ROM2 ROM1 ROM0 Selection of internal ROM capacity 0 1 0 0 16 KB 0 1 1 0 24 KB 1 0 0 0 32 KB 1 1 0 0 48 KB 1 1 1 1 60 KB Other than above RAM2 RAM1 RAM0 1 1 0 Other than above Setting prohibited Selection of internal high-speed RAM capacity 1024 bytes Setting prohibited Table 4-1 shows the IMS setting values to make the memory mapping the same as that of mask ROM versions. Table 4-1. Setting Value of Internal Memory Size Switching Register Target Mask ROM Versions IMS Setting Value µPD780982 C4H µPD780983 C6H µPD780984 C8H µPD780986 CCH µPD780988 CFH Data Sheet U15801EJ1V0DS 17 µPD78F0988A, 78F0988A(A) 5. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) IXS is a register that sets the internal expansion RAM capacity by software setting. By using this register, the memory of the µPD78F0988A and µPD78F0988A(A) can be mapped in the same manner as that of a mask ROM version with a different internal expansion RAM capacity. IXS is set with an 8-bit memory manipulation instruction. IXS is set to 0CH by RESET input. Figure 5-1. Format of Internal Expansion RAM Size Switching Register IXS 7 6 5 0 0 0 4 3 2 1 0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 Address After reset R/W FFF4H 0CH R/W IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 Selection of internal expansion RAM capacity 0 1 0 1 0 1024 bytes 0 1 1 0 0 No internal expansion RAM Other than above Setting prohibited Table 5-1 shows the IXS setting values to make the memory mapping the same as that of mask ROM versions. Table 5-1. Setting Value of Internal Expansion RAM Size Switching Register Target Mask ROM Versions µPD780982 IXS Setting Value 0CH µPD780983 µPD780984 µPD780986 0AH µPD780988 18 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) 6. FLASH MEMORY PROGRAMMING On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is done after connecting a dedicated flash programmer (Flashpro III (part numbers FL-PR3 and PG-FP3)) to the host machine and target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro III. Remark 6.1 FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd. Selection of Communication Mode Writing to flash memory is performed using Flashpro III with a serial communication mode. Select the communication mode for writing from Table 6-1. For the selection of the communication mode, a format like the one shown in Figure 6-1 is used. The communication modes are selected using the VPP pulse numbers shown in Table 6-1. Table 6-1. Communication Mode List Communication Mode Pin UsedNote 1 Number of Channels Number of VPP Pulses 3-wire serial I/O 1 SCK/P51 SI/P52 SO/P53 0 3-wire serial I/O + HS 1 P50 (HS) SCK/P51 SI/P52 SO/P53 3 UART 1 RxD00/P20 TxD00/P21 8 Pseudo 3-wire serial I/O modeNote 2 1 P24/TI50/TO50 (Serial data input) P25/TI51/TO51 (Serial data output) P26/TI52/TO52 (Serial clock input) 12 Notes 1. Shifting to the flash memory programming mode sets all pins not used for flash memory programming to the same state as that immediately after reset. If the external device connected to each port does not acknowledge the state immediately after reset, pin handling such as connecting to VDD or VSS via a resistor is required. 2. Serial transfer is performed by controlling ports using software. Caution Always select the communication mode according to the number of VPP pulses shown in Table 61. Figure 6-1. Communication Mode Selection Format VPP pulses 10 V VPP VDD VSS 1 2 n VDD RESET VSS Flash memory write mode Data Sheet U15801EJ1V0DS 19 µPD78F0988A, 78F0988A(A) 6.2 Flash Memory Programming Functions Flash memory writing is performed via command and data transmit/receive operations using the selected communication mode. The main functions are listed in Table 6-2. Table 6-2. Main Functions of Flash Memory Programming Function 6.3 Description Batch erase Erases the contents of the entire memory. Batch blank check Checks that the entire memory has been erased. Data write Performs writing to flash memory according to the write start address and the number of the data to be written (the number of bytes). Batch verify Compares the contents of the entire memory and the input data. Write back Countermeasure for the over-erase state of the flash memory. Connection of Flashpro III The connection of the Flashpro III and the µPD78F0988A differs depending on the communication mode. The types of connections are shown in Figures 6-2, 6-3, and 6-4. Figure 6-2. Connection of Flashpro III Using 3-Wire Serial I/O Mode µ PD78F0988A Flashpro III VPP VDD VPP VDD1 VDD0 CLK X1 Note RESET RESET SCK SCK SO SI SI SO VSS1 GND Note 20 VSS0 For input to X1, a normal oscillator can also be used instead of CLK. Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) Figure 6-3. Connection of Flashpro III Using 3-Wire Serial I/O Mode (When Using Handshake) µ PD78F0988A Flashpro III VPP VPP VDD1 VDD VDD0 X1Note RESET CLK RESET SCK SO SCK SI SI HS SO P50 (HS) VSS1 VSS0 GND Note For input to X1, a normal oscillator can also be used instead of CLK. Figure 6-4. Connection of Flashpro III Using UART µ PD78F0988A Flashpro III VPP VPP VDD1 VDD VDD0 CLK X1Note RESET RESET SO RxD00 SI TxD00 VSS1 VSS Note VSS0 For input to X1, a normal oscillator can also be used instead of CLK. Figure 6-5. Connection of Flashpro III Using Pseudo 3-Wire Serial I/O Mode µ PD78F0988A Flashpro III VPP VPP VDD1 VDD VDD0 CLK X1Note RESET RESET SCK P26 (Serial clock input) SO P24 (Serial data input) P25 (Serial data output) VSS1 VSS0 SI VSS Note For input to X1, a normal oscillator can also be used instead of CLK. Data Sheet U15801EJ1V0DS 21 µPD78F0988A, 78F0988A(A) 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Conditions Input voltage VDD VPP AVDD AVREF AVSS VI Output voltage Analog input voltage VO VAN Output current, high IOH Per pin P00, P01, P30 to P37, P40 to P47, P50 to P57, P64 to P67 total P02, P03, P20 to P26, TO70 to TO75 total Output current, low IOLNote P00 to P03, P10 to P17, P20 to P26, P30 to P37, P40 to P47, P64 to P67 per pin P50 to P57, TO70 to TO75 per pin Operating ambient temperature Storage temperature TA P00 to P03, P10 to P17, P20 to P26, P30 to P37, P50 to P57, P64 to P67, TO70 to TO75, X1, X2, RESET P10 to P17 Analog input pin Ratings Unit –0.3 to +6.5 –0.3 to +10.5 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –0.3 to +0.3 –0.3 to VDD + 0.3 V V V V V V –0.3 to VDD + 0.3 AVSS – 0.3 to AVREF + 0.3 and –0.3 to VDD + 0.3 V V –10 –15 –15 mA mA mA 20 10 30 15 100 70 30 15 100 70 100 70 –40 to +85 +10 to +40 –40 to +125 mA mA mA mA mA mA mA mA mA mA mA mA °C °C °C Peak value rms value Peak value rms value P00, P01, P30 to P37, P40 to P47, P64 to P67 Peak value total rms value P02, P03, P20 to P26 total Peak value rms value TO70 to TO75 total Peak value rms value P50 to P57 total Peak value rms value In normal operating mode In flash memory programming mode Tstg The rms value should be calculated as follows: [rms value] = [Peak value] × √Duty Note Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz Unmeasured pins returned to 0 V 15 pF I/O capacitance CIO f = 1 MHz P00 to P03, P20 to P26, P30 Unmeasured pins to P37, P40 to P47, P50 to returned to 0 V P57, P64 to P67, TO70 to TO75 15 pF Remark 22 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 4.0 to 5.5 V) Resonator Ceramic resonator Recommended Circuit VPP X2 C1 Crystal resonator X1 C2 VPP X2 C1 External clock X1 C2 X2 µPD74HCU04 X1 Parameter Conditions Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 1.0 After VDD reaches oscillation voltage range MIN. Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 MIN. 1.0 After VDD reaches oscillation voltage range MIN. TYP. MAX. Unit 8.38 MHz 4 ms 8.38 MHz 10 ms X1 input frequency (fX)Note 1 1.0 8.38 MHz X1 input high-/lowlevel width (tXH, tXL) 50 500 ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS1. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. Data Sheet U15801EJ1V0DS 23 µPD78F0988A, 78F0988A(A) Recommended Oscillator Constant System clock: Ceramic resonator (TA = –40 to +85°C) Manufacturer Part Number Frequency (MHz) Recommended Circuit Constant C1 (pF) C2 (pF) Oscillation Voltage Range MIN. (V) MAX. (V) Murata Mfg. CSA2.00MG040 2.00 100 100 4.0 5.5 Co., Ltd. CST2.00MG040 2.00 On-chip On-chip 4.0 5.5 CSA3.58MG 3.58 30 30 4.0 5.5 CST3.58MGW 3.58 On-chip On-chip 4.0 5.5 CSA4.00MG 4.00 30 30 4.0 5.5 CST4.00MGW 4.00 On-chip On-chip 4.0 5.5 CSA4.19MG 4.19 30 30 4.0 5.5 CST4.19MGW 4.19 On-chip On-chip 4.0 5.5 CSA4.91MG 4.91 30 30 4.0 5.5 CST4.91MGW 4.91 On-chip On-chip 4.0 5.5 CSA5.00MG 5.00 30 30 4.0 5.5 CST5.00MGW 5.00 On-chip On-chip 4.0 5.5 Caution CSA7.37MTZ 7.37 30 30 4.0 5.5 CST7.37MTW 7.37 On-chip On-chip 4.0 5.5 CSA8.00MTZ 8.00 30 30 4.0 5.5 CST8.00MTW 8.00 On-chip On-chip 4.0 5.5 CSA8.38MTZ 8.38 30 30 4.0 5.5 CST8.38MTW 8.38 On-chip On-chip 4.0 5.5 The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, contact directly the manufacturer of the resonator you will use. 24 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) DC Characteristics (TA = –40 to +85°C, VDD = 4.0 to 5.5 V) Parameter Input voltage, high Symbol Conditions MIN. ILIL2 ILOH P10 to P17, P21, P23, P30 to P37, P40 to P47, P50, P53, P64 to P67 RESET, P00 to P03, P20, P22, P24 to P26, P51, P52, P54 to P57 X1, X2 P10 to P17, P21, P23, P30 to P37, P40 to P47, P50, P53, P64 to P67 RESET, P00 to P03, P20, P22, P24 to P26, P51, P52, P54 to P57 X1, X2 4.5 V ≤ VDD ≤ 5.5 V, IOH = –1 mA IOH = –100 µA P50 to P57, TO70 to TO75 5.0 V ≤ VDD ≤ 5.5 V, IOL = 15 mA P00 to P03, P20 to P26, 5.0 V ≤ VDD ≤ 5.5 V, P30 to P37, P40 to P47, IOL = 1.6 mA P64 to P67 IOL = 400 µA VIN = VDD P00 to P03, P10 to P17, P20 to P26, P30 to P37, P40 to P47, P50 to P57, P64 to P67, TO70 to TO75, RESET X1, X2 VIN = 0 V P00 to P03, P10 to P17, P20 to P26, P30 to P37, P40 to P47, P50 to P57, P64 to P67, TO70 to TO75, RESET X1, X2 VOUT = VDD ILOL VOUT = 0 V R2 VIN = 0 V P00 to P03, P20 to P26, P30 to P37, P40 to P47, P50 to P57, P64 to P67 8.38 MHz crystal VDD = 5.0 V ±10%Note 2 When A/D oscillation converter operating mode stopped When A/D converter operating 8.38 MHz crystal VDD = 5.0 V ±10%Note 2 When peripheral oscillation HALT function mode stopped When peripheral function operating VIH1 VIH2 Input voltage, low VIH3 VIL1 VIL2 Output voltage, high Output voltage, low Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Software pull-up resistor Power supply currentNote 1 VIL3 VOH1 VOL1 VOL2 ILIH1 ILIH2 ILIL1 IDD1 IDD2 IDD3 VPP supply voltage VPP1 STOP mode MAX. Unit 0.7VDD VDD V 0.8VDD VDD V VDD – 0.5 0 VDD 0.3VDD V V 0 0.2VDD V 0 VDD – 1.0 VDD – 0.5 0.4 VDD VDD 2.0 V V V V 0.4 V 0.5 3 V µA 20 –3 µA µA –20 3 µA µA –3 µA 30 90 kΩ 15 30 mA 16 32 mA 1.3 2.6 mA 7.3 mA 30 µA 0.2VDD V 0.4 15 VDD = 5.0 V ±10% In normal operation mode TYP. 0.1 0 Notes 1. Refers to the total current flowing to the internal power supply (VDD0 and VDD1). The peripheral operation current is included, but the current flowing to the pull-up resistors of ports and the AVREF pin is not. 2. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U15801EJ1V0DS 25 µPD78F0988A, 78F0988A(A) AC Characteristics (1) Basic operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V) Parameter Cycle time (Min. instruction execution time) TI000, TI001, TI010, TI011 input frequency TI000, TI001, TI010, TI011 input high-/ low-level width TI50, TI51, TI52 input frequency TI50, TI51, TI52 input high-/ low-level width Interrupt request input high-/ low-level width TOFF input high-/low-level width RESET input low-level width Note Symbol MAX. Unit 0.24 32 µs fTI0 0 fX/64 MHz tTIH0 tTIL0 2/fsam + 0.1Note TCY Conditions Operating with system clock MIN. TYP. µs fTI5 8-/16-bit precision 0 4 MHz tTIH5 tTIL5 8-/16-bit precision 100 ns tINTH tINTL INTP0 to INTP7 1 µs tTOFFH tTOFFL 2 µs tRSL 10 µs Selection of fsam = fX, fX/4, fX/32 is possible with bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00) or with bits 0 and 1 (PRM010, PRM011) of prescaler mode register 01 (PRM01). Note that when selecting TI000 (TM00) or TI001 (TM01) valid edge as the count clock, fsam = fX/16. 26 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) TCY VS VDD (System clock operation) 32.0 Cycle time TCY [ µ s] 10.0 Guaranteed operation range 5.0 2.0 1.0 0.24 0.1 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 Supply voltage VDD [V] Data Sheet U15801EJ1V0DS 27 µPD78F0988A, 78F0988A(A) (2) Read/write operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V) Parameter ASTB high-level width Symbol Conditions MIN. MAX. Unit tASTH 0.3tCY ns Address setup time tADS 20 ns Address hold time tADH 6 ns Data input time from address tADD1 (2 + 2n)tCY – 54 ns tADD2 (3 + 2n)tCY – 60 ns Address output time from RD↓ tRDAD Data input time from RD↓ tRDD1 0 tRDD2 Read data hold time RD low-level width WAIT↓ input time from RD↓ 100 ns (2 + 2n)tCY – 87 ns (3 + 2n)tCY – 93 ns tRDH 0 ns tRDL1 (1.5 + 2n)tCY – 33 ns tRDL2 (2.5 + 2n)tCY – 33 ns tRDWT1 tCY – 43 ns tRDWT2 tCY – 43 ns 0.5tCY – 25 ns (2 + 2n)tCY ns WAIT↓ input time from WR↓ tWRWT WAIT low-level width tWTL (0.5 + 2n)tCY + 10 Write data setup time tWDS 60 ns Write data hold time tWDH 6 ns WR low-level width tWRL (1.5 + 2n)tCY – 15 ns Delay time from ASTB↓ to RD↓ tASTRD 6 ns Delay time from ASTB↓ to WR↓ tASTWR 2tCY – 15 Delay time from RD↑ at external tRDAST 0.8tCY – 15 tRDWD 40 ns 1.2tCY ns fetch to ASTB↑ Write data output time from RD↑ ns Write data output time from WR↓ tWRWD 10 60 ns Delay time from WAIT↑ to RD↑ tWTRD 0.8tCY 2.5tCY + 25 ns Delay time from WAIT↑ to WR↑ tWTWR 0.8tCY 2.5tCY + 25 ns Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, RD, WR, WAIT, and ASTB pins.) 28 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) (3) Serial interface (TA = –40 to +85°C, VDD = 4.0 to 5.5 V) (a) 3-wire serial I/O mode (SCK... Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK cycle time tKCY1 954 ns SCK high-/low-level width tKH1 tKCY1/2 – 50 ns 100 ns tKL1 SI setup time (to SCK↑) tSIK1 SI hold time (from SCK↑) tKSI1 Delay time from SCK↓ tKSO1 400 ns C = 100 pFNote 300 ns MAX. Unit to SO output Note C is the load capacitance of the SCK and SO output lines. (b) 3-wire serial I/O mode (SCK... External clock input) Parameter SCK cycle time SCK high-/low-level width Symbol Conditions MIN. TYP. tKCY2 800 ns tKH2 400 ns tKL2 SI setup time (to SCK↑) tSIK2 100 ns SI hold time (from SCK↑) tKSI2 400 ns Delay time from SCK↓ tKSO2 C = 100 pFNote 300 ns MAX. Unit 125000 bps MAX. Unit 115200 bps ±0.87 % 0.24/fbrNote µs to SO output Note C is the load capacitance of the SCK and SO output lines. (c) UART mode (UART00) (Dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate (d) UART mode (UART00) (Infrared data transfer mode) Parameter Symbol Conditions MIN. TYP. Transfer rate Bit rate allowable error Output pulse width 1.2 Input pulse width 4/fX Note µs fbr: Set baud rate (e) UART mode (UART01) (Dedicated baud rate generator output) Parameter Symbol Conditions Transfer rate Data Sheet U15801EJ1V0DS MIN. TYP. MAX. Unit 38400 bps 29 µPD78F0988A, 78F0988A(A) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH VIH3 (MIN.) VIL3 (MAX.) X1 input TI Timing 1/fTI0 tTIL0 tTIH0 TI000, TI001, TI010, TI011 1/fTI5 tTIL5 tTIH5 TI50, TI51, TI52 TOFF Timing tTOFFL TOFF7 30 Data Sheet U15801EJ1V0DS tTOFFH µPD78F0988A, 78F0988A(A) Read/Write Operation External fetch (no wait): tADD1 AD0 to AD7 8-bit address tADS tADH Hi-Z Operation code tRDAD tRDD1 tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH External fetch (wait insertion): tADD1 AD0 to AD7 Hi-Z 8-bit address tADS tADH tRDAD Operation code tRDD1 tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH WAIT tRDWT1 tWTL Data Sheet U15801EJ1V0DS tWTRD 31 µPD78F0988A, 78F0988A(A) External data access (no wait): tADD2 AD0 to AD7 Hi-Z tRDAD tRDD2 8-bit address tADS tADH Read data tASTH Hi-Z Write data tRDH ASTB RD tASTRD tRDWD tRDL2 tWDS tWDH tWRWD WR tASTWR tWRL External data access (wait insertion): AD0 to AD7 8-bit address tADS tADH tASTH tADD2 Hi-Z Read data Hi-Z Write data tRDAD tRDH tRDD2 ASTB tASTRD RD tRDWD tRDL2 tWDS tWDH tWRWD WR tASTWR tWRL WAIT tRDWT2 32 tWTL tWTRD Data Sheet U15801EJ1V0DS tWRWT tWTL tWTWR µPD78F0988A, 78F0988A(A) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK tSIKm SI tKSIm Input data tKSOm SO Output data m = 1, 2 Data Sheet U15801EJ1V0DS 33 µPD78F0988A, 78F0988A(A) A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions TYP. MAX. Unit 10 10 bit 4.0 V ≤ AVREF ≤ 5.5 V ±0.2 ±0.4 %FSR 2.7 V ≤ AVREF < 4.0 V ±0.3 ±0.6 %FSR Resolution Overall 10 errorNote Conversion time Zero-scale error tCONV Note Full-scale errorNote Non-linearity error Differential non-linearity error Analog input voltage VIAN Reference voltage AVREF Resistance between AVREF and AVSS RREF Note MIN. 4.0 V ≤ AVREF ≤ 5.5 V 14 96 µs 2.7 V ≤ AVREF < 4.0 V 19 96 µs 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR 2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR 2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR 4.0 V ≤ AVREF ≤ 5.5 V ±2.5 LSB 2.7 V ≤ AVREF < 4.0 V ±4.5 LSB 4.0 V ≤ AVREF ≤ 5.5 V ±1.5 LSB 2.7 V ≤ AVREF < 4.0 V ±2.0 LSB 0 AVREF V 2.7 AVDD V When A/D converter is not operating 20 40 kΩ Excludes quantization error (±1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C) Parameter Symbol Data retention power supply voltage VDDDR Data retention power supply current IDDDR Release signal set time tSREL Oscillation stabilization tWAIT wait time Note Conditions TYP. 2.0 VDDDR = 2.0 V 0.1 MAX. Unit 5.5 V 10 µA µs 0 Release by RESET 217/fX ms Release by interrupt request Note ms Selection of 212/fX and 214/fX to 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). 34 MIN. Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode Operation mode STOP mode Data retention mode VDD tSREL VDDDR STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal) HALT mode Operation mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT Interrupt Request Input Timing tINTH tINTL INTP0 to INTP7 RESET Input Timing tRSL RESET Data Sheet U15801EJ1V0DS 35 µPD78F0988A, 78F0988A(A) Flash Memory Programming Characteristics (TA = 10 to 40°C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V, VPP = 9.7 to 10.3 V) (1) Basic characteristics Parameter Symbol Operation frequency Conditions MIN. fX Supply voltage 1.0 VDD MAX. Unit 8.38 MHz 4.0 5.5 V VPPL When VPP low-level is detected 0 0.2VDD V VPP When VPP high-level is detected 0.8VDD VDD 1.2VDD V VPPH When VPP high-voltage is detected 9.0 10.0 10.5 V When programming 9.7 10.0 10.3 V Number of rewrites CWRT 20Note Programming temperature TPRG 10 Note TYP. Times 40 °C Operation is not guaranteed for over 20 rewrites. Remark After execution of the program command, execute the verify command and check that the writing has been completed normally. (2) Serial write operation characteristics Parameter Symbol Conditions MIN. Set time from VDD↑ to VPP↑ tDRPSR VPP high voltage 0 µs Set time from VPP↑ to RESET↑ tPSRRF VPP high voltage 1.0 µs VPP count start time from RESET↑ tRFCF VPP high voltage 1.0 µs Count execution time tCOUNT VPP counter high-level width tCH 8.0 VPP counter low-level width tCL 8.0 VPP counter noise elimination width tNFW VDD tDRPSR tRFCF tCH VPPH VPP tCL VPPL tPSRRF tCOUNT VDD RESET (input) 0V 36 Data Sheet U15801EJ1V0DS Unit ms µs µs 40 VDD VPP MAX. 20 Flash Write Mode Setting Timing 0V TYP. ns µPD78F0988A, 78F0988A(A) (3) Write erase characteristics Parameter Symbol Conditions During flash memory programming MIN. TYP. MAX. Unit 9.7 10.0 10.3 V VPP supply voltage VPP2 VDD supply current IDD When VPP = VPP2, fXX = 8.38 MHz 40 mA VPP supply current IPP When VPP = VPP2 100 mA Step erase time Ter Note 1 0.201 s 20 s/area 50.6 ms 60 Times/ 0.199 Overall erase time per area Tera When step erase time = 0.2 Write-back time Twb Note 3 Number of write-backs per write-back command Cwb 49.4 When write-back time = 50 0.2 sNote 2 50 msNote 4 writeback command Number of erase/ write-backs Cerwb Step write time Twr Note 5 48 Overall write time per word Twrw When step write time = 50 µs (1 word = 1 byte)Note 6 48 Number of rewrites per area Cerwr 1 erase + 1 write after erase = 1 rewriteNote 7 50 16 Times 52 µs 520 µs/ word 20 Times/ area Notes 1. The recommended setting value for the step erase time is 0.2 s. 2. The prewrite time before erasure and the erase verify time (write-back time) is not included. 3. The recommended setting value for the write-back time is 50 ms. 4. Write-back is executed once by the issuance of the write-back command. Therefore, the number of retries must be the maximum value minus the number of commands issued. 5. Recommended step write setting value is 50 µs. 6. The actual write time per word is 100 µs longer. The internal verify time during or after a write is not included. 7. When a product is first written after shipment, “erase → write” and “write only” are both taken as one rewrite. Example: P: Write, E: Erase Shipped product → P → E → P → E → P: 3 rewrites Shipped product → E → P → E → P → E → P: 3 rewrites Remarks 1. The range of the operating clock during flash memory programming is the same as the range during normal operation. 2. When using the PG-FP3, the time parameters that need to be downloaded from the parameter files for write/erase are automatically set. Unless otherwise directed, do not change the set values. Data Sheet U15801EJ1V0DS 37 µPD78F0988A, 78F0988A(A) 8. PACKAGE DRAWINGS 64-PIN PLASTIC SDIP (19.05mm(750)) 64 33 1 32 A K J L I M F D N C M R B H G NOTES 1. Each lead centerline is located within 0.17 mm of its true position (T.P.) at maximum material condition. 2. Item "K" to center of leads when formed parallel. ITEM MILLIMETERS A 58.0 +0.68 −0.20 B 1.78 MAX. C 1.778 (T.P.) D 0.50±0.10 F 0.9 MIN. G 3.2±0.3 H 0.51 MIN. I 4.05 +0.26 −0.20 J 5.08 MAX. K 19.05 (T.P.) L 17.0±0.2 M 0.25 +0.10 −0.05 N 0.17 R 0 ∼ 15° P64C-70-750A,C-4 38 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) 64-PIN PLASTIC QFP (14x14) A B 48 49 33 32 detail of lead end S C D Q 64 1 R 17 16 F J G H I M P K S N S L M NOTE ITEM Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 17.6±0.4 B 14.0±0.2 C 14.0±0.2 D 17.6±0.4 F 1.0 G 1.0 H 0.37 +0.08 −0.07 I J 0.15 0.8 (T.P.) K 1.8±0.2 L 0.8±0.2 M 0.17 +0.08 −0.07 N 0.10 P 2.55±0.1 Q 0.1±0.1 R 5°±5° S 2.85 MAX. P64GC-80-AB8-5 Data Sheet U15801EJ1V0DS 39 µPD78F0988A, 78F0988A(A) 64-PIN PLASTIC LQFP (14x14) A B 48 49 33 32 detail of lead end S P C D T R 64 1 L 17 16 U Q F G J H I M ITEM K S N M S MILLIMETERS A 17.2±0.2 B 14.0±0.2 C 14.0±0.2 D 17.2±0.2 F 1.0 G 1.0 H 0.37 +0.08 −0.07 I 0.20 J K 0.8 (T.P.) NOTE L 0.8 Each lead centerline is located within 0.20 mm of its true position (T.P.) at maximum material condition. M 0.17 +0.03 −0.06 N 0.10 P 1.4±0.1 Q 0.127±0.075 +4° 3° −3° R S T U 1.6±0.2 1.7 MAX. 0.25 0.886±0.15 P64GC-80-8BS 40 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) 9. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC sales representative. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). Table 9-1. Surface Mounting Type Soldering Conditions (1) µPD78F0988AGC-AB8: 64-pin plastic QFP (14 × 14) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Three times or less IR35-00-3 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Three times or less VP15-00-3 Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) –– Caution Do not use different soldering methods together (except for partial heating). (2) µPD78F0988AGC(A)-AB8: Soldering Method 64-pin plastic QFP (14 × 14) Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less IR35-00-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Two times or less VP15-00-2 Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) –– Caution Do not use different soldering methods together (except for partial heating). Table 9-2. Insertion Type Soldering Conditions µPD78F0988ACW: 64-pin plastic SDIP (19.05 mm (750)) Soldering Method Soldering Condition Wave soldering (only for pins) Solder bath temperature: 260°C max., Time: 10 seconds max. Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package. Data Sheet U15801EJ1V0DS 41 µPD78F0988A, 78F0988A(A) APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD780988 Subseries. Also refer to (5) Cautions on Using Development Tools. (1) Software package SP78K0 Software package common to 78K/0 Series (2) Language processing software RA78K0 Assembler package common to 78K/0 Series CC78K0 C compiler package common to 78K/0 Series DF780988 Device file for µPD780988 Subseries CC78K0-L C compiler library source file common to 78K/0 Series (3) Flash memory writing tools Flashpro III (part No. FL-PR3, PG-FP3) Flash programmer dedicated to on-chip flash memory microcontroller FA-64CW FA-64GC FA-64GC-8BS-A Adapter for flash memory writing. Used connected to Flashpro III. • FA-64CW: for 64-pin plastic SDIP (CW type) • FA-64GC: for 64-pin plastic QFP (GC-AB8 type) • FA-64GC-8BS-A: for 64-pin plastic LQFP (GC-8BS type) (4) Debugging tools • When IE-78K0-NS, IE-78K0-NS-A in-circuit emulator is used IE-78K0-NS In-circuit emulator common to 78K/0 Series IE-78K0-NS-PA Performance board for enhancement and expansion of IE-78K0-NS functions IE-78K0-NS-A Combination of IE-78K0-NS and IE-78K0-NS-PA IE-70000-MC-PS-B Power supply unit for IE-78K0-NS IE-70000-98-IF-C Interface adapter necessary when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) IE-70000-CD-IF-A PC card and interface cable when notebook PC is used as host machine (PCMCIA socket supported) IE-70000-PC-IF-C Interface adapter necessary when using IBM PC/ATTM or compatible as host machine (ISA bus supported) IE-70000-PCI-IF-A Adapter necessary when using PCI bus incorporated personal computer as host machine IE-780988-NS-EM4, IE-78K0-NS-P01 Emulation board and I/O board to emulate µPD780988 Subseries NP-64CW Emulation probe for 64-pin plastic SDIP (CW type) NP-64GC NP-64GC-TQ NP-H64GC-TQ Emulation probe for 64-pin plastic QFP (GC-AB8 type), 64-pin plastic LQFP (GC-8BS type) EV-9200GC-64 Conversion socket to connect the NP-64GC and a target system board on which the 64-pin plastic QFP (GC-AB8 type), 64-pin plastic LQFP (GC-8BS type) can be mounted TGC-064SAP Conversion adapter to connect the NP-64GC-TQ or NP-H64GC-TQ and a target system board on which the 64-pin plastic QFP (GC-AB8 type), 64-pin plastic LQFP (GC-8BS type) can be mounted ID78K0-NS Integrated debugger for IE-78K0-NS SM78K0 System simulator common to 78K/0 Series DF780988 Device file for µPD780988 Subseries 42 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) • When IE-78001-R-A in-circuit emulator is used IE-78001-R-A In-circuit emulator common to 78K/0 Series IE-70000-98-IF-C Adapter necessary when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) IE-70000-PC-IF-C Adapter necessary when using IBM PC/AT or compatible as host machine (ISA bus supported) IE-70000-PCI-IF-A Adapter necessary when using PCI bus incorporated personal computer as host machine IE-78000-R-SV3 Interface adapter and cable when using EWS as host machine IE-780988-NS-EM4, Emulation board and I/O board to emulate µPD780988 Subseries IE-78K0-NS-P01 IE-78K0-R-EX1 Emulation probe conversion board necessary when using IE-780988-NS-EM4 and IE-78K0-NS-P01 on IE-78001-R-A EP-78240CW-R Emulation probe for 64-pin plastic SDIP (CW type) EP-78240GC-R Emulation probe for 64-pin plastic QFP (GC-AB8 type), 64-pin plastic LQFP (GC-8BS type) EV-9200GC-64 Socket to connect target system board made for mounting 64-pin plastic QFP (GC-AB8 type) or 64-pin plastic LQFP (GC-8BS type) and EP-78240GC-R ID78K0 Integrated debugger for IE-78001-R-A SM78K0 System simulator common to 78K/0 Series DF780988 Device file for µPD780988 Subseries (5) Real-time OS RX78K0 Real-time OS for 78K/0 Series (6) Cautions on using development tools • The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780988. • The CC78K0 and RX78K0 are used in combination with the RA78K0 or DF780988. • The FL-PR3, FA-64CW, FA-64GC, NP-64CW, NP-64GC, NP-64GC-TQ, and NP-H64GC-TQ are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191). • The TGC-064SAP is a product made by TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672) • For third-party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide (U11069E). • The host machine and OS suitable for each software are as follows. Host Machine [OS] EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] Software PC PC-9800 series [Japanese WindowsTM] IBM PC/AT and compatibles [Japanese/English Windows] RA78K0 √Note √ CC78K0 √Note √ ID78K0-NS √ – ID78K0 √ – SM78K0 √ – RX78K0 √Note √ Note DOS-based software Data Sheet U15801EJ1V0DS 43 µPD78F0988A, 78F0988A(A) (7) Cautions on designing target system The connection condition diagrams for an emulation probe, conversion connector, and conversion socket or conversion adapter are shown below. Design the system taking into consideration the dimension or shape, etc. of the parts to be mounted on the target system. Table A-1. Distance Between In-Circuit Emulator and Conversion Socket Emulation Probe Conversion Adapter, Conversion Socket Distance Between In-Circuit Emulator and Conversion Socket or Conversion Adapter NP-64GC EV-9200GC-64 170 mm NP-64GC-TQ TGC-064SAP 170 mm NP-H64GC-TQ NP-64CW 370 mm – 160 mm Figure A-1. Distance Between In-Circuit Emulator and Conversion Socket or Conversion Adapter (1) In-circuit emulator: IE-78K0-NS or IE-78K0-NS-A Target system Emulation board: IE-780988-NS-EM4 CN6 (64GC) 170 mm Emulation probe: NP-64GC, NP-64GC-TQ Conversion socket: EV-9200GC-64, Conversion adapter: TGC-064SAP 44 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) Figure A-2. Distance Between In-Circuit Emulator and Conversion Socket or Conversion Adapter (2) In-circuit emulator: IE-78K0-NS or IE-78K0-NS-A Target system Emulation board: IE-780988-NS-EM4 CN6 (64GC) 370 mm Emulation probe: NP-H64GC-TQ Conversion adapter: TGC-064SAP Figure A-3. Distance Between In-Circuit Emulator and Conversion Socket or Conversion Adapter (3) In-circuit emulator: IE-78K0-NS or IE-78K0-NS-A Target system Emulation board: IE-780988-NS-EM4 CN7 (64CW) 160 mm Emulation probe: NP-64CW IC socket Data Sheet U15801EJ1V0DS 45 µPD78F0988A, 78F0988A(A) Figure A-4. Connection Condition of Target System (1) Emulation probe: NP-64GC Emulation board: IE-780988-NS-EM4 25 mm 35 mm 50 mm 10 mm 10 mm Conversion socket: EV-9200GC-64 1 pin 35 mm 18.5 mm 60 mm Target system Figure A-5. Connection Condition of Target System (2) Emulation probe: NP-64GC-TQ Emulation board: IE-780988-NS-EM4 25 mm 40 mm 34 mm 23 mm 11 mm 17 mm 1 pin 17 mm 65 mm Target system Conversion adapter: TGC-064SAP 46 Data Sheet U15801EJ1V0DS 34 mm µPD78F0988A, 78F0988A(A) Figure A-6. Connection Condition of Target System (3) Emulation probe: NP-H64GC-TQ Emulation board: IE-780988-NS-EM4 10.0 mm 42 mm 45 mm 23 mm 11 mm Conversion adapter: TGC-064SAP 1 pin 17 mm 45 mm 17 mm 52 mm Target system Figure A-7. Connection Condition of Target System (4) Emulation probe: NP-64CW Emulation board: IE-780988-NS-EM4 25 mm 40 mm 34 mm 20 mm 14 mm 33 mm 13 mm 34 mm 8 mm 24 mm Target system Data Sheet U15801EJ1V0DS 47 µPD78F0988A, 78F0988A(A) APPENDIX B. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Documents related to devices Document Name Document No. µPD780988 Subseries User’s Manual U13029E µPD780982, 780983, 780984, 780986, 780988, 780982(A), 780983(A), 780984(A), 780986(A), 780988(A) Data Sheet U12804E µPD78F0988A, 78F0988A(A) Data Sheet This manual µPD780988 Subseries Inverter Control Application Note U13119E 78K/0 Series Instructions User’s Manual U12326E • Documents related to development software tools (user’s manuals) Document Name RA78K0 Assembler Package Document No. Operation U14445E Language U14446E Structured Assembly Language U11789E Operation U14297E Language U14298E SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later Operation (Windows Based) U14611E SM78K Series System Simulator Ver. 2.10 or Later External Part User Open Interface Specifications U15006E ID78K0-NS Integrated Debugger Ver. 2.00 or Later Operation (Windows Based) U14379E ID78K0 Integrated Debugger Windows Based Reference U11539E Guide U11649E Fundamentals U11537E Installation U11536E CC78K0 C Compiler RX78K0 Real-Time OS Project Manager Ver. 3.12 or Later (Windows Based) U14610E • Documents related to development hardware tools (user’s manuals) Document Name Document No. IE-78K0-NS In-Circuit Emulator U13731E IE-78K0-NS-A In-Circuit Emulator U14889E IE-78001-R-A In-Circuit Emulator U14142E IE-78K0-R-EX1 In-Circuit Emulator To be prepared 48 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) • Documents related to flash memory writing Document Name PG-FP3 Flash Memory Programmer User’s Manual Document No. U13502E • Other related documents Document Name Document No. SEMICONDUCTORS SELECTION GUIDE - Products & Packages - X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U15801EJ1V0DS 49 µPD78F0988A, 78F0988A(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. FIP and IEBus are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. 50 Data Sheet U15801EJ1V0DS µPD78F0988A, 78F0988A(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 Data Sheet U15801EJ1V0DS 51 µPD78F0988A, 78F0988A(A) • The information in this document is current as of September, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4