MOSEL V53C8256H

MOSEL VITELIC
PRELIMINARY
V53C8256H
ULTRA-HIGH SPEED,
256K x 8 FAST PAGE MODE
CMOS DYNAMIC RAM
HIGH PERFORMANCE
35
40
45
50
Max. RAS Access Time, (tRAC)
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (tCAA)
18 ns
20 ns
22 ns
24 ns
Min. Fast Page Mode Cycle Time, (tPC)
21 ns
23 ns
25 ns
28 ns
Min. Read/Write Cycle Time, (tRC)
70 ns
75 ns
80 ns
90 ns
Features
Description
■ 256K x 8-bit organization
■ Fast Page Mode for a sustained data rate
of 47 MHz
■ RAS access time: 35, 40, 45, 50 ns
■ Low power dissipation
■ Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
■ Refresh Interval: 512 cycles/8 ms
■ Single 5V ± 10% Power Supply
■ Available in 24-pin 300 mil Plastic DIP,
26/24-pin 300 mil SOJ, and 28-pin TSOP-I
packages
The V53C8256H is a high speed 262,144 x 8 bit
CMOS dynamic random access memory. The
V53C8256H offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to 512
(x8) bits within a row with cycle times as short as 21
ns. Because of static circuitry, the CAS clock is not
in the critical timing path. The flow-through column
address latches allow address pipelining while relaxing many critical system timing requirements for
fast usable speed. These features make the
V53C8256H ideally suited for graphics, digital signal processing and high performance computing
systems.
Device Usage Chart
Operating
Temperature
Range
P
K
T
0°C to 70 °C
•
•
•
V53C8256H Rev. 1.2 July 1997
Package Outline
Access Time (ns)
Power
50
60
70
Std.
Temperature
Mark
•
•
•
•
Blank
1
V53C8256H
MOSEL VITELIC
V
5
3
C
8
2
FAMILY
Description
Pkg.
Pin Count
Plastic DIP
P
24
SOJ
K
26/24
TSOP-I
T
28
5
6
DEVICE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PKG
SPEED
( t RAC)
P (PLASTIC DIP)
K (SOJ)
T (TSOP-I)
24-Pin Plastic DIP
PIN CONFIGURATION
Top View
VSS
I/O1
I/O2
I/O3
I/O4
WE
RAS
A0
A1
A2
A3
VDD
H
TEMP.
PWR.
BLANK (0°C to 70°C)
BLANK (NORMAL)
35
40
45
50
(35 ns)
(40 ns)
(45 ns)
(50 ns)
26/24-Pin SOJ
PIN CONFIGURATION
Top View
VSS
I/O8
I/O7
I/O6
I/O5
CAS
OE
A8
A7
A6
A5
A4
8256H-02
VSS
I/O1
I/O2
I/O3
I/O4
WE
1
2
3
4
5
6
27
26
24
23
22
21
VSS
I/O8
I/O7
I/O6
I/O5
CAS
RAS
A0
A1
A2
A3
VDD
8
9
10
11
12
13
19
18
17
16
15
14
OE
A8
A7
A6
A5
A4
8256H-03
28-Pin TSOP-I
PIN CONFIGURATION
Top View
V53C8256H Rev. 1.2 July 1997
8256H-01
Pin Names
2
A0–A8
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O1–I/O8
Data Input, Output
VDD
+5V Supply
VSS
0V Supply
NC
No Connect
V53C8256H
MOSEL VITELIC
Absolute Maximum Ratings*
Capacitance*
Ambient Temperature
Under Bias .............................. –10°C to +80°C
Storage Temperature (plastic) ...... -55°C to +125°C
Voltage Relative to VSS ...................–1.0V to +7.0V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.0 W
TA = 25°C, VDD = 5 V ± 10%, VSS = 0 V
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
*Note: Capacitance is sampled and not 100% tested.
Symbol
Parameter
Min.
Max.
CIN1
Unit
Address Input
3
4
pF
CIN2
RAS, CAS, WE, OE
4
5
pF
COUT
Data Input/Output
5
7
pF
Block Diagram
256K x 8
OE
WE
CAS
RAS
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VDD
VSS
I/O 1
DATA I/O BUS
I/O 2
COLUMN DECODERS
Y0 -Y8
SENSE AMPLIFIERS
I/O 3
I/O
BUFFER
I/O 6
REFRESH
COUNTER
I/O 7
I/O 8
512 x 8
•
•
•
A
7
A8
V53C8256H Rev. 1.2 July 1997
X 0 -X8
ROW
DECODERS
A1
ADDRESS BUFFERS
AND PREDECODERS
9
A0
I/O 4
I/O 5
512
MEMORY
ARRAY
8256H-05
3
V53C8256H
MOSEL VITELIC
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified.
V53C8256H
Symbol
Parameter
Access
Time
Min.
Typ.
Max.
Unit
Test Conditions
Notes
ILI
Input Leakage Current
(any input pin)
–10
10
µA
VSS ≤ VIN ≤ VCC
ILO
Output Leakage Current
(for High-Z State)
–10
10
µA
VSS≤ VOUT ≤ VCC
RAS, CAS at VIH
ICC1
VCC Supply Current,
Operating
35
160
mA
tRC = tRC (min.)
40
150
45
145
50
135
4
mA
RAS, CAS at VIH
other inputs ≥ VSS
35
160
mA
tRC = tRC (min.)
2
40
150
45
145
50
135
35
95
mA
Minimum Cycle
1, 2
40
90
45
85
50
80
ICC2
VCC Supply Current,
TTL Standby
ICC3
VCC Supply Current,
RAS-Only Refresh
ICC4
VCC Supply Current,
Fast Page Mode
Operation
1, 2
ICC5
VCC Supply Current,
Standby, Output Enabled
2
mA
RAS = VIH, CAS = VIL,
other inputs ≥ VSS
ICC6
VCC Supply Current,
CMOS Standby
1
mA
RAS ≥ VCC – 0.2 V,
CAS ≥ VCC – 0.2 V,
All other inputs ≥ VSS
VIL
Input Low Voltage
–1
0.8
V
3
VIH
Input High Voltage
2.4
VCC + 1
V
3
VOL
Output Low Voltage
0.4
V
IOL = 4.2 mA
VOH
Output High Voltage
V
IOH = –5 mA
V53C8256H Rev. 1.2 July 1997
2.4
4
1
V53C8256H
MOSEL VITELIC
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
35
40
45
50
#
JEDEC
Symbol
Symbol
Parameter
1
tRL1RH1
tRAS
RAS Pulse Width
35
2
tRL2RL2
tRC
Read or Write Cycle Time
70
75
80
90
ns
3
tRH2RL2
tRP
RAS Precharge Time
25
25
25
30
ns
4
tRL1CH1
tCSH
CAS Hold Time
35
40
45
50
ns
5
tCL1CH1
tCAS
CAS Pulse Width
12
12
13
14
ns
6
tRL1CL1
tRCD
RAS to CAS Delay
16
7
tWH2CL2
tRCS
Read Command Setup Time
0
0
0
0
ns
8
tAVRL2
tASR
Row Address Setup Time
0
0
0
0
ns
9
tRL1AX
tRAH
Row Address Hold Time
6
7
8
9
ns
10
tAVCL2
tASC
Column Address Setup Time
0
0
0
0
ns
11
tCL1AX
tCAH
Column Address Hold Time
4
5
6
7
ns
12
tCL1RH1(R)
tRSH (R)
RAS Hold Time (Read Cycle)
12
12
13
14
ns
13
tCH2RL2
tCRP
CAS to RAS Precharge Time
5
5
5
5
ns
14
tCH2WX
tRCH
Read Command Hold Time
Referenced to CAS
0
0
0
0
ns
5
15
tRH2WX
tRRH
Read Command Hold Time
Referenced to RAS
0
0
0
0
ns
5
16
tOEL1RH2
tROH
RAS Hold Time Referenced
to OE
8
8
9
10
ns
17
tGL1QV
tOAC
Access Time from OE
12
12
13
14
ns
18
tCL1QV
tCAC
Access Time from CAS
12
12
13
14
ns
6, 7
19
tRL1QV
tRAC
Access Time from RAS
35
40
45
50
ns
6, 8, 9
20
tAVQV
tCAA
Access Time from Column
Address
18
20
22
24
ns
6, 7, 10
21
tCL1QX
tLZ
OE or CAS to Low-Z Output
0
ns
16
22
tCH2QZ
tHZ
OE or CAS to High-Z Output
0
ns
16
23
tRL1AX
tAR
Column Address Hold Time
from RAS
28
24
tRL1AV
tRAD
RAS to Column Address
Delay Time
11
25
tCL1RH1(W)
tRSH (W)
RAS or CAS Hold Time in
Write Cycle
12
12
13
14
ns
26
tWL1CH1
tCWL
Write Command to CAS Lead
Time
12
12
13
14
ns
27
tWL1CL2
tWCS
Write Command Setup Time
0
0
0
0
ns
28
tCL1WH1
tWCH
Write Command Hold Time
5
5
6
7
ns
V53C8256H Rev. 1.2 July 1997
Min. Max. Min. Max. Min. Max. Min. Max. Unit
5
75K
23
40
17
75K
28
0
6
0
12
18
75K
32
0
6
30
17
45
0
13
19
75K
36
0
7
35
20
50
0
8
40
23
14
Notes
ns
ns
4
ns
26
ns
11
12, 13
V53C8256H
MOSEL VITELIC
AC Characteristics (Cont’d)
35
40
45
50
#
JEDEC
Symbol
Symbol
Parameter
29
tWL1WH1
tWP
Write Pulse Width
5
5
6
7
ns
30
tRL1WH1
tWCR
Write Command Hold Time
from RAS
28
30
35
40
ns
31
tWL1RH1
tRWL
Write Command to RAS Lead
Time
12
12
13
14
ns
32
tDVWL2
tDS
Data in Setup Time
0
0
0
0
ns
14
33
tWL1DX
tDH
Data in Hold Time
4
5
6
7
ns
14
34
tWL1GL2
tWOH
Write to OE Hold Time
5
6
7
8
ns
14
35
tGH2DX
tOED
OE to Data Delay Time
5
6
7
8
ns
14
36
tRL2RL2
(RMW)
tRWC
Read-Modify-Write Cycle Time
105
110
115
130
ns
37
tRL1RH1
(RMW)
tRRW
Read-Modify-Write Cycle
RAS Pulse Width
70
75
80
87
ns
38
tCL1WL2
tCWD
CAS to WE Delay
28
30
32
34
ns
12
39
tRL1WL2
tRWD
RAS to WE Delay in ReadModify-Write Cycle
54
58
62
68
ns
12
40
tCL1CH1
tCRW
CAS Pulse Width (RMW)
46
48
50
52
ns
41
tAVWL2
tAWD
Col. Address to WE Delay
35
38
41
42
ns
42
tCL2CL2
tPC
Fast Page Mode
21
23
25
28
ns
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Notes
12
Read or Write Cycle Time
43
tCH2CL2
tCP
CAS Precharge Time
4
5
6
7
ns
44
tAVRH1
tCAR
Column Address to RAS
Setup Time
18
20
22
24
ns
45
tCH2QV
tCAP
Access Time from Column
Precharge
46
tRL1DX
tDHR
Data in Hold Time Referenced
to RAS
28
30
35
40
ns
47
tCL1RL2
tCSR
CAS Setup Time
CAS-before-RAS Refresh
10
10
10
10
ns
48
tRH2CL2
tRPC
RAS to CAS Precharge Time
0
0
0
0
ns
49
tRL1CH1
tCHR
CAS Hold Time
CAS-before-RAS Refresh
8
8
10
12
ns
50
tCL2CL2
(RMW)
tPCM
Fast Page Mode Read-ModifyWrite Cycle Time
58
60
65
70
ns
tT
tT
Transition Time (Rise and Fall)
3
tREF
Refresh Interval (512 Cycles)
V53C8256H Rev. 1.2 July 1997
20
50
8
6
22
3
50
8
24
3
50
8
27
3
ns
7
50
ns
15
8
ms
17
V53C8256H
MOSEL VITELIC
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two
transitions per address cycle in Fast Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VCC.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to two TTL inputs and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.).
9. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ≥ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C8256H Rev. 1.2 July 1997
7
V53C8256H
MOSEL VITELIC
Waveforms of Read Cycle
t RC (2)
t RAS (1)
RAS
t RP (3)
tAR (23)
VIH
VIL
t CSH (4)
t CRP (13)
CAS
t RCD (8)
VIL
t CRP (13)
t RAD (24)
t RAH (9)
tASR (8)
ADDRESS
t RSH (R)(12)
t CAS (5)
VIH
VIH
ROW ADDRESS
VIL
t CAH (11)
t ASC (10)
COLUMN ADDRESS
t RCH (14)
t CAR (44)
t RCS (7)
WE
t ROH (15)
VIH
VIL
t ROH (16)
t CAA (20)
OE
tOAC (17)
VIH
V IL
t CAC (18)
tRAC (19)
I/O
tHZ (22)
t HZ (22)
VOH
VALID DATA-OUT
VOL
8256H-06
t LZ (21)
Waveforms of Early Write Cycle
t RC (2)
t RAS (1)
RAS
t RP (3)
tAR (23)
VIH
V IL
t CSH (4)
tCRP (13)
t RCD (6)
t RSH (W)(25)
t CAS (5)
VIH
CAS
V IL
t CAR (44)
t CAH (11)
t RAH (9)
tASR (8)
ADDRESS
t CRP (13)
VIH
V IL
tASC (10)
ROW ADDRESS
COLUMN ADDRESS
t WCH (28)
t RAD (24)
t CWL (26)
WE
t WP(29)
tWCS (27)
VIH
V IL
t WCR (30)
t RWL (31)
OE
VIH
V IL
t DHR (46)
tDS (32)
I/O
VIH
V IL
tDH (33)
VALID DATA-IN
HIGH-Z
8256H-07
Don’t Care
V53C8256H Rev. 1.2 July 1997
8
Undefined
V53C8256H
MOSEL VITELIC
Waveforms of Write Cycle (OE Controlled Write)
t RC (2)
tRAS (1)
RAS
V IL
t CSH (4)
t CRP (13)
t RCD (6)
t RSH (W)(12)
tCAS (5)
VIH
CAS
t CRP (13)
V IL
tRAD (24)
t RAH (9)
tASR (8)
ADDRESS
t RP (3)
t AR (23)
VIH
VIH
tASC (10)
ROW ADDRESS
V IL
t CAR (44)
t CAH (11)
COLUMN ADDRESS
t CWL (26)
t RWL (31)
t WP(29)
WE
VIH
V IL
t WOH (34)
OE
VIH
V IL
t OED (35)
I/O
tDH (33)
t DS (32)
VIH
VALID DATA-IN
V IL
8256H-09
Waveforms of Read-Modify-Write Cycle
tRWC (36)
tRRW (37)
RAS
tRP (3)
tAR (23)
VIH
VIL
t CSH (4)
t CRP (13)
tRCD (6)
tRSH (W)(25)
t CRW (40)
VIH
CAS
VIL
tCAH (11)
tRAH (9)
tASC (10)
tASR (8)
ADDRESS
VIH
ROW
ADDRESS
VIL
COLUMN
ADDRESS
tAWD (41)
tCWD (38)
t RAD (24)
tRWD (39)
WE
OE
tCRP (13)
t CWL (26)
tRWL (31)
tWP(29)
VIH
VIL
t CAA (20)
t OAC (17)
VIH
VIL
t OED (35)
tCAC (18)
tRAC (19)
I/O
VIH
VOH
VIL
VOL
tDH (33)
tHZ (22)
t DS (32)
VALID
DATA-OUT
VALID
DATA-IN
8256H-09
tLZ (21)
Don’t Care
V53C8256H Rev. 1.2 July 1997
9
Undefined
V53C8256H
MOSEL VITELIC
Waveforms of Fast Page Mode Read Cycle
RAS
tPC (42)
tCP(43)
tCSH (4)
t RAH (9)
tCAR (44)
tASC (10)
t CAH (11)
tASC (10)
VIH
ROW
ADDRESS
COLUMN
ADDRESS
t RCH (14)
t CAH (11)
t CAH (11)
COLUMN
ADDRESS
COLUMN
ADDRESS
t RCS (7)
t RCS (7)
t RCS (7)
V IL
tCAA (20)
t CAA (20)
t CAP (45)
t OAC (17)
tRRH (15)
t OAC (17)
VIH
V IL
tHZ (22)
tRAC (19)
tCAC (18)
t LZ (21)
t CAC (18)
tCAC (18)
t HZ (22)
VOH
tHZ (22)
tHZ (22)
VALID
DATA OUT
VOL
tHZ (22)
tHZ (22)
t LZ (21)
t LZ (21)
I/O
tRCH (14)
VIH
t OAC (17)
OE
t CRP (13)
t CAS (5)
tCAS (5)
V IL
V IL
WE
tRSH (R)(12)
t CAS (5)
VIH
tASR (8)
ADDRESS
RP (3)
V IL
t RCD (6)
tCRP (13)
CAS
t
t RAS (1)
tAR (23)
VIH
VALID
DATA OUT
VALID
DATA OUT
8256H-10
Waveforms of Fast Page Mode Write Cycle
tRP (3)
tAR (23)
RAS
t RAS (1)
VIH
V IL
t CRP (13)
tRCD (6)
CAS
t PC (42)
t CP(43)
t CAS (5)
VIH
t RSH (W)(25)
t CRP (13)
tCAS (5)
tCAS (5)
V IL
tCSH (4)
tRAH (9)
t CAR (44)
tASC (10)
t ASR (8)
ADDRESS
VIH
ROW
ADD
V IL
tASC (10)
tCAH (11)
tCAH (11)
COLUMN
ADDRESS
tRAD (24)
COLUMN
ADDRESS
t CWL (26)
t CWL (26)
t WCS (27)
t WCS (27)
tCWL (26)
t WCS (27)
t WCH (28)
t WCH (28)
t WP (29)
WE
t CAH (11)
COLUMN
ADDRESS
t WP(29)
tRWL(31)
t WCH (28)
tWP(29)
tDS (32)
tDH (33)
tDH (33)
VIH
V IL
OE
VIH
VIL
tDS (32)
t DH (33)
t DS (32)
I/O
VIH
V IL
VALID
DATA IN
VALID
DATA IN
OPEN
VALID
DATA IN
OPEN
8256H-11
Don’t Care
V53C8256H Rev. 1.2 July 1997
10
Undefined
V53C8256H
MOSEL VITELIC
Waveforms of Fast Page Mode Read-Write Cycle
tRAS (1)
VIH
RAS
V
IL
t CSH (4)
tRP (3)
tRCD (6)
tPCM (50)
t RSH (W)(25)
t CRP (13)
t CAS (5)
t CP(43)
t CAS (5)
V
IH
CAS
V
t CAS (5)
t RAD (24)
IL
tRAH (9)
t CAR (44)
tASC (10)
tASC (10)
tASR (8)
V
IH
ADDRESS
tCAH (11)
IL
tCAH (11)
COLUMN
ADDRESS
ROW
ADD
V
tASC (10)
t CAH (11)
COLUMN
ADDRESS
tRWD (39)
COLUMN
ADDRESS
tCWD (38)
t RCS (7)
t CWD (38)
tRWL(31)
tCWL (26)
t CWL (26)
t CWD (38)
t CWL (26)
V
IH
WE
V
IL
tAWD (41)
tAWD (41)
tAWD (41)
t WP(29)
t CAA (20)
t OAC (17)
tWP(29)
tWP(29)
t OAC (17)
t OAC (17)
V
IH
OE
V
IL
tCAP (45)
tCAP (45)
t CAA (20)
t CAA (20)
tOED (35)
tOED (35)
t CAC (18)
t RAC (19)
t CAC (18)
t HZ (22)
tHZ (22)
tDH (33)
t DH (33)
tDS (32)
tDS (32)
I/O
VI/OH
OUT
VI/OL
OUT
IN
tLZ (21)
t LZ (21)
t OED (35)
tCAC (18)
t HZ (22)
tDH (33)
tDS (32)
OUT
IN
IN
tLZ (21)
8256H-12
Waveforms of RAS Only Refresh Cycle
t RC (2)
RAS
t RAS (1)
V IH
t RP (3)
V IL
t CRP (13)
CAS
V IH
V IL
t ASR (8)
ADDRESS
V IH
t RAH (9)
ROWADDR
V IL
8256H-13
NOTE:
WE, OE = Don’t care
Don’t Care
V53C8256H Rev. 1.2 July 1997
11
Undefined
V53C8256H
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1)
RAS
t RP (3)
VIH
V IL
t CSR (47)
CAS
t CHR (49)
t RSH (W)(25)
tCAS (5)
t CP(43)
VIH
V IL
ADDRESS
VIH
V IL
READ CYCLE
WE
t RRH (15)
t RCH (14)
t RCS (7)
VIH
V IL
t ROH (16)
t OAC (17)
OE
VIH
V IL
t HZ (22)
t HZ (22)
t LZ (21)
I/O
VIH
DOUT
V IL
t RWL (31)
t CWL (26)
WRITE CYCLE
WE
t WCH (28)
t WCS (27)
VIH
V IL
OE
VIH
V IL
tDS (32)
I/O
VIH
t DH (33)
D IN
V IL
8256H-14
Waveforms of CAS-before-RAS Refresh Cycle
t RC (2)
t RP (3)
RAS
t RAS (1)
t RP (3)
VIH
V IL
t RPC (48)
t CP (43)
t CHR (49)
t CSR (47)
CAS
VIH
V IL
t HZ (22)
I/O
VOH
VOL
8256H-15
NOTE: WE, OE, A0–A7 = Don’t care
Don’t Care
V53C8256H Rev. 1.2 July 1997
12
Undefined
V53C8256H
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
tRC (2)
RAS
tRC (2)
t RP (3)
t RAS (1)
tAR (23)
VIH
t RP (3)
t RAS (1)
V IL
tRCD (6)
t CRP (13)
tRSH (R)(12)
t CHR (49)
tCRP (13)
VIH
CAS
V IL
tRAD (24)
tASC (10)
tASR (8)
t RAH (9)
ADDRESS
VIH
t CAH (11)
COLUMN
ADDRESS
ROW
ADD
V IL
tRCS (7)
WE
t RRH (15)
VIH
V IL
t CAA (20)
t OAC (17)
OE
VIH
V IL
t CAC (18)
t LZ (21)
t RAC (19)
I/O
t HZ (22)
t HZ (22)
VOH
VALID DATA
VOL
8256H-16
Waveforms of Hidden Refresh Cycle (Write)
t RC (2)
VIH
RAS
t RAS (1)
tRP (3)
V IL
t RCD (6)
t CRP (13)
CAS
t RC (2)
tRP (3)
t RAS (1)
tAR (23)
t RSH (12)
t CHR (49)
t CRP (13)
VIH
V IL
tRAD (24)
tASC (10)
tASR (8)
t RAH (9)
ADDRESS
VIH
V IL
t CAH (11)
ROW
ADD
COLUMN
ADDRESS
t WCH (28)
t WCS (27)
WE
VIH
V IL
VIH
OE
V IL
t DS (32)
VIH
I/O
V IL
tDH (33)
VALID DATA-IN
t DHR (46)
8256H-17
Don’t Care
V53C8256H Rev. 1.2 July 1997
13
Undefined
V53C8256H
MOSEL VITELIC
Functional Description
Refresh Cycle
The V53C8256H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional
dynamic RAM. The V53C8256H reads and writes
data by multiplexing an 18-bit address into a 9-bit
row and a 9-bit column address. The row address is
latched by the Row Address Strobe (RAS). The column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
To retain data, 512 Refresh Cycles are required
in each 8 ms period. There are two ways to refresh
the memory:
1. By clocking each of the 512 row addresses (A0
through A8) with RAS at least once every 8 ms.
Any Read, Write, Read-Modify-Write or RASonly cycle refreshes the addressed row.
2. Using a CAS-before-RAS Refresh Cycle. If CAS
makes a transition from low to high to low after
the previous cycle and before RAS falls, CASbefore-RAS
refresh
is
activated.
The
V53C8256H uses the output of an internal 9-bit
counter as the source of row addresses and ignore external address inputs.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time tRP/tCP has elapsed.
CAS-before-RAS is a “refresh-only” mode and no
data access or device selection is allowed. Thus,
the output remains in the High-Z state during the cycle. A CAS-before-RAS counter test mode is provided to ensure reliable operation of the internal
refresh counter.
Read Cycle
Fast Page Mode Operation
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only
when tOAC, tRAC, tCAA and tCAC are all satisifed. As
a result, the access time is dependent on the timing
relationships between these parameters. For example, the access time is limited by tCAA when tRAC,
tCAC and tOAC are all satisfied.
Fast Page Mode operation permits all 512 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining
RAS low while performing successive CAS cycles
retains the row address internally and eliminates the
need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through
latch while CAS is high. Thus, access begins from
the occurrence of a valid column address rather
than from the falling edge of CAS, eliminating tASC
and tT from the critical timing path. CAS latches the
address into the column address buffer and acts as
an output enable. During Fast Page Mode operation, Read, Write, Read-Modify-Write or ReadWrite-Read cycles are possible at random addresses within a row. Following the initial entry cycle into
Fast Page Mode, access is tCAA or tCAP controlled.
If the column address is valid prior to the rising edge
of CAS, the access time is referenced to the CAS
rising edge and is specified by tCAP. If the column
address is valid after the rising CAS edge, access
is timed from the occurrence of a valid address and
is specified by tCAA. In both cases, the falling edge
of CAS latches the address and enables the output.
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and tOED must be satisfied.
V53C8256H Rev. 1.2 July 1997
14
V53C8256H
MOSEL VITELIC
During Power-On, the VDD current requirement of
the V53C8256H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and IDD will exhibit
current transients. It is recommended that RAS and
CAS track with VDD or be held at a valid VIH during
Power-On to avoid current surges.
Fast Page Mode provides a sustained data rate of
47 MHz for applications that require high data rates
such as bit-mapped graphics or high-speed signal
processing. The following equation can be used to
calculate the maximum data rate:
512
Data Rate = ---------------------------------------t RC + 511 × t PC
Table 1. V53C8256H Data Output
Data Output Operation
Operation for Various Cycle Types
The V53C8256H Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected
row address in the Memory Array. A RAS high transition disables data transfer and latches the output
data if the output is enabled. After a memory cycle
is initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled,
can be disabled by holding OE high. The OE signal
has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE
goes low at a time in relationship to CAS that would
normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to
the WE low transition to allow Data In Setup Time
(tDS) to be satisfied.
Power-On
After application of the VDD supply, an initial
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
V53C8256H Rev. 1.2 July 1997
15
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled.
High OE = High-Z I/Os
Read-Modify-Write Cycles
Data from Addressed
Memory Cell
Fast Page Mode Read Cycle
Data from Addressed
Memory Cell
Fast Page Mode Write Cycle
(Early Write)
High-Z
Fast Page Mode ReadModify-Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
V53C8256H
MOSEL VITELIC
Package Diagrams
24-Pin 300 mil PDIP
0.300 – 0.330
[7.62 – 8.38]
0.250 – 0.300
[6.35 – 7.62]
.180 Max.
[4.57 Max.]
1.310 Max.
[33.27 Max.]
Unit in inches [mm]
0.005 – 0.050
[0.127 – 1.27]
0.110 – 0.140
[2.79 – 3.56]
.100 Typ.
[2.54 Typ.]
.008 – .013
[.203 – .330]
0.018 – 0.024
[0.457 – 0.610]
0.320 – 0.390
[8.13 – 9.91]
0.048 – 0.065
[1.22 – 1.65]
26/24-Pin 300 mil SOJ
0.332 – 0.342
[8.43 – 8.69]
0.296 – 0.304
[7.52 – 7.72]
0.665 – 0.698
[16.89 – 17.73]
0.125 – 0.135
[3.175 – 3.429]
0.082 – 0.093
[2.08 – 2.36]
0.028 Typ.
[0.711 Typ.]
V53C8256H Rev. 1.2 July 1997
0.05 Typ.
[1.27 Typ.]
0.018 Typ.
[0.457 Typ.]
0.025 Min.
[0.635 Min.]
16
0.255 – 0.275
[6.477 – 6.985]
Unit in inches [mm]
V53C8256H
MOSEL VITELIC
28-Pin TSOP-I
Unit in inches [mm]
.035 – .043
[.889 – 1.09]
Detail “A”
.520 – .535
[13.21 – 13.59]
.039 DIA.
[.991 DIA]
.000
.079 DIA. x .0004
Deep
.000
2.01 DIA. x .0102
Deep
Fixed Pin (1 Plcs.)
0.10 (.004)
[2.54 (.102)]
.461 – .469
[11.71 – 11.91]
.047
[1.19]
.035 – .043
[.889 – 1.09]
.002 – .006
[.051 – .152]
0.10
[2.54]
.055 – .063
[1.40 – 1.60]
.311 – .319
[7.90 – 8.10]
.55 [13.97]
.055 – .063
[1.40 – 1.60]
0.25
[6.35]
0.10
[2.54]
Top View
Bottom View
.055 – .063
[1.40 – 1.60]
See Detail “B”
D
.037 – .041
[.940 – 1.04]
See Detail “A”
D
.008 – .20
[.203 – 5.08]
.007 – .011
[.178 – .279]
0° – 6°
Gage Plane
.007 – .009
[.178 – .229]
.012 MAX
[.305 MAX]
With Plating
Base Metal
.004 – .008
[.102 – .203]
.020 – .028
[.508 – .711]
.004 – .006
[.102 – .152]
Detail “A”
Section “D-D”
V53C8256H Rev. 1.2 July 1997
17
0.25 BSC
[6.35 BSC]
Detail “B”
MOSEL VITELIC
WORLDWIDE OFFICES
V53C8256H
U.S.A.
TAIWAN
JAPAN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 011-886-2-545-1213
FAX: 011-886-2-545-1209
RM.302 ANNEX-G
HIGASHI-NAKANO
NAKANO-KU, TOKYO 164
PHONE: 011-81-03-3365-2851
FAX: 011-81-03-3365-2836
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 011-852-665-4883
FAX: 011-852-664-7535
1 CREATION ROAD I
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 011-886-35-783344
FAX: 011-886-35-792838
U.S. SALES OFFICES
NORTHWESTERN
SOUTHWESTERN
CENTRAL & SOUTHEASTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
SUITE 200
5150 E. PACIFIC COAST HWY.
LONG BEACH, CA 90804
PHONE: 310-498-3314
FAX: 310-597-2174
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 972-690-1402
FAX: 972-690-0341
NORTHEASTERN
SUITE 436
20 TRAFALGAR SQUARE
NASHUA, NH 03063
PHONE: 603-889-4393
FAX: 603-889-9347
© Copyright 1997, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
7/97
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461