WEDC WMF2M8

White Electronic Designs
WMF2M8-XXX5
2Mx8 MONOLITHIC FLASH, SMD 5962-97609
FEATURES
Access Times of 90, 120, 150ns
Low Power CMOS
Packaging:
• 56 lead, Hermetic Ceramic, 0.520" CSOP
(Package 207). Fits standard 56 SSOP footprint.
Data# Polling and Toggle Bit feature for detection of
program or erase cycle completion.
Supports reading or programming data to a sector
not being erased.
RESET# pin resets internal state machine to the
read mode.
Multiple Ground Pins for Low Noise Operation
• 44 pin Ceramic LCC**
Sector Architecture
• 32 equal size sectors of 64KBytes each
• Any combination of sectors can be erased. Also
supports full chip erase.
100,000 Write/Erase Cycles Minimum
* This data sheet describes a product that is subject to change without
notice.
Organized as 2Mx8
** Package to be developed.
Commercial, Industrial, and Military Temperature
Ranges
Note: For programming information refer to Flash Programming 16M5 Application Note.
5V Read and Write. 5V ± 10% Supply.
Fig. 1 – Pin Configuration for WMF2M8-XXX5
A15
A14
A13
A12
CS#
VCC
RESET#
A11
A10
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Ready/Busy
Reset
A9
6 5 4 3 2 1 44 43 42 41 40
A7
A6
A5
A4
NC
NC
NC
A3
A2
A1
A0
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
A16
A17
A18
A19
NC
NC
NC
A20
WE#
OE#
RY/BY#
I/O7
I/O6
I/O5
I/O4
VCC
GND
18 19 20 21 22 23 24 25 26 27 28
GND
I/O0-7
A0-20
WE#
CS#
OE#
VCC
GND
RY/BY#
RESET#
I/O2
NC
RESET#
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
VCC
NC
I/O1
NC
I/O0
A0
NC
NC
NC
I/O2
NC
I/O3
NC
GND
A8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
I/O1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O0
CS#
A12
A13
A14
A15
NC
NC
NC
A20
A19
A18
A17
A16
VCC
GND
I/O6
NC
I/O7
NC
RY/BY#
OE#
WE#
NC
NC
I/O5
NC
I/O4
VCC
44 CLCC**
Top View
Pin Description
I/O3
56 CSOP
Top View
** Package to be developed.
May 2004
Rev. 6
1
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White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
WMF2M8-XXX5
CAPACITANCE
TA = +25°C
Parameter
Symbol Ratings
Unit
Voltage on Any Pin Relative to VSS
VT
-2.0 to +7.0
V
Power Dissipation
PT
8
W
Storage Temperature
TSTG -65 to +125 °C
Short Circuit Output Current
IOS
100
mA
Endurance - Write/Erase Cycles (Mil Temp)
100,000 min cycles
Data Retention (Mil Temp)
20
years
Parameter
Address Input capacitance
Output Enable capacitance
Write Enable capacitance
Chip Select capacitance
Data I/O capacitance
Symbol
CAD
COE
CWE
CCS
CI/O
Conditions
Max Unit
VI/O = 0 V, f = 1.0MHz 12 pF
VIN = 0 V, f = 1.0MHz 12 pF
VIN = 0 V, f = 1.0MHz 12 pF
VIN = 0 V, f = 1.0MHz 12 pF
VI/O = 0 V, f = 1.0MHz 12 pF
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol Min
Supply Voltage
VCC
4.5
Ground
VSS
0
Input High Voltage
VIH
2.0
Input Low Voltage
VIL
-0.5
Operating Temperature (Mil.)
TA
-55
Operating Temperature (Ind.)
TA
-40
Typ
5.0
0
-
Max
5.5
0
VCC + 0.5
+0.8
+125
+85
Unit
V
V
V
V
°C
°C
DC CHARACTERISTICS — CMOS COMPATIBLE
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
VCC Active Current for Read (1)
VCC Active Current for Program or Erase (2)
VCC Standby Current
Output Low Voltage
Output High Voltage
Low VCC Lock-Out Voltage
Symbol
ILI
ILO
ICC1
ICC2
ICC3
VOL
VOH
VLKO
Conditions
VCC = 5.5, VIN = GND to VCC
VCC = 5.5, VIN = GND to VCC
CS# = VIL, OE# = VIH, f = 5MHz
CS# = VIL, OE# = VIH
VCC = 5.5, CS# = VIH, f = 5MHz, RESET# = Vcc ± 0.3V
IOL = 12.0 mA, VCC = 4.5
IOH = -2.5 mA, VCC = 4.5
Min
0.85xVCC
3.2
Max
10
10
40
60
2.0
0.45
4.2
Unit
µA
µA
mA
mA
mA
V
V
V
NOTES:
1. The Icc current listed includes both the DC operating current and the frequency
dependent component (@ 5MHz). The frequency component typically is less than
2mA/MHz, with OE# at VIH.
2. Icc active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V
May 2004
Rev. 6
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White Electronic Designs
WMF2M8-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS – WE# CONTROLLED
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
Write Cycle Time
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase (2)
Read Recovery Time before Write
VCC Setup Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
RESET# Pulse Width
tAVAV
tELWL
tWLWH
tAVWL
tDVWH
tWHDX
tWLAX
tWHWL
tWHWH1
tWHWH2
tGHWL
tVCS
-90
tWC
tCS
tWP
tAS
tDS
tDH
tAH
tWPH
Min
90
0
45
0
45
0
45
20
-120
Max
Min
120
0
50
0
50
0
50
20
300
15
0
50
0
50
10
500
Min
150
0
50
0
50
0
50
20
Unit
Max
300
15
300
15
0
50
44
256
tOEH
tRP
-150
Max
44
256
10
500
44
256
10
500
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
µs
sec
sec
ns
ns
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
AC CHARACTERISTICS – READ-ONLY OPERATIONS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Enable Hold Time
Chip Select High to Output High Z (1)
Output Enable High to Output High Z (1)
Output Hold from Addresses, CS# or OE# Change,
whichever is First
RESET# Low to Read Mode (1)
Symbol
tAVAV
tAVQV
tELQV
tGLQV
Read
Toggle &
Data Polling
tEHQZ
tGHQZ
tAXQX
-90
tRC
tACC
tCE
tOE
Min
90
-120
Max
Min
120
-150
Max
Min
150
Unit
Max
0
0
0
ns
ns
ns
ns
ns
10
10
10
ns
90
90
40
120
120
50
150
150
55
tOEH
tDF
tDF
tOH
tReady
20
20
0
30
30
0
20
35
35
ns
ns
ns
20
µs
0
20
1. Guaranteed by design, not tested.
May 2004
Rev. 6
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White Electronic Designs
WMF2M8-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED
VCC = 5.0V, VSS = 0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
Write Cycle Time
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
tAVAV
tWLEL
tELEH
tAVEL
tDVEH
tEHDX
tELAX
tEHEL
-90
tWC
tWS
tCP
tAS
tDS
tDH
tAH
tCPH
tWHWH1
tWHWH2
tGHEL
Min
90
0
45
0
45
0
45
20
-120
Max
Min
120
0
50
0
50
0
50
20
-150
Max
300
15
0
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
sec
sec
ns
300
15
0
44
256
44
256
10
Unit
Max
300
15
0
tOEH
Min
150
0
50
0
50
0
50
20
10
44
256
10
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
FIGURE 2 – AC TEST CIRCUIT
AC Test Conditions
Parameter
IOL
Current Source
VZ = 1.5V
(Bipolar Supply)
D.U.T.
Ceff = 50 pf
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
IOL
Current Source
HARDWARE RESET (RESET#)
Parameter
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET Pin Low (During Embedded Algorithms) to Read or Write (See Note)
Max
20
µs
tREADY
RESET Pin Low (Not During Embedded Algorithms) to Read or Write (See Note)
Max
500
ns
tRP
RESET Pulse Width
Min
500
ns
tRH
RESET High Time Before Read (See Note)
Min
50
ns
tRB
RY/BY Recovery Time
Min
0
ns
May 2004
Rev. 6
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WMF2M8-XXX5
FIGURE 3 – RESET# TIMING
RY/BY#
CS#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CS#, OE#
RESET#
tRP
May 2004
Rev. 6
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White Electronic Designs
WMF2M8-XXX5
FIGURE 4 – AC WAVEFORMS FOR READ OPERATIONS
tRC
Addresses Stable
Addresses
tACC
CS#
tDF
tOE
OE#
tOEH
tCE
WE#
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
May 2004
Rev. 6
0V
6
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White Electronic Designs
WMF2M8-XXX5
FIGURE 5 – WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED
Read Status Data (last two cycles)
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CS#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
A0h
Data
PD
Status
tBUSY
DOUT
tRB
RY/BY#
tVCS
VCC
Notes:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to the device.
4. Dout is the output of the data written to the device.
5. Figure indicates last two bus cycles of a four bus cycle sequence.
May 2004
Rev. 6
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WMF2M8-XXX5
FIGURE 6 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
tWC
tAS
2AAh
Addresses
VA
SA
VA
555h for chip erase
tAH
CS#
tCH
OE#
tWP
WE#
tWHWH2
tWPH
tC tCS
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for CHip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes: SA is the sector address for Sector Erase.
May 2004
Rev. 6
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WMF2M8-XXX5
FIG. 7 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALIGORITHM OPERATIONS
tRC
Addresses
VA
VA
VA
tACC
tCE
CS#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
DQ7
Complement
Complement
DQ0-DQ6
Status Data
Status Data
True
Valid Data
High Z
High Z
True
Valid Data
tBUSY
RY/BY#
Notes: VA = Valid Address. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.
May 2004
Rev. 6
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WMF2M8-XXX5
FIGURE 8 – ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS
XXX for program PA for program
SA for sector erase
XXX for erase
XXX for chip erase
Data Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CS#
tWS
tCPH
tDS
tBUSY
tDH
DQ7
Data
tRH
AO for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to the device.
4. Dout is the output of the data written to the device.
5. Figure indicates last two bus cycles of a four bus cycle sequence.
May 2004
Rev. 6
10
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White Electronic Designs
WMF2M8-XXX5
FIGURE 9 – TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CS#
tCH
tOE
OE#
tDF
tOEH
WE#
tOH
High Z
DQ6-DQ2
Valid Status
Valid Status
Valid Status
(first read)
(second read)
(stops toggling)
Valid Data
tBUSY
RY/BY#
Notes:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after
command sequence, last status read cycle and array data read cycle.
May 2004
Rev. 6
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WMF2M8-XXX5
FIGURE 10 – DQ2 VS. DQ6
Enter
Embedded
Erasing
Erase
Suspend
WE#
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Enter
Embedded
Erasing
Erase
Complete
Erase
Erase Suspend
Read
DQ6
DQ2
Note:
The system may use OE# or CS# to toggle DQ2 and DQ6. DQ6 toggles only when read
at an address within the erase-suspended sector.
TEMPORARY SECTOR UNPROTECTED
Parameter
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall time (see notes)
Min
500
ns
tRSP
RESET# setup time for temporary sector unprotect
Min
4
ms
Note:
Not 100% tested.
FIGURE 11 – TEMPORARY SECTOR GROUP UNPROTECTED TIMINGS
12V
RESET#
0 or 5V
0 or 5V
tVIDR
tVIDR
Program or Erase Command Sequence
CS#
WE#
tRSP
RY/BY#
May 2004
Rev. 6
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White Electronic Designs
WMF2M8-XXX5
PACKAGE 207: 56 LEAD, CERAMIC SOP
23.63 (0.930) ± 0.25 (0.010)
0.18 (0.007)
± 0.05 (0.002)
21.59 (0.850) TYP
2.87 (0.113)
MAX
1.02 (0.040)
± 0.18 (0.007)
12.96 (0.510)
± 0.15 (0.006)
16.13 (0.635)
± 0.13 (0.005)
1.60 (0.063) TYP
+
+
PIN 1
IDENTIFIER
0.80 (0.031) TYP
0.25 (0.010)
± 0.05 (0.002)
0.51 (0.020) TYP
R = 0.18 (0.007) TYP
0 / -4
SEE DETAIL "A"
4.06 (0.160)
MAX
DETAIL "A"
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE DIMENSION: 44 LEAD, CERAMIC LCC**
12.70 (0.500) TYP
1.27 (0.050)
TYP
12.70 (0.500)
TYP
0.53 (0.021)
0.74 (0.029)
PIN 1
1.14 (0.045)
1.40 (0.055)
16.26 (0.640)
16.67 (0.660)
3.05 (0.120)
MAX
16.26 (0.640)
16.67 (0.660)
PIN 1 IDENTIFIER
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
** Package to be developed.
May 2004
Rev. 6
13
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White Electronic Designs
WMF2M8-XXX5
ORDERING INFORMATION
W M F 2M 8 - XXX X X 5 X
LEAD FINISH:
Blank =
A
=
Gold plated leads
Solder dip leads
VPP PROGRAMMING VOLTAGE
5 = 5V
DEVICE GRADE:
M
= Military, 883 Screened
I
= Industrial
C
= Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
PACKAGE TYPE:
DA = 56 Lead CSOP (Package 207) fits standard 56 SSOP footprint
L
= 44 Lead Ceramic LCC*
ACCESS TIME (ns)
ORGANIZATION, 2M x 8
Flash
MONOLITHIC
WHITE ELECTRONIC DESIGNS CORP.
* Package to be developed.
Device Type
Sector Size
Speed
Package
SMD No.
2M x 8 Flash Monolithic
64KByte
150ns
56 lead CSOP (DA)
5962-97609 01HXX
2M x 8 Flash Monolithic
64KByte
120ns
56 lead CSOP (DA)
5962-97609 02HXX
2M x 8 Flash Monolithic
64KByte
90ns
56 lead CSOP (DA)
5962-97609 03HXX
May 2004
Rev. 6
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com