ETC WS256K32N

WS256K32-XXX
HI-RELIABILITY PRODUCT
256Kx32 SRAM MODULE
PRELIMINARY*
FEATURES
■ 2V Data Retention devices available
(WS256K32L-XXX low power version only)
■ Access Times 20, 25, 35ns
■ MIL-STD-883 Compliant Devices Available
■ Packaging
■ Commercial, Industrial and Military Temperature Range
• 66 pin, PGA Type, 1.185 inch square, Hermetic
Ceramic HIP (Package 401)
■ 5 Volt Power Supply
• 68 lead, 40mm, Hermetic CQFP (Package 501)
■ TTL Compatible Inputs and Outputs
■ Weight
WS256K32N-XHX - 13 grams typical
WS256K32-XG4X - 20 grams typical
■ Low Power CMOS
■ Organized as 256Kx32, User Configurable as 512Kx16
■ Upgradable to 512Kx32 for future expansion
■ Data I/O Compatible with 3.3V devices
FIG. 1
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
PIN CONFIGURATION FOR WS256K32N-XHX
PIN DESCRIPTION
TOP VIEW
1
12
23
NC
I/O8
34
I/O15
45
VCC
I/O24
56
I/O31
I/O9
NC
I/O14
I/O25
NC
I/O30
I/O10
GND
I/O13
I/O26
NC
I/O29
A13
I/O11
I/O12
A6
I/O27
I/O28
A10
A14
OE
A3
A7
A0
A15
A11
NC
NC
A4
A1
A16
A12
WE1
A8
A5
A2
A17
VCC
I/O7
A9
WE2
I/O23
I/O0
CS1
I/O6
I/O16
CS2
I/O22
I/O1
NC
I/O5
I/O17
GND
I/O21
I/O4
I/O18
I/O3
I/O2
11
October 2000 Rev. 2
22
33
WE1 CS 1
55
WE2 CS2
Data Inputs/Outputs
A0-17
Address Inputs
WE1-2
Write Enables
CS1-2
Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
NC
Not Connected
OE
A0-17
256K x 16
256K x 16
16
16
I/O20
I/O19
44
BLOCK DIAGRAM
I/O0-31
I/O0-15
I/O16-31
66
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS256K32-XXX
FIG. 2
PIN CONFIGURATION FOR WS256K32-XG4X
TOP VIEW
NC
A0
A1
A2
A3
A4
A5
CS1
GND
CS2
WE
A6
A7
A8
A9
A10
VCC
PIN DESCRIPTION
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
BLOCK DIAGRAM
WE
OE
A0-17
256K x 16
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
16
VCC
A11
A12
A13
A14
A15
A16
NC
OE
NC
A17
NC
NC
NC
NC
NC
NC
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CS 2
CS 1
I/O0-15
2
256K x 16
16
I/O16-31
I/O0-31
Data Inputs/Outputs
A0-17
Address Inputs
WE
Write Enable
CS1-2
Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
NC
Not Connected
WS256K32-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
TRUTH TABLE
Symbol
Min
Max
Unit
CS
OE
WE
Mode
Data I/O
Power
TA
-55
+125
°C
°C
H
L
L
L
X
L
H
X
X
H
H
L
Standby
Read
Out Disable
Write
High Z
Data Out
High Z
Data In
Standby
Active
Active
Active
Operating Temperature
TSTG
-65
+150
Signal Voltage Relative to GND
VG
-0.5
Vcc+0.5
V
Junction Temperature
TJ
150
°C
7.0
V
Storage Temperature
Supply Voltage
VCC
-0.5
CAPACITANCE
(T A = +25°C)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
Supply Voltage
VCC
4.5
5.5
V
OE capacitance
COE
VIN = 0 V, f = 1.0 MHz
Input High Voltage
VIH
2.2
V CC + 0.3
V
CWE
VIN = 0 V, f = 1.0 MHz
Input Low Voltage
VIL
-0.5
+0.8
V
Operating Temp (Mil)
TA
-55
+125
°C
WE1-2 capacitance
HIP (PGA)
CQFP G4
CS1-2 capacitance
Parameter
Symbol
Conditions
Max
Unit
28
pF
pF
CCS
VIN = 0 V, f = 1.0 MHz
20
28
20
Data I/O capacitance
CI/O
VI/O = 0 V, f = 1.0 MHz
20
pF
Address input capacitance
CAD
VIN = 0 V, f = 1.0 MHz
28
pF
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)
Parameter
Symbol
Conditions
Units
Min
Max
10
µA
Input Leakage Current
ILI
VCC = 5.5, VIN = GND to VCC
Output Leakage Current
ILO
CS = VIH, OE = VIH, VOUT = GND to VCC
10
µA
ICC x 32
CS = VIL, OE = VIH, f = 5MHz, Vcc = 5.5
550
mA
Standby Current
ISB
CS = VIH, OE = VIH, f = 5MHz, Vcc = 5.5
34
mA
Output Low Voltage
VOL
IOL = 8mA, Vcc = 4.5
0.4
Output High Voltage
VOH
IOH = -4.0mA, Vcc = 4.5
Operating Supply Current x 32 Mode
2.4
V
V
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
LOW POWER DATA RETENTION CHARACTERISTICS
(WS256K32L-XXX ONLY)
(T A = -55°C to +125°C)
Parameter
Symbol
Conditions
Units
Min
Data Retention Supply Voltage
Data Retention Current
V DR
CS ≥ V CC -0.2V
I CCDR3
V CC = 3V
Typ
2.0
1.0
3
Max
5.5
V
16
mA
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS256K32-XXX
AC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)
Parameter
Symbol
Read Cycle
-20
-25
Min
Read Cycle Time
t RC
Address Access Time
t AA
Output Hold from Address Change
t OH
Chip Select Access Time
t ACS
Max
20
Min
-35
Max
25
Units
Max
35
20
0
Min
ns
25
0
35
ns
35
ns
20
ns
0
20
ns
25
Output Enable to Output Valid
t OE
Chip Select to Output in Low Z
t CLZ 1
5
12
5
15
5
Output Enable to Output in Low Z
t OLZ 1
0
0
0
Chip Disable to Output in High Z
t CHZ 1
12
15
20
ns
Output Disable to Output in High Z
t OHZ 1
12
15
20
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)
Parameter
Symbol
Write Cycle
-20
-25
Min
Max
Min
-35
Max
Min
Units
Max
Write Cycle Time
t WC
20
25
35
ns
Chip Select to End of Write
t CW
17
20
25
ns
Address Valid to End of Write
t AW
17
20
25
ns
Data Valid to End of Write
t DW
12
15
20
ns
Write Pulse Width
t WP
17
20
25
ns
Address Setup Time
t AS
0
0
0
ns
Address Hold Time
t AH
2
2
2
ns
Output Active from End of Write
t OW 1
0
0
0
Write Enable to Output in High Z
t WHZ 1
Data Hold Time
t DH
8
0
10
0
ns
15
ns
0
ns
1. This parameter is guaranteed by design but not tested.
FIG. 3
AC TEST CONDITIONS
AC TEST CIRCUIT
I OL
Parameter
Current Source
VZ
D.U.T.
≈ 1.5V
(Bipolar Supply)
C eff = 50 pf
I OH
Current Source
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
NOTES:
V Z is programmable from -2V to +7V.
I OL & IOH programmable from 0 to 16mA.
Tester Impedance Z 0 = 75 Ω.
V Z is typically the midpoint of V OH and V OL.
I OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
WS256K32-XXX
FIG. 4
TIMING WAVEFORM - READ CYCLE
tRC
ADDRESS
tAA
CS
tRC
tCHZ
tACS
ADDRESS
tCLZ
tAA
OE
tOE
tOLZ
tOH
DATA I/O
PREVIOUS DATA VALID
DATA I/O
DATA VALID
tOHZ
DATA VALID
HIGH IMPEDANCE
READ CYCLE 1 (CS = OE = VIL, WE = VIH)
READ CYCLE 2 (WE = VIH)
FIG. 5
WRITE CYCLE - WE CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
CS
tAS
tWP
WE
tOW
tWHZ
tDW
DATA I/O
tDH
DATA VALID
WRITE CYCLE 1, WE CONTROLLED
FIG. 6
WRITE CYCLE - CS CONTROLLED
tWC
WS32K32-XHX
ADDRESS
tAS
tAW
tAH
tCW
CS
tWP
WE
tDW
DATA I/O
tDH
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS256K32-XXX
PACKAGE 401:
66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H)
30.1 (1.185) ± 0.38 (0.015) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
6.22 (0.245)
MAX
3.81 (0.150)
± 0.1 (0.005)
1.27 (0.050) ± 0.1 (0.005)
0.76 (0.030) ± 0.1 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
0.46 (0.018) ± 0.05 (0.002) DIA
25.4 (1.0) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 501:
68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G4)
39.6 (1.56) ± 0.38 (0.015) SQ
5.1 (0.200) MAX
1.27 (0.050)
± 0.1 (0.005)
PIN 1 IDENTIFIER
Pin 1
12.7 (0.500)
± 0.5 (0.020)
4 PLACES
5.1 (0.200)
± 0.25 (0.010)
4 PLACES
1.27 (0.050)
TYP
0.38 (0.015)
± 0.08 (0.003)
68 PLACES
0.25 (0.010)
± 0.05 (0.002)
38 (1.50) TYP
4 PLACES
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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6
WS256K32-XXX
ORDERING INFORMATION
W S 256K32 X - XXX X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
M = Military Screened
-55°C to +125°C
I = Industrial
-40°C to +85°C
C = Commercial
0°C to +70°C
PACKAGE:
H = Ceramic Hex-In-Line Package, HIP (Package 401)
G4 = 40mm Ceramic Quad Flat Pack, CQFP (Package 501)
ACCESS TIME (ns)
IMPROVEMENT MARK
N = No Connect at pins 21, 28 and 39 in HIP for Upgrades
Blank = Standard Power
L = Low Power Data Retention
ORGANIZATION, 256Kx32
User configurable as 512Kx16
SRAM
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7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com