NSC 54ACT564L

54ACT564
Octal D-Type Flip-Flop with TRI-STATE ® Outputs
General Description
Features
The ’ACT564 is a high-speed, low power octal flip-flop with a
buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs
is stored in the flip-flops on the LOW-to-HIGH Clock (CP)
transition.
n ICC and IOZ reduced by 50%
n Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
n Useful as input or output port for microprocessors
n Functionally identical to ’ACT574 but with inverted
outputs
n TRI-STATE outputs for bus-oriented applications
n Outputs source/sink 24 mA
n ’ACT564 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD) 5962-89557
The ’ACT564 is functionally identical to the ’ACT574, but
with inverted outputs.
Logic Symbols
IEEE/IEC
DS100994-1
DS100994-2
Pin Names
Description
D0–D7
Data Inputs
CP
Clock Pulse Input
OE
TRI-STATE Output Enable Input
O0–O7
TRI-STATE Outputs
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100994
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54ACT564 Octal D-Type Flip-Flop with TRI-STATE Outputs
September 1998
Connection Diagrams
Pin Assignment for DIP,
and Flatpak
Pin Assignment
for LCC
DS100994-4
DS100994-3
Functional Description
The’ACT564 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE complement outputs. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the complement of
the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the
state of the flip-flops.
Function Table
Inputs
Internal Outputs
CP
H
H
L
NC
Z
Hold
H
H
H
NC
Z
Hold
H
N
L
L
Z
Load
H
N
H
H
Z
Load
L
N
L
L
H
Data Available
L
N
H
H
L
Data Available
L
H
L
NC
NC
No Change in Data
L
H
H
NC
NC
No Change in Data
D
Q
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
NC = No Change
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2
Function
OE
ON
Absolute Maximum Ratings (Note 1)
CDIP
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC +0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC +0.5V
DC Output Voltage (VO)
DC Output Source or Sink Current
(IO)
DC VCC or Ground Current
Per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
175˚C
Recommended Operating
Conditions
−0.5V to +7.0V
Supply Voltage (VCC)
(Unless Otherwise Specified) (ACT)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
ACT
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
−20 mA
+20 mA
−0.5V to VCC +0.5V
−20 mA
+20 mA
−0.5V to VCC +0.5V
± 50 mA
4.5V to 5.5V
0V to VCC
0V to VCC
−55˚C to +125˚C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications.
± 50 mA
−65˚C to +150˚C
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
VCC
54ACT
TA =
(V)
−55˚C to +125˚C
Units
Conditions
Guaranteed Limits
VIH
VIL
VOH
Minimum High
Level Input
Voltage
Maximum Low
Level Input
Voltage
Minimum High
Level
4.5
2.0
5.5
2.0
4.5
0.8
5.5
0.8
4.5
4.4
5.5
5.4
V
VOUT = 0.1V
or VCC − 0.1V
V
VOUT = 0.1V
or VCC − 0.1V
V
IOUT = −50 µA
(Note 2)
VIN = VIL or VIH
VOL
Maximum Low
Level Output
Voltage
4.5
3.70
5.5
4.70
4.5
0.1
5.5
0.1
V
IOH
−24 mA
−24 mA
V
IOUT = 50 µA
(Note 2)
VIN = VIL or VIH
4.5
0.50
5.5
0.50
5.5
± 1.0
µA
VI = VCC, GND
Maximum
TRI-STATE
Leakage Current
5.5
± 10.0
µA
VI = VIL, VIH
ICCT
Maximum ICC/Input
5.5
1.6
mA
IOLD
5.5
50
mA
VI = VCC − 2.1V
VOLD = 1.65V
IOHD
(Note 3) Minimum
Dynamic Output
Current
5.5
−50
mA
VOHD = 3.85V
ICC
Maximum Quiescent
5.5
80.0
µA
VIN = VCC
IIN
Maximum Input
V
IOL
24 mA
24 mA
Leakage Current
IOZ
VO = VCC, GND
Supply Current
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
3
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DC Characteristics for ’ACT Family Devices
(Continued)
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for ’ACT Family Devices
54ACT
TA = −55˚C
VCC
Symbol
Parameter
(V)
to +125˚C
CL = 50 pF
(Note 4)
Min
Units
Max
fMAX
Maximum Clock
Frequency
5.0
65
tPLH
Propagation Delay
5.0
1.0
12.5
ns
5.0
1.0
11.5
ns
ns
CP to On
tPHL
Propagation Delay
CP to On
tPZH
Output Enable Time
5.0
1.0
10.5
ns
tPZL
Output Enable Time
5.0
1.0
10.5
ns
tPHZ
Output Disable Time
5.0
1.0
12.5
ns
tPLZ
Output Disable Time
5.0
1.0
9.5
ns
Note 4: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ’ACT Family Devices
VCC
Symbol
Parameter
(V)
(Note 5)
54ACT
TA = −55˚C
to +125˚C
CL = 50 pF
Units
Guaranteed Minimum
ts
Set-Up Time, HIGH or LOW
5.0
3.5
ns
5.0
2.5
ns
5.0
5.0
ns
Dn to CP
th
Hold Time, HIGH or LOW
Dn to CP
tw
CP Pulse Width
HIGH or LOW
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
CPD
Power Dissipation Capacitance
40.0
pF
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4
Conditions
VCC = OPEN
VCC = 5.0V
5
Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
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6
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
20 Lead Ceramic Flatpak (F)
NS Package Number W20A
7
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54ACT564 Octal D-Type Flip-Flop with TRI-STATE Outputs
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be reasonably expected to result in a significant injury
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