ANPEC APA2120RI-TY

APA2120/2121
Stereo 2-W Audio Power Amplifier (with DC_Volume Control)
General Description
Features
•
•
•
•
•
•
•
•
•
•
Low operating current with 14mA
APA2120/1 is a monolithic integrated circuit, which
Improved depop circuitry to eliminate turn-on
provides precise DC volume control, and a stereo
and turn off transients in outputs
bridged audio power amplifiers capable of producing
High PSRR
32 steps volume adjustable by DC voltage with
hysteresis
2W per channel output power into 4Ω load at 5V,
BTL mode
Two output modes allowable with BTL and SE
modes selected by SE/BTL pin
Low current consumption in shutdown mode
(50µA)
Short Circuit Protection
Power off depop circuit integration
2.7W(2.0W) into 3Ω with less than 10% (1.0%)
TSSOP-24 with or without thermal pad package
improves the power off pop noise and protects the
THD+N. The attenuator range of the volume control
in APA2120/1 is from 20dB (DC_Vol=0V) to -80dB
(DC_Vol=3.54V) with 32 steps. The advantage of
internal gain setting can be less components and PCB
area. Both of the depop circuitry and the thermal
shutdown protection circuitry are integrated in
APA2120/1, that reduce pops and clicks noise during power up or shutdown mode operation. It also
chip from being destroyed by over temperature and
short current failure. To simplify the audio system
Applications
design, APA2120/1 combines a stereo bridge-tied
loads (BTL) mode for speaker drive and a stereo
•
•
NoteBook PC
single-end (SE) mode for headphone drive into a
LCD Monitor or TV
single chip, where both modes are easily switched
by the SE/BTL input control pin signal. Besides, the
multiple input selection is used for portable audio
system.
Ordering and Marking Information
P ackage C ode
R : T S S O P -P *
Tem p. R ange
I : - 4 0 to 8 5 ° C
H a n d lin g C o d e
TU : Tube
T Y : T ra y
A P A 2 1 2 0 /1
H a n d lin g C o d e
Tem p. R ange
P ackage C ode
A P A 2 1 2 0 /1 R :
A P A 2 1 2 0 /1
XXXXX
TR : Tape & R eel
X X X X X - D a te C o d e
* TSSOP-P is a standard TSSOP package with a thermal pad exposure on the bottom of the package.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
1
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APA2120/2121
Block Diagram
LOUT+
LLINEIN
LHPIN
MUX
RHPIN
LOUT-
V o lu m e
C o n tro l
RLINEIN
LBYPASS
MUX
VOLUM E
BYPASS
BYPASS
ROUT+
HP/LINE
H P /L IN E
SE/BTL
ROUT-
S E /B T L
RBYPASS
SHUTDOW N
S h u td o w n
ckt
PCBEEP
CLK
P C -B E E P
ckt
C lo c k G e n
For APA2121
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.)
Symbol
Parameter
VDD
Supply Voltage Range
VIN
TA
TJ
TSTG
TS
Input Voltage Range, SE/BTL, HP/LINE,
SHUTDOWN, PCBEN
Operating Ambient Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Soldering Temperature,10 seconds
VESD
Electrostatic Discharge
PD
Power Dissipation
Rating
Unit
-0.3 to 6
V
-0.3 to VDD+0.3
V
-40 to 85
Intermal Limited*1
-65 to +150
260
-3000 to 3000*2
-200 to 200*3
Intermal Limited
°C
°C
°C
°C
V
Note:
1.APA2120/1 integrated internal thermal shutdown protection when junction temperature ramp up to 150°C
2.Human body model: C=100pF, R=1500Ω, 3 positives pulse plus 3 negative pulses
3.Machine model: C=200pF, L=0.5µF, 3 positive pulses plus 3 negative pulses
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
2
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APA2120/2121
Recommended Operating Conditions
Supply Voltage, VDD
High level threshold voltage, VIH
Low level threshold voltage, VIL
Min.
Max.
Unit
4.5
5.5
V
SHUTDOWN, PCBEN
2
SE/BTL , HP/LINE
SHUTDOWN, PCBEN
4
V
1.0
SE/BTL , HP/LINE
Common mode input voltage, VICM
V
3
VDD-1.0
V
Thermal Characteristics
Symbol
Parameter
R THJA
Thermal Resistance from Junction to Ambient in Free Air
TSSOP-P*
Value
Unit
45
K/W
* 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias.
The thermal pad on the TSSOP_P package with solder on the printed circuit board.
Electrical Characteristics
VDD=5V, -20°C<TA<85°C (unless otherwise noted)
Symbol
VDD
IDD
Parameter
Test Condition
Supply Voltage
Supply Current
APA2120/1
Min.
Typ.
4.5
Max.
5.5
SE/BTL=0V
14
25
SE/BTL=5V
8.0
15
Unit
V
mA
ISD
Supply Current in Shutdown SE/BTL=5V
Mode
SHUTDOWN=0V
50
µA
IIH
High input Current
900
nA
IIL
Low Input Current
900
nA
5
mV
VOS
Output Differential Voltage
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
3
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APA2120/2121
Electrical Characteristics (Cont.)
Operating Characteristics, BTL mode
VDD=5V,TA=25°C,RL=4Ω, Gain=2V/V (unless otherwise noted)
Symbol
PO
Parameter
Maximum Output Power
Test Condition
PSRR Power Ripple Rejection Ratio
Xtalk
S/N
Min. Typ. Max.
THD=10%, RL=3Ω, Fin=1kHz
2.7
THD=10%, RL=4Ω, Fin=1kHz
2.3
THD=10%, RL=8Ω, Fin=1kHz
1.5
THD=1%, RL=3Ω, Fin=1kHz
2.0
THD=1%, RL=4Ω, Fin=1kHz
1.9
THD=0.5%, RL=8Ω, Fin=1kHz
THD+N Total Harmonic Distortion Plus
Noise
APA2120/1
1
Unit
W
1.1
PO=1.5W, RL=4Ω, Fin=1kHz
0.05
PO=1W, RL=8Ω, Fin=1kHz
0.07
%
VIN=0.1Vrms, RL=8Ω, CB=1µF,
Fin=120Hz
60
dB
Channel Separation
CB=1µF, RL=8Ω, Fin=1kHz
90
dB
Signal to Noise Ratio
PO=1.1W, RL=8Ω, A_wieght
95
dB
Operating Characteristics, SE mode
VDD=5V,TA=25°C,RL=4Ω, Gain=1V/V (unless otherwise noted)
Symbol
PO
Parameter
Maximum Output Power
THD+N Total Harmonic Distortion Plus
Noise
Test Condition
APA2120/1
Min. Typ. Max.
THD=10%, RL=8Ω, Fin=1kHz
400
THD=10%, RL=32Ω, Fin=1kHz
110
THD=1%, RL=8Ω, Fin=1kHz
320
THD=1%, RL=32Ω, Fin=1kHz
90
PO=250mW, RL=8Ω, Fin=1kHz
0.08
PO=75mW, RL=32Ω, Fin=1kHz
0.08
Unit
mW
%
VIN=0.1Vrms, RL=8Ω, CB=1µF,
PSRR
Power Ripple Rejection Ratio
Xtalk
Channel Separation
S/N
Signal to Noise Ratio
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
48
dB
CB=1µF, RL=32Ω, Fin=1kHz
100
dB
PO=75mW, SE, RL=32Ω, A_wieght
100
dB
Fin=120Hz
4
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APA2120/2121
Pin Description
GND
1
24
GND
PCBEN
2
23
R LIN EIN
VO LU M E
3
22
SHUTDO W N
LO U T+
4
21
R O UT+
LLIN EIN
5
20
RHPIN
LH PIN
19
PVDD
6
7
RBYPASS
G ND
1
24
G ND
H P/LIN E
2
23
RLINEIN
VO LUM E
3
22
S HU TD O W N
LO U T+
4
21
R OU T+
LLIN EIN
5
20
RHPIN
VDD
LH PIN
19
VDD
18
PVDD
PVDD
6
7
18
PVDD
8
17
C LK
RBYPASS
8
17
C LK
LO U T-
9
16
R O UT-
LO U T-
9
16
R OU T-
LBYPASS
10
15
SE/BTL
LBYPASS
10
15
SE/BTL
BYPASS
11
14
PC-BEEP
BYPASS
11
14
PC-BEEP
GND
12
13
GND
G ND
12
13
G ND
APA2120
TO P View
APA2121
TO P View
Thermal
Pad
APA2120/1
Bottom View
APA2120
APA2121
Multiple Input Selection PCBEEP Control Input
SE/BTL
PCBEN
HP/LINE
-
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
5
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APA2120/2121
Pin Function Description
Pin
Name
Config.
PCBEN
No
1,12,
13,24
2
I/P
HP/LINE
2
I/P
VOLUME
LOUT+
LLINEIN
3
4
5
O/P
I/P
LHPIN
6
O/P
PVDD
RBYPASS
7,18
8
I/P
LOUT-
9
O/P
LBYPASS
BYPASS
10
11
I/P
PC_BEEP
14
I/P
SE/BTL
15
I/P
ROUT-
16
O/P
CLK
VDD
17
19
RHPIN
20
I/P
ROUT+
SHUTDOWN
21
22
O/P
I/P
RLINEIN
23
I/P
GND
Description
Ground connection, Connected to thermal pad.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
BEEP mode control input, active H, for APA2120 only
Multi-input selection input, headphone mode when held high, line-in
mode when held low for APA2121 only.
Input signal for internal volume gain setting.
Left channel positive output in BTL mode and SE mode.
Left channel line input terminal, selected when HP/LINE is held low.
Left channel headphone input terminal, selected when HP/LINE is
held high.
Supply voltage only for power amplifier.
Right channel bypass voltage.
Left channel negative output in BTL mode and high impedance in
SE mode.
Left channel bias voltage generator.
Bias voltage generator
PCBEP signal input
Output mode control input, high for SE output mode and low for
BTL mode.
Right channel negative output in BTL mode and high impedance in
SE mode.
Clock signal generator
Supply voltage for internal circuit excepting power amplifier.
Right channel headphone input terminal, selected when HP/LINE is
held high.
Right channel positive output in BTL mode and SE mode.
It will be into shutdown mode when pull low.
Right channel line input terminal, selected when HP/LINE is held
low.
6
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APA2120/2121
Control Input Table
For APA2120
SE/BTL
X
L
H
X
SHUTDOWN
L
H
H
X
PC-BEEP
Disable
Disable
Disable
Enable
Operating mode
Shutdown mode
Line input, BTL out
HP input, SE out
PCBEEP input, BTL out
For APA2121
SE/BTL
X
L
L
H
H
X
HP/LINE
X
L
H
L
H
X
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
SHUTDOWN
L
H
H
H
H
X
7
PC-BEEP
Disable
Disable
Disable
Disable
Disable
Enable
Operating mode
Shutdown mode
Line input, BTL out
HP input, BTL out
Line input, SE out
HP input, BTL out
PCBEEP input, BTL out
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APA2120/2121
Typical Application Circuit
APA2120
0Ω
VDD
0.1µF
VDD
1µF
LHPIN
PVDD
LOUT+
220µF
MUX
1kΩ
1µF
1µF
RHPIN
1µF
LOUT-
Volume
Control
RLINEIN
R-LINE
R-HP
GND
LLINEIN
L-LINE
L-HP
100µF
Control
Pin
LBYPASS
MUX
Ring
SE/BTL
2.2µF
VDD
BYPASS
Sleeve
Tip
BYPASS
Headphone Jack
VOLUME
50kΩ
4Ω
ROUT+
220µF
1kΩ
VDD
100kΩ
4Ω
SE/BTL
ROUT-
SE/BTL
RBYPASS
SHUTDOWN
Shutdown
Signal
BEEP
Signal
0.47µF
PCBEN
Signal
Shutdown
ckt
PCBEEP
PCBEN
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
CLK
Clock Gen
PC-BEEP
ckt
47nF
8
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APA2120/2121
Typical Application Circuit
APA2121
0Ω
VDD
0.1µF
VDD
1µF
GND
PVDD
LOUT+
LLINEIN
L-LINE
LHPIN
L-HP
100µF
220µF
MUX
1kΩ
1µF
4Ω
1µF
RLINEIN
R-LINE
R-HP
RHPIN
1µF
LBYPASS
MUX
Ring
SE/BTL
2.2µF
VDD
BYPASS
Sleeve
Tip
BYPASS
Headphone Jack
VOLUME
50kΩ
Control
Pin
LOUT-
Volume
Control
ROUT+
220µF
1kΩ
HP/LINE
HP/LINE
Signal
HP/LINE
VDD
100kΩ
4Ω
SE/BTL
ROUTSE/BTL
RBYPASS
Shutdown
Signal
BEEP
Signal
SHUTDOWN
PCBEEP
Shutdown
ckt
CLK
PC-BEEP
ckt
Clock Gen
0.47µF
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
47nF
9
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APA2120/2121
Volume Control Table_BTL Mode
Supply Voltage Vdd=5V
Gain(dB)
20
18
16
14
12
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
-32
-34
-36
-38
-40
-80
High(V)
0.12
0.23
0.34
0.46
0.57
0.69
0.80
0.91
1.03
1.14
1.25
1.37
1.48
1.59
1.71
1.82
1.93
2.05
2.16
2.28
2.39
2.50
2.62
2.73
2.84
2.96
3.07
3.18
3.30
3.41
3.52
5.00
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
Low(V)
0.00
0.17
0.28
0.39
0.51
0.62
0.73
0.84
0.96
1.07
1.18
1.29
1.41
1.52
1.63
1.74
1.85
1.97
2.08
2.19
2.30
2.42
2.53
2.64
2.75
2.87
2.98
3.09
3.20
3.32
3.43
3.54
Hysteresis(mV)
52
51
50
49
47
46
45
44
43
41
40
39
38
37
35
34
33
32
30
29
28
27
26
24
23
22
21
20
18
17
16
10
Recommended Voltage(V)
0
0.20
0.31
0.43
0.54
0.65
0.77
0.88
0.99
1.10
1.22
1.33
1.44
1.56
1.67
1.78
1.89
2.01
2.12
2.23
2.35
2.46
2.57
2.69
2.80
2.91
3.02
3.14
3.25
3.36
3.48
5
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APA2120/2121
Typical Characteristics
THD+N vs. Frequency
THD+N vs. Output Power
10
10
VDD=5V
RL=3Ω
AV=2
BTL
1
THD+N (%)
THD+N (%)
VDD=5V
RL=3Ω
Po=1.75W
BTL
AV=10 AV=2
0.1
f=20kHz
1
0.1
f=1kHz
AV=5
f=20Hz
0.01
20
100
1k
0.01
10m
20k
100m
THD+N vs. Output Power
THD+N vs. Frequency
10
10
VDD=5V
RL=4Ω
Po=1.5W
BTL
1
THD+N (%)
THD+N (%)
2 3
Output Power (W)
Frequency (Hz)
0.1
1
AV=2
VDD=5V
RL=4Ω
AV=2
BTL
1
f=20kHz
0.1
f=1kHz
AV=5
f=20Hz
AV=10
0.01
20
50 100 200
500 1k
2k
5k
0.01
100m
20k
Frequency (W)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
200m
500m 800m
2
3
Output Power (W)
11
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APA2120/2121
Typical Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Output Power
10
10
1
0.1
THD+N (%)
THD+N (%)
VDD=5V
RL=8Ω
Po=1.0W
BTL
AV=2
0.01
20
VDD=5V
RL=8Ω
AV=2
BTL
1
f=20kHz
0.1
AV=5
f=1kHz
AV=10
f=20Hz
10 0
1k
0.01
10m
20 k
100m
Frequency (Hz)
THD+N vs. Output Power
10
VDD=5V
RL=8Ω
Po=250mW
SE
VDD=5V
RL=8Ω
AV=2
BTL
1
1
THD+N (%)
THD+N (%)
2
Output Power (W)
THD+N vs. Frequency
10
1
AV=1 AV=5
0.1
f=20kHz
0 .1
f=20Hz
AV=2.5
0.01
20
100
1k
f=1kHz
0 .01
10m
20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
1 0 0m
5 0 0m
Output Power (W)
12
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APA2120/2121
Typical Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Output Power
10
VDD=5V
RL=16Ω
Po=100mW
SE
VDD=5V
RL=16Ω
AV=1
BTL
1
AV=1
AV=2
0.1
THD+N (%)
THD+N (%)
10
1
f=20kHz
f=20Hz
0.1
f=1kHz
AV=2.5
0.01
20
50 100 200
500 1k
2k
5k
0.01
10m
20k
100m
Frequency (Hz)
Output Power (W)
THD+N vs. Output Power
THD+N vs. Frequency
10
VDD=5V
RL=32Ω
Po=75mW
SE
5
1
0.1
AV=2.5
THD+N (%)
THD+N (%)
10
300m
AV=1
VDD=5V
RL=32Ω
AV=1
BTL
f=20kHz
1
0.1
f=20Hz
f=1kHz
AV=5
0.01
20
100
1k
0.01
10 m
20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
50 m
10 0m
20 0m
Output Power (W)
13
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APA2120/2121
Typical Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Output Swing
10
10
VDD=5V
RL=10Ω
AV=1
SE
1
0.1
AV=2.5
THD+N (%)
THD+N (%)
VDD=5V
RL=10Ω
Vo=1VRMS
SE
AV=1
1
0.1
f=20kHz
f=1kHz
f=20Hz
AV=5
0.01
20
10 0
1k
0.01
100m
20 k
500m
Frequency (Hz)
+0
VDD=5V
RL=32Ω
-2 0 Po=75mW
AV=1
SE
Crosstalk (dB)
VDD=5V
RL=8Ω
-20 Po=1.0W
AV=2
BTL
Crosstalk (dB)
3
Crosstalk vs. Frequency
+0
-40
-60
R-ch to L-ch
1 00
1k
-6 0
-8 0
R-ch to L-ch
-1 00
-1 20
20
2 0k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
-4 0
L-ch to R-ch
L-ch to R-ch
-10 0
-12 0
20
2
Output Swing (VRMS)
Crosstalk vs. Frequency
-80
1
100
1k
20k
Frequency (Hz)
14
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APA2120/2121
Typical Characteristics (Cont.)
Noise Floor vs. Frequency
Noise Floor vs. Frequency
10 0u
100u
VDD=5V
RL=32Ω
50 u AV=1
SE
No Filter
Noise Floor (µVRMS)
Noise Floor (µVRMS)
50u
20u
A-Weight
10u
5u
VDD=5V
RL=8Ω
AV=2
BTL
2u
1u
20
100
1k
20 u
No Filter
10 u
A-Weight
5u
2u
1u
20
20k
10 0
Noise Floor vs. Frequency
Power Dissipation vs. Output Power
0 .2
VDD=5V
RL=10KΩ
5 0 u AV=1
SE
0 .1 8
Power Dissipation (W)
Noise Floor (µVRMS)
1 0 0u
No Filter
10u
A-Weight
5u
2u
0 .1 6
0 .1 4
RL=8Ω
0 .1 2
0 .1
RL=16Ω
0 .0 8
0 .0 6
RL=32Ω
0 .0 4
VDD=5V
AV=1
SE
0 .0 2
1u
20
20 k
Frequency (Hz)
Frequency (Hz)
20u
1k
0
100
1k
20k
0
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
0 .0 5 0 .1 0 .1 5 0 .2 0 .2 5 0 .3 0 .3 5 0 .4
Output Power (W)
15
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APA2120/2121
Typical Characteristics (Cont.)
Power Dissipation vs. Output Power
Supply Current vs. Supply Voltage
20
1 .8
1 7 .5
RL=3Ω
1 .4
Suuply Current (mA)
Power Dissipation (W)
1 .6
1 .2
RL=4Ω
1
0 .8
0 .6
RL=8Ω
0 .4
VDD=5V
AV=2
BTL
0 .2
15
BTL
1 2 .5
10
SE
7 .5
5
2 .5
No Load
0
0
1 .8
Output Power (W)
1 .6
1
1 .5
2
1
2 .5
1 .5
2
2 .5
3
3 .5
4
4 .5
5 5 .5
Output Power (W)
Supply Voltage (V)
Output Power vs. Supply Voltage
Output Power vs. Supply Voltage
160
RL=8Ω
AV=2
BTL
140
Output Power (mW)
2 .0
0 .5
1 .4
THD+N=10%
1 .2
1 .0
0 .8
THD+N=1%
0 .6
RL=32Ω
AV=1
SE
120
100
THD+N=10%
80
60
THD+N=1%
40
0 .4
20
0 .2
0
0
2 .5
3
3 .5
4
4 .5
5
2.5
5 .5
Supply Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
16
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APA2120/2121
Typical Characteristics (Cont.)
Output Power vs. Load Resistance
3
0.7
VDD=5V
AV=2
BTL
2
1.5
1
THD+N=10%
0.5
VDD=5V
AV=1
SE
0.6
Output Power (W)
2.5
Output Power (W)
Output Power vs. Load Resistance
0.5
0.4
0.3
0.2
THD+N=10%
0.1
THD+N=1%
0
THD+N=1%
0
4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
4 8 12 16 20 24 28 32 36 40 44 48 52 56 6064
Load Resistance (Ω)
Load Resistance (Ω)
Close Loop Response
Close Loop Response
+12
+6
+4
Loop Gain (dB)
Loop Gain (dB)
VDD=5V
RL=8Ω
+10 AV=2
BTL
CO=330µF
+8
+6
AV=2
AV=5
AV=10
+4
+2
-0
20
VDD=5V
RL=32Ω
AV=1
SE
CO=330µF
+2
+0
AV=1
AV=2.5
AV=5
-2
-4
100
1k
-6
20
20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
100
1k
20k
Frequency (Hz)
17
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APA2120/2121
Typical Characteristics (Cont.)
PSRR vs. Frequency
Ripple Rejection Ratio (dB)
+0
-2 0
66
VDD=5V
Vin=100mVRMS
RL=8Ω
Cbypass=2.2µF
BTL
-4 0
SE
-6 0
-8 0
20
100
1k
20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
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APA2120/2121
Application Descriptions
BTL Operation
BTL Operation (Cont.)
The APA2120/1 output stage (power amplifier) has
Four times the output power same conditions. A BTL
two pairs of operational amplifiers internally, allowed
configuration, such as the one used in APA2120/1,
for different amplifier configurations.
also creates a second advantage over SE amplifiers.
Since the differential outputs, ROUT+, ROUT-,
OUT+
LOUT+, and LOUT-, are biased at half-supply, no
Volume Control
am plifier output
signal
OP1
need DC voltage exists across the load. This eliminates the need for an output coupling capacitor which
RL
is required in a single supply, SE configuration.
OUT-
Vbias
Circuit
OP2
Single-Ended Operation
Figure 1: APA2120/1 internal configuration
Consider the single-supply SE configuration shown
(each channel)
The power amplifier’s OP1 gain is setting by internal
Application Circuit. A coupling capacitor is required
to block the DC offset voltage from reaching the load.
unity-gain and input audio signal is come from inter-
These capacitors can be quite large (approximately
nal volume control amplifier, while the second ampli-
33µF to 1000µF) so they tend to be expensive, oc-
fier OP2 is internally fixed in a unity-gain, inverting
cupy valuable PCB area, and have the additional
configuration. Figure 1 shows that the output of OP1
drawback of limiting low-frequency performance of
is connected to the input to OP2, which results in the
the system (refer to the Output Coupling Capacitor).
output signals of with both amplifiers with identical in
The rules described still hold with the addition of the
magnitude, but out of phase 180°. Consequently,
following relationship:
the differential gain for each channel is 2 x (Gain of
1
≤ 1 << 1
Cbypass x 125kΩ
RiCi
RLCC
SE mode).
(1)
By driving the load differentially through outputs OUT+
Output SE/BTL Operation
and OUT-, an amplifier configuration commonly referred to as bridged mode is established. BTL mode
The ability of the APA2120/1 to easily switch between
operation is different from the classical single-ended
BTL and SE modes is one of its most important costs
SE amplifier configuration where one side of its load
saving features. This feature eliminates the require-
is connected to ground.
ment for an additional headphone amplifier in appli-
A BTL amplifier design has a few distinct advantages
cations where internal stereo speakers are driven in
over the SE configuration, as it provides differential
BTL mode but external headphone or speakers must
drive to the load, thus doubling the output swing for a
be accommodated.
specified supply voltage.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
19
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APA2120/2121
Application Descriptions (Cont.)
Output SE/BTL Operation (Cont.)
Output SE/BTL Operation (Cont.)
Internal to the APA2120/1, two separate amplifiers
Resistor 1kΩ then pulls low the SE/BTL pin, enabling
drive OUT+ and OUT- (see Figure 1). The SE/BTL
the BTL function.
input controls the operation of the follower amplifier
Volume Control Function
that drives LOUT- and ROUT-.
• When SE/BTL is held low, the OP2 is turn on and
APA2120/1 has an internal stereo volume control
the APA2120/1 is in the BTL mode.
whose setting is a function of the DC voltage applied
•When SE/BTL is held high, the OP2 is in a high
to the VOLUME input pin. The APA2120/1 volume
output impedance state, which configures the
control consists of 32 steps that are individually se-
APA2120/1 as SE driver from OUT+. IDD is reduced
lected by a variable DC voltage level on the VOL-
by approximately one-half in SE mode.
UME control pin. The range of the steps, controlled
Control of the SE/BTL input can be a logic-level TTL
by the DC voltage, are from 20dB to -80dB. Each
source or a resistor divider network or the stereo
gain step corresponds to a specific input voltage
headphone jack with switch pin as shown in Applica-
range, as shown in table. To minimize the effect of
tion Circuit.
noise on the volume control pin, which can affect the
selected gain level, hysteresis and clock delay are
1k Ω
implemented. The amount of hysteresis corresponds
VDD
100k Ω
Control
Pin
to half of the step width, as shown in volume control
Ring
graph.
SE/BTL
Tip
Gain_BT L m ode
Sleeve
APA2021 volum e control curve
Forward
Backward
20
Headphone Jack
16
Figure 2: SE/BTL input selection by phonejack plug
12
8
In Figure 2, input SE/BTL operates as follows :
4
When the phonejack plug is inserted, the 1kΩ resis-
0
-4
tor is disconnected and the SE/BTL input is pulled
-8
high and enables the SE mode. When the input goes
-12
-16
high, the OUT- amplifier is shutdown causing the
-20
-24
speaker to mute. The OUT+ amplifier then drives
-28
through the output capacitor (CC) into the headphone
-32
-36
jack. When there is no headphone plugged into the
-40
system, the contact pin of the headphone jack is con-
-44
0
nected from the signal pin, the voltage divider set up
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
(V)
Figure 3: Gain setting vs VOLUME pin voltage
by resistors 100kΩ and 1kΩ.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
20
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APA2120/2121
Application Descriptions (Cont.)
Volume Control Function (Cont.)
Ri vs Gain(BTL)
Ri(kΩ)
120
For highest accuracy, the voltage shown in the ‘rec-
100
ommended voltage’ column of the table is used to
80
select a desired gain. This recommended voltage is
exactly halfway between the two nearest transitions.
60
The gain levels are 2dB/step from 20dB to -40dB in
40
BTL mode, and the last step at -80dB as mute mode.
20
0
Input Resistance, Ri
-40
The gain for each audio input of the APA2120/1 is
-30
-20
-10
0
10
20
Gain(dB)
Figure 4: Input resistance vs Gain setting
set by the internal resistors (Ri and Rf) of volume
Input Capacitor, Ci
control amplifier in inverting configuration.
RF
(2)
Ri
RF
(3)
BTL Gain = -2 x
Ri
BTL mode operation brings the factor of 2 in the gain
In the typical application an input capacitor, Ci, is re-
SE Gain = AV = -
quired to allow the amplifier to bias the input signal to
the proper DC level for optimum operation. In this
case, Ci and the minimum input impedance Ri (10kΩ)
equation due to the inverting amplifier mirroring the
form a high-pass filter with the corner frequency de-
voltage swing across the load. For the varying gain
termined in the follow equation :
setting, APA2120/1 generates each input resistance
FC(highpass)=
on figure 4. The input resistance will affect the low
1
2πx10kΩxCi
(4)
frequency performance of audio signal. The minmum
The value of Ci is important to consider as it directly
input resistance is 10kΩ when gain setting is 20dB
affects the low frequency performance of the circuit.
and the resistance will ramp up when close loop gain
Consider the example where Ri is 10kΩ and the speci-
below 20dB. The input resistance has wide variation
fication calls for a flat bass response down to 100Hz.
(+/-10%) caused by process variation.
Equation is reconfigured as follow :
Ci=
1
2πx10kΩxfC
(5)
Consider to input resistance variation, the Ci is 0.16µF
so one would likely choose a value in the range
of 0.22µF to 1.0µF.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
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APA2120/2121
Application Descriptions (Cont.)
Input Capacitor, Ci (Cont.)
Effective Bypass Capacitor, Cbypass (Cont.)
A further consideration for this capacitor is the leak-
The effective capacitance is the Cbypass=(Cb//
age path from the input source through the input net-
CLbyasss//CRbypass). When absolute minimum
work (Ri+Rf, Ci) to the load. This leakage current
cost and/or component space is required, one by-
creates a DC offset voltage at the input to the ampli-
pass capacitor can be used.
fier that reduces useful headroom, especially in high
To avoid start-up pop noise occurred, the bypass
gain applications. For this reason a low-leakage tan-
voltage should rise slower than the input bias voltage
talum or ceramic capacitor is the best choice. When
and the relationship shown in equation (6) should be
polarized capacitors are used, the positive side of
maintained.
1
1
<<
Cbypass x 125kΩ
100kΩ x Ci
the capacitor should face the amplifier input in most
applications as the DC level there is held at VDD/2,
(6)
The bypass capacitor is fed thru from a 125kΩ resis-
which is likely higher that the source DC level.
tor inside the amplifier and the 100kΩ is maximum
sPlease note that it is important to confirm the ca-
input resistance of (Ri+ Rf). Bypass capacitor, Cb,
pacitor polarity in the application.
values of 3.3µF to 10µF ceramic or tantalum low-ESR
Effective Bypass Capacitor, Cbypass
capacitors are recommended for the best THD and
As other power amplifiers, proper supply bypassing
noise performance.
is critical for low noise performance and high power
The bypass capacitance also effects to the start up
supply rejection.
time. It is determined in the following equation :
The capacitors located on both the bypass and power
Tstart up = 5 x (Cbypass x 125KΩ)
supply pins should be as close to the device as
(7)
Output Coupling Capacitor, Cc
possible. The effect of a larger bypass capacitor will
improve PSRR due to increased supply stability. Typi-
In the typical single-supply SE configuration, an out-
cal applications employ a 5V regulator with 1.0µF and
put coupling capacitor (Cc) is required to block the
a 0.1µF bypass capacitor as supply filtering. This
DC bias at the output of the amplifier thus preventing
does not eliminate the need for bypassing the supply
DC currents in the load. As with the input coupling
nodes of the APA2120/1. The selection of bypass
capacitor, the output coupling capacitor and imped-
capacitors, especially Cbypass, is thus dependent
ance of the load form a high-pass filter governed by
upon desired PSRR requirements, click and pop
equation.
FC(highpass)=
performance.
1
2πRLCC
(8)
On the chip, there are three bypass pins for used,
and they are tied together in the internal circuit.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
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APA2120/2121
Application Descriptions (Cont.)
Output Coupling Capacitor, Cc (Cont.)
Optimizing Depop Circuitry
For example, a 330µF capacitor with an 8Ω speaker
Circuitry has been included in the APA2120/1 to mini-
would attenuate low frequencies below 60.6Hz. The
mize the amount of popping noise at power-up and
main disadvantage, from a performance standpoint,
when coming out of shutdown mode. Popping oc-
is the load impedance is typically small, which drives
curs whenever a voltage step is applied to the
the low-frequency corner higher degrading the bass
speaker. In order to eliminate clicks and pops, all
response. Large values of CC are required to pass
capacitors must be fully discharged before turn-on.
low frequencies into the load.
Rapid on/off switching of the device or the shutdown
function will cause the click and pop circuitry.
Power Supply Decoupling, Cs
The value of Ci will also affect turn-on pops. (Refer
to Effective Bypass Capacitance) The bypass volt-
The APA2120/1 provides PVDD and VDD two indepen-
age ramp up should be slower than input bias voltage.
dent power inputs for used. PVDD is used for power
Although the bypass pin current source cannot be
amplifier only and VDD is used for volume control
modified, the size of Cbypass can be changed to al-
amplifier and internal circuit excepting power amplifier.
ter the device turn-on time and the amount of clicks
The APA2120/1 is a high-performance CMOS audio
and pops. By increasing the value of Cbypass, turn-
amplifier that requires adequate power supply
on pop can be reduced. However, the tradeoff for
decoupling to ensure the output total harmonic dis-
using a larger bypass capacitor is to increase the turn-
tortion (THD) is as low as possible. Power supply
on time for this device. There is a linear relationship
decoupling also prevents the oscillations causing by
between the size of Cbypass and the turn-on time.
long lead length between the amplifier and the
In a SE configuration, the output coupling capacitor,
speaker. The optimum decoupling is achieved by
CC, is of particular concern.
using two different type capacitors that target on dif-
This capacitor discharges through the internal 10kΩ
ferent type of noise on the power supply leads.
resistors. Depending on the size of CC, the time con-
For higher frequency transients, spikes, or digital hash
stant can be relatively large. To reduce transients in
on the line, a good low equivalent-series-resistance
SE mode, an external 1kΩ resistor can be placed in
(ESR) ceramic capacitor, typically 0.1µF placed as
parallel with the internal 10kΩ resistor. The tradeoff
close as possible to the device VDD and PVDD lead
for using this resistor is an increase in quiescent
works best. For filtering lower-frequency noise
current. In the most cases, choosing a small value
signals, a large aluminum electrolytic capacitor of
of Ci in the range of 0.33µF to 1µF, Cb being equal to
10µF or greater placed near the audio power ampli-
4.7µF and an external 1kΩ resistor should be placed
fier is recommended.
in parallel with the internal 10kΩ resistor should produce a virtually clickless and popless turn-on.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
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APA2120/2121
Application Descriptions (Cont.)
Optimizing Depop Circuitry (Cont.)
Input HP/LINE Operation (Cont.)
A high gain amplifier intensifies the problem as the
This logic-low voltage at the SE/BTL pin makes
small delta in voltage is multiplied by the gain. So it
APA2120 into LINE input mode operation. It becomes
is advantageous to use low-gain configurations.
HP input mode when phonejack plugged.
An internal multiplexor selects the input to connect to
Shutdown Function
the amplifier based on the state of the HP/LINE pin
In order to reduce power consumption while not in
of the APA2121.
use, the APA2120/1 contains a shutdown pin to ex-
• To select the LINE inputs, set HP/LINE pin to low
ternally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low
level.
• To enable the HP(headphone) inputs, set HP/LINE
is placed on the SHUTDOWN pin. The trigger point
pin to high level.
between a logic high and logic low level is typically
As APA2121, HP/LINE input multiplexor, and SE/BTL
2.0V. It is best to switch between ground and the sup-
output operating mode have independent control
ply VDD to provide maximum device performance.
paths, which can be used for multiple audio input
By switching the SHUTDOWN pin to low, the ampli-
system. This function will be the same as APA2120
when HP/LINE and SE/BTL are tied together.
fier enters a low-current state, IDD<50µA. APA2120/1
is in shutdown mode, except PC-BEEP detect circuit.
PC-BEEP Detection
On normal operating, SHUTDOWN pin pull to high
APA2120/1 integrates a BEEP detect circuit for
level to keeping the IC out of the shutdown mode.
NOTEBOOK PC. When BEEP signal is provided on
The SHUTDOWN pin should be tied to a definite volt-
PCBEEP input pin, the BEEP mode is active.
age to avoid unwanted state changes.
APA2120/1 will force to BTL mode and the internal
gain is fixed at -10dB. The PCBEEP signal becomes
Input HP/LINE Operation
the amplifier input signal and plays on the speaker
APA2120/1 amplifier has two separate inputs for each
without coupling capacitor. It will be out of shutdown
of the left and right stereo channels. The APA2120
mode whenever BEEP mode is enabled. APA2120/
and APA2121 have different control input by SE/BTL
1 will return to previous setting when it is out of BEEP
mode. The input impedance is 100kΩ on PCBEEP
and HP/LINE, respectively.
APA2120 internal multiplexor is selected by SE/BTL
input pin.
control input. Refer to the ‘Output SE/BTL Operation’,
APA2120 provides extra PCBEN control input signal
to force IC into BEEP mode. The BEEP mode will be
the voltage divider of 100kΩ and 1kΩ sets the volt-
enabled when PCBEN goes to high level. When
age at the SE/BTL pin to be approximately 50mV
BEEP mode is overridden, the signal from PCBEEP
when no phonejack plugged into the system.
will pass to speaker directly.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
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APA2120/2121
Application Descriptions (Cont.)
Clock Generator
BTL Amplifier Efficiency (Cont.)
APA2120/1 integrates a clock block to avoid volume
Note that the efficiency of the amplifier is quite low
control function abnormal when VOLUME control sig-
for lower power levels and rises sharply as power to
nal with spike or noise. APA2120/1 changes each
the load is increased resulting in a nearly flat internal
step of volume gain after four clock cycles to make
power dissipation over the normal operating range.
sure control signal ready. It provides 130kHz fre-
Note that the internal dissipation at full output power
quency if no capacitor place on CLK pin to ground.
is less than in the half power range. Calculating the
The larger capacitance will slow down the and clock
efficiency for a specific system is the key to proper
frequency. A capacitor 33nF between CLK to ground
power supply design. For a stereo 1W audio system
and will generates 147Hz frequency on CLK pin.
with 8Ω loads and a 5V supply, the maximum draw
on the power supply is almost 3W.
BTL Amplifier Efficiency
A final point to remember about linear amplifiers
An easy-to-use equation to calculate efficiency starts
(either SE or BTL) is how to manipulate the terms in
out as being equal to the ratio of power from the power
the efficiency equation to utmost advantage when
supply to the power delivered to the load.
possible. Note that in equation, V DD is in the
The following equations are the basis for calculating
denominator. This indicates that as VDD goes down,
amplifier efficiency.
efficiency goes up. In other words, use the efficiency
Efficiency =
PO
PSUP
analysis to choose the correct supply voltage and
(9)
speaker impedance for the application.
Where :
PO = VORMS x VORMS = VPxVP
2RL
RL
VORMS =
VP
√2
PSUP = VDD x IDDRMS = VDD x 2VP
πRL
Po (W) Efficiency (%) IDD(A) VPP(V) PD (W)
(10)
0.25
31.25
0.16
2.00
0.55
0.50
47.62
0.21
2.83
0.55
1.00
66.67
0.30
4.00
0.5
1.25
78.13
0.32
4.47
0.35
(11)
Efficiency of a BTL configuration :
PO
VPxVP ) / (VDD x 2VP ) = πVP
=(
2VDD
PSUP
2RL
πRL
(12)
**High peak voltages cause the THD to increase.
Table 1. Efficiency Vs Output Power in 5-V/8Ω BTL
Table 1 calculates efficiencies for four different out-
Systems
put power levels.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
25
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APA2120/2121
Application Descriptions (Cont.)
Power Dissipation
Power Dissipation (Cont.)
Whether the power amplifier is operated in BTL or
Once the power dissipation is greater than the maxi-
SE modes, power dissipation is a major concern. In
mum limit (PD,MAX), either the supply voltage (VDD) must
equation13 states the maximum power dissipation
be decreased, the load impedance (RL) must be in-
point for a SE mode operating at a given supply volt-
creased or the ambient temperature should be
age and driving a specified load.
reduced.
SE mode : PD,MAX=
VDD2
2π2RL
(13)
Thermal Pad Considerations
In BTL mode operation, the output voltage swing is
The thermal pad must be connected to ground. The
doubled as in SE mode. Thus the maximum power
package with thermal pad of the APA2120/1 requires
dissipation point for a BTL mode operating at the
special attention on thermal design. If the thermal
same given conditions is 4 times as in SE mode.
design issues are not properly addressed, the
BTL mode : PD,MAX=
4VDD2
2π2RL
APA2120/1 4Ω will go into thermal shutdown when
(14)
driving a 4Ω load.
The thermal pad on the bottom of the APA2120/1
Since the APA2120/1 is a dual channel power
should be soldered down to a copper pad on the cir-
amplifier, the maximum internal power dissipation is
cuit board. Heat can be conducted away from the
2 times that both of equations depending on the mode
thermal pad through the copper plane to ambient. If
of operation. Even with this substantial increase in
the copper plane is not on the top surface of the cir-
power dissipation, the APA2120/1 does not require
extra heatsink.
cuit board, 8 to 10 vias of 13 mil or smaller in diam-
The power dissipation from
eter should be used to thermally couple the thermal
equation14, assuming a 5V-power supply and an 8Ω
pad to the bottom plane.
load, must not be greater than the power dissipation
For good thermal conduction, the vias must be plated
that results from the equation15 :
through and solder filled. The copper plane used to
TJ,MAX - TA
PD,MAX=
θJA
(15)
conduct heat away from the thermal pad should be
as large as practical.
For TSSOP-24 package with thermal pad, the ther-
If the ambient temperature is higher than 25°C, a
ο
mal resistance (θJA) is equal to 45 C/W.
larger copper plane or forced-air cooling will be re-
Since the maximum junction temperature (TJ,MAX) of
quired to keep the APA2120/1 junction temperature
APA2120/1 is 150οC and the ambient temperature
below the thermal shutdown temperature (150°C). In
(TA) is defined by the power system design, the maxi-
higher ambient temperature, higher airflow rate and/
mum power dissipation which the IC package is able
or larger copper area will be required to keep the IC
to handle can be obtained from equation16.
out of thermal shutdown.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
26
www.anpec.com.tw
APA2120/2121
Packaging Information
T S S O P / T S S O P -P ( R eference JE D E C R egistration M O -153)
e
N
2x E/2
E1
1
2
3
E
e/2
D
A2
A
(
2)
GAUGE
PLANE
A1
b
D1
S
EXPOSED THERMAL
PAD ZONE
E2
0.25
L
1
(L1)
( 3)
BOTTOM VIEW
(THERMALLY ENHANCED VARIATIONDS ONLY)
D im
A
A1
A2
D
D1
e
E
E1
E2
L
L1
R
R1
S
φ1
φ2
φ3
M illim eters
Inches
M in.
M ax.
1.2
0.00
0.15
0.80
1.05
6.4 (N =20P IN )
6.6 (N =20P IN )
7.7 (N =24P IN )
7.9 (N =24P IN )
9.6 (N =28P IN )
9.8 (N =28P IN )
4.2 B S C (N =20P IN )
4.7 B S C (N =24P IN )
3.8 B S C (N =28P IN )
0.65 B S C
6.40 B S C
4.30
4.50
3.0 B S C (N =20P IN )
3.2 B S C (N =24P IN )
2.8 B S C (N =28P IN )
0.45
0.75
1.0 R E F
0.09
0.09
0.2
0°
8°
12° R E F
12° R E F
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
27
M in.
M ax.
0.047
0.000
0.006
0.031
0.041
0.252 (N =20P IN ) 0.260 (N =20P IN )
0.303 (N =24P IN ) 0.311 (N =24P IN )
0.378 (N =28P IN ) 0.386 (N =28P IN )
0.165 B S C (N =20P IN )
0.188 B S C (N =24P IN )
0.150 B S C (N =28P IN )
0.026 B S C
0.252 B S C
0.169
0.177
0.118 B S C (N =20P IN )
0.127 B S C (N =24P IN )
0.110 B S C (N =28P IN )
0.018
0.030
0.039R E F
0.004
0.00 4
0.008
0°
8°
12° R E F
12° R E F
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APA2120/2121
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb)
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
temperature
Reference JEDEC Standard J-STD-020A APRIL 1999
Peak temperature
183°C
Pre-heat temperature
Time
Classification Reflow Profiles
Convection or IR/
Convection
Average ramp-up rate(183°C to Peak)
3°C/second max.
120 seconds max
Preheat temperature 125 ± 25°C)
60 – 150 seconds
Temperature maintained above 183°C
Time within 5°C of actual peak temperature 10 –20 seconds
Peak temperature range
220 +5/-0°C or 235 +5/-0°C
Ramp-down rate
6 °C /second max.
6 minutes max.
Time 25°C to peak temperature
VPR
10 °C /second max.
60 seconds
215-219°C or 235 +5/-0°C
10 °C /second max.
Package Reflow Conditions
pkg. thickness ≥ 2.5mm
and all bgas
Convection 220 +5/-0 °C
VPR 215-219 °C
IR/Convection 220 +5/-0 °C
pkg. thickness < 2.5mm and
pkg. volume ≥ 350 mm³
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
28
pkg. thickness < 2.5mm and pkg.
volume < 350mm³
Convection 235 +5/-0 °C
VPR 235 +5/-0 °C
IR/Convection 235 +5/-0 °C
www.anpec.com.tw
APA2120/2121
Reliability test program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C , 5 SEC
1000 Hrs Bias @ 125 °C
168 Hrs, 100 % RH , 121°C
-65°C ~ 150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms , Itr > 100mA
Carrier Tape & Reel Dimensions
D
P
Po
t
E
P1
Bo
F
W
Ko
Ao
D1
T2
J
C
A
B
T1
Application
TSSOP- 24
A
B
C
J
T1
T2
W
P
E
330 ±1
100 ref
13 ±0.5
2 ±0.5
16.4 ±0.2
2 ±0.2
16 ±0.3
12 ±0.1
1.75±0.1
F
D
D1
Po
P1
Ao
Bo
Ko
t
7.5 ±0.1
1.5 +0.1
1.5 min
4.0 ±0.1
2.0 ±0.1
6.9 ±0.1
8.3 ±0.1
1.5 ±0.1
0.3±0.05
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
29
www.anpec.com.tw
APA2120/2121
Cover Tape Dimensions
Application
TSSOP- 24
Carrier Width
16
Cover Tape Width
21.3
Devices Per Reel
2000
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2003
30
www.anpec.com.tw