LH532000B CMOS 2M (256K × 8/128K × 16) MROM FEATURES PIN CONNECTIONS • 262,144 words × 8 bit organization (Byte mode) 131,072 words × 16 bit organization (Word mode) • BYTE input pin selects bit configuration • Access times: 120/150 ns (MAX.) • Low-power consumption: Operating: 275 mW (MAX.) Standby: 550 µW (MAX.) • Programmable OE/OE and OE1/OE1/DC • Static operation • TTL compatible I/O 40-PIN DIP 40-PIN SOP TOP VIEW OE1/OE1/DC 1 40 A8 A7 2 39 A9 A6 3 48 A10 A5 4 37 A11 A4 5 36 A12 A3 6 35 A13 A2 7 34 A14 A1 8 33 A15 A0 9 32 A16 CE 10 31 BYTE 11 30 GND OE/OE 12 29 D15/A-1 (LSB) D0 13 28 D7 GND • Three-state outputs D8 14 27 D14 D1 15 26 D6 • Single +5 V power supply D9 16 25 D13 D2 17 24 D5 D10 18 23 D12 D3 19 22 D4 D11 20 21 VCC • Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 48-pin, 12 × 18 mm2 TSOP (Type I) • ×16 word-wide pinout DESCRIPTION 532000B-1 Figure 1. Pin Connections for DIP and SOP Packages The LH532000B is a 2M-bit mask-programmable ROM with two programmable memory organizations, byte and word modes. It is fabricated using silicon-gate CMOS process technology. 1 LH532000B CMOS 2M MROM 48-PIN TSOP (Type I) TOP VIEW BYTE 1 48 GND A16 2 47 GND A15 3 46 D15/A-1 A14 4 45 D7 A13 5 44 D14 A12 6 43 D6 A11 7 42 D13 A10 8 41 D5 A9 9 40 D12 A8 10 39 D4 VCC NC 11 38 GND 12 37 VCC NC 13 36 GND D11 NC 14 35 OE1/OE1/DC 15 34 D3 A7 16 33 D10 A6 17 32 D2 D9 A5 18 31 A4 19 30 D1 A3 20 29 D8 A2 21 28 D0 A1 22 27 OE/OE A0 23 26 GND CE 24 25 GND NOTE: Reverse bend available on request. 532000B-5 Figure 2. Pin Connections for TSOP Package 2 CMOS 2M MROM 38 39 40 2 3 A5 4 A4 A3 A2 A1 DATA SELECTOR/OUTPUT BUFFER A6 35 36 37 MEMORY MATRIX (262,144 x 8) (131,072 x 16) ADDRESS DECODER A7 32 33 34 ADDRESS BUFFER A16 A15 A14 A13 A12 A11 A10 A9 A8 LH532000B 5 6 7 29 D15 27 D14 25 D13 23 D12 20 D11 18 D10 16 D9 14 D8 28 D7 26 D6 24 D5 22 D4 8 19 D3 17 D2 15 D1 A0 9 13 D0 COLUMN SELECTOR CE 10 CE BUFFER OE1/OE1/DC 1 OE/OE 12 OE BUFFER BYTE 31 BYTE/WORD SWITCHOVER CIRCUIT TIMING GENERATOR SENSE AMPLIFIER ADDRESS BUFFER 29 21 A-1 VCC 11 30 GND NOTE: Pin numbers apply to the 40-pin DIP or SOP. 532000B-2 Figure 3. LH532000B Block Diagram PIN DESCRIPTION SIGNAL PIN NAME NOTE A–1 Address input (BYTE mode) 1 A0 – A16 Address input D0 – D15 Data output CE OE/OE 1 Chip enable input Output enable input 2 SIGNAL PIN NAME OE1/OE1/DC Output enable input or Don’t care BYTE Byte/word mode switch VCC Power supply (+5 V) GND Ground NOTE 2 NOTES: 1. D15/A–1 pin becomes LSB address input (A–1) when the bit configuration is set in byte mode, and data output (D15) when in word mode. BYTE input pin selects bit configuration. 2. The active levels of OE/OE and OE1/OE1/DC are mask-programmable. Selecting DC allows the outputs to be active for both high and low levels applied to this pin. It is recommended to apply either a HIGH or a LOW to the DC pin. 3 LH532000B CMOS 2M MROM TRUTH TABLE CE OE/OE OE1/OE1 BYTE DATA OUTPUT ADDRESS INPUT A–1 (D15) D0 – D7 D8 – D15 LSB MSB SUPPLY CURRENT H X X X X High-Z High-Z – – Standby (ISB) L L/H X X X High-Z High-Z – – Operating (ICC) L X L/H X X High-Z High-Z – – Operating (ICC) D0 – D7 D8 – D15 A0 A16 Operating (ICC) L H/L H/L H Input inhibit L H/L H/L L L D0 – D7 High-Z A–1 A16 Operating (ICC) L H/L H/L L H D8 – D15 High-Z A–1 A16 Operating (ICC) NOTE: 1. X = H or L, High-Z = High-impedance. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage VCC – 0.3 to +7.0 V Input voltage VIN – 0.3 to VCC + 0.3 V Output voltage VOUT – 0.3 to VCC + 0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg – 65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER Supply voltage SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS TYP. MAX. UNIT Input ‘Low’ voltage VIL – 0.3 0.8 V Input ‘High’ voltage V IH 2.2 VCC + 0.3 V Output ‘Low’ voltage VOL I OL = 2.0 mA Output ‘High’ voltage VOH I OH = –400 µA Input leakage current | ILI | V IN = 0 V to VCC Output leakage current | ILO | ICC1 Operating current Standby current Input capacitance Output capacitance 0.4 2.4 NOTE V V 10 µA V OUT = 0 V to VCC 10 µA 1 t RC = tRC (MIN.) 50 t RC = 1 µs mA 2 ICC2 45 ICC3 t RC = tRC (MIN.) 45 t RC = 1 µs mA 3 ICC4 40 ISB1 CE = VIH 3 mA ISB2 CE = VCC - 0.2 V 100 µA CIN f = 1 MHz T A = 25°C 10 pF 10 pF COUT NOTES: 1. OE/OE1= VIL, CE/OE/OE1= VIH 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC - 0.2 V) or 0.2 V, CE = 0.2 V, outputs open 4 MIN. CMOS 2M MROM LH532000B AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER 120 ns SYMBOL MIN. 150 ns MAX. 120 MIN. UNIT Read cycle time tRC Address access time tAA 120 150 150 ns Chip enable access time tACE 120 150 ns ns Output enable delay time tOE Output hold time tOH CE to output in High-Z tCHZ 55 70 ns OE to output in High-Z tOHZ 55 70 ns 55 5 NOTE MAX. 70 ns 10 ns 1 NOTE: 1. This is the time required for the output to become high-impedance. AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude 0.6 V to 2.4 V Input rise/fall time 10 ns Input reference level 1.5 V Output reference level 0.8 V and 2.2 V Output load condition 1TTL +100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin. tRC (NOTE 2) A-1 - A16 (A0 - A16) tAA(NOTE 1) CE tACE tCHZ OE/OE1 OE/OE1 tOHZ tOE (NOTE 1) (NOTE 2) D0 - D7 DATA VALID (D0 - D15) tOH NOTES: 1. Data becomes valid after tAA, tACE, and tOE from address input, chip enable or output enable, respectively have been met. 2. Applied to byte mode. Signals in parentheses apply to word mode. 532000B-3 Figure 4. Timing Diagram 5 LH532000B CMOS 2M MROM PACKAGE DIAGRAMS 40DIP (DIP040-P-0600) 40 21 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 20 0.30 [0.012] 0.20 [0.008] 52.30 [2.059] 51.70 [2.035] 15.24 [0.600] TYP. 4.55 [0.179] 3.95 [0.156] 5.40 [0.213] 4.80 [0.189] 3.55 [0.140] 2.95 [0.116] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 40DIP 40-pin, 600-mil DIP 40SOP (SOP040-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 40 21 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 20 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 26.50 [1.043] 26.10 [1.028] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 40SOP 40-pin, 525-mil SOP 6 CMOS 2M MROM LH532000B 48TSOP (TSOP048-P-1218) 0.50 [0.020] TYP. 0.30 [0.012] 0.10 [0.004] 25 48 16.60 [0.654] 16.20 [0.638] 1 18.40 [0.724] 17.60 [0.693] 17.00 [0.669] 24 12.20 [0.480] 11.80 [0.465] 0.15 [0.006] 0.425 [0.017] 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] DIMENSIONS IN MM [INCHES] 0.20 [0.008] 0.00 [0.000] MAXIMUM LIMIT MINIMUM LIMIT 48TSOP 2 48-pin, 12 × 18 mm TSOP (Type I) ORDERING INFORMATION LH532000B Device Type X Package D N T TR 40-pin, 600-mil DIP (DIP040-P-0600) 40-pin, 525-mil SOP (SOP040-P-0525) 48-pin, 12 x 18 mm2 TSOP (Type I) (TSOP048-P-1218) 48-pin, 12 x 18 mm2 TSOP (Type I) Reverse bend (TSOP048-P-1218) CMOS 2M (256K x 8 or 128K x 16) Mask Programmable ROM Example: LH532000BD (CMOS 2M (256K x 8 or 128K x 16) Mask Programmable ROM, 40-pin, 600-mil DIP) 532000B-4 7