Cypress Semiconductor Product Qualification Report QTP# 040901 VERSION 2.1 March 2008 PSoC™ Mixed Signal Array Family S4AD-5CTI Technology, Fab 2 CY8C29466 CY8C29566 CY8C29666 CY8C29866 Mixed Signal Array with On-Chip Controller CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Fredrick Whitwer Principal Reliability Engineer (408) 943-2722 Mira Ben-Tzur Quality Engineering Director (408) 943-2675 Cypress Semiconductor PSoC™ Mixed-Signal Array family, S4AD-5CTI, Fab 2 Device: CY8C29xxxA 040901 V. 2.1 Page 2 of 12 March 2008 PRODUCT QUALIFICATION HISTORY Qual Report Description of Qualification Purpose Date Comp 010702 New Technology S4AD-5, New Product Programmable Clock Generator, CY2414ZC product family and bond option. Apr 01 040901 PSoC 8C29xxxA New Device Product Family on S4AD-5CTI Technology, Fab2 Oct 04 073302 Minor Changes to Metal 2 (MM2) masks on Hydra Device (8C29000AT) on S4AD-5 Technology, Fab 2 Jan 08 Cypress Semiconductor PSoC™ Mixed-Signal Array family, S4AD-5CTI, Fab 2 Device: CY8C29xxxA 040901 V. 2.1 Page 3 of 12 March 2008 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: Qualify New device CY8C29xxx product family in Technology S4D-5CTI in Fab 2 Marketing Part #: CY8C29466, CY8C29566, CY8C29666, CY8C29866 Device Description: 3.3V and 5.5V, Industrial, available in 28 lead PDIP, 28-lead SOIC, 28/48-lead SSOP and 44/100-pin TQFP, 48-lead MLF package respectively. Cypress Division: Cypress Semiconductor - Consumer and Computation Division TECHNOLOGY/FAB PROCESS DESCRIPTION S4AD-5CTI Number of Metal Layers: 2 Metal Composition: Metal 1: 500A Ti/6000A Al 0.5% Cu /1200A TiW Metal 2: 500A Ti/8000A Al 0.5% Cu/300A TiW Passivation Type and Materials: 3,000A TeOs / 6000A Si3N4 Free Phosphorus contents in top glass layer(%): 0% Number of Transistors in Device: 600,000 Number of Gates in Device 100,000 Generic Process Technology/Design Rule ( -drawn): Single Poly, Double Metal, 0.35 m Gate Oxide Material/Thickness (MOS): SiO2 / 110A Name/Location of Die Fab (prime) Facility: Cypress Semiconductor - Round Rock, TX Die Fab Line ID/Wafer Process ID: Fab2, S4AD-5 CTI PACKAGE AVAILABILITY PACKAGE ASSEMBLY SITE FACILITY 28-lead PDIP INDNS-O 28/48-lead SSOP TAIWN-T, CML-R, PHIL-M 48-lead MLF SEOUL-L 44/100-pin TQFP CML-R Note: Package Qualification details upon request. Cypress Semiconductor PSoC™ Mixed-Signal Array family, S4AD-5CTI, Fab 2 Device: CY8C29xxxA 040901 V. 2.1 Page 4 of 12 March 2008 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: Mold Compound Flammability Rating: SP28 28-Lead Shrunk Small Outline Package (SSOP) G600 V-O per UL94 Oxygen Rating Index: N/A Lead Frame Material: Copper Lead Finish, Composition / Thickness: NiPdAu Die Backside Preparation Method/Metallization: Backgrind Die Separation Method: Sawing 100% Die Attach Supplier: Ablestik Die Attach Material: 8290 Die Attach Method: Epoxy Bond Diagram Designation: 001-16740 Wire Bond Method: Thermosonic Wire Material/Size: Au, 1.0mil Thermal Resistance Theta JA °C/W: 96°C/W Package Cross Section Yes/No: N/A Assembly Process Flow: 49-14999 Name/Location of Assembly (prime) facility: AMKOR-PHIL (M) ELECTRICAL TEST / FINISH DESCRIPTION Test Location: CML-R Note: Please contact a Cypress Representative for other packages availability. Cypress Semiconductor PSoC™ Mixed-Signal Array family, S4AD-5CTI, Fab 2 Device: CY8C29xxxA 040901 V. 2.1 Page 5 of 12 March 2008 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT Stress/Test Test Condition (Temp/Bias) High Temperature Operating Life Dynamic Operating Condition, Vcc Max=3.8V, 150°C Early Failure Rate Dynamic Operating Condition, Vcc Max=5.5V, 125°C High Temperature Operating Life Dynamic Operating Condition, Vcc Max=3.8V, 150°C Latent Failure Rate Dynamic Operating Condition, Vcc Max=5.5V, 125°C Temperature Cycle MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C Result P/F P P P Precondition: JESD22 Moisture Sensitivity MSL 1 168 Hrs, 85C/85%RH+3IR-Reflow, 235°C+5, 0°C Pressure Cooker 121°C, 100%RH P MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C Precondition: JESD22 Moisture Sensitivity MSL 1 168 Hrs, 85C/85%RH+3IR-Reflow, 235°C+5, 0°C High Accelerated Saturation Test (HAST) 130°C, 5.5V, 85%RH, 130°C, 3.63V, 85%RH P Precondition: JESD22 Moisture Sensitivity MSL 1 168 Hrs, 85C/85%RH+3IR-Reflow, 235°C+5, 0°C Data Retention 150°C ± 5°C no bias P High Temperature Steady State Life 150°C, 363V, Vcc Max P Electrostatic Discharge Human Body Model (ESD-HBM) 2,200V Electrostatic Discharge 2,200V, 2,000V Human Body Model (ESD-HMB) MIL-STD-883, Method 3015.7 Electrostatic Discharge P Charge Device Model (ESD-CDM) 500V Cypress Spec. 25-00020 Age Bond Strength MIL-STD-883C, Method 2011 P Acoustic Microscopy Cypress Spec. 25-00104 P Low Temperature Operating Life -30C, 4.3V, 8MHZ P Endurance Test MIL-STD-883C, Method 1033 P Dynamic Latchup Sensitivity Cypress Spec. 01-00081 P Static Latchup Sensitivity 125°C, ± 300mA P JESD22, Method A114-B In accordance with JEDEC 17. Cypress Spec. 01-00081 P P Cypress Semiconductor PSoC™ Mixed-Signal Array family, S4AD-5CTI, Fab 2 Device: CY8C29xxxA 040901 V. 2.1 Page 6 of 12 March 2008 RELIABILITY FAILURE RATE SUMMARY Device Tested/ Device Hours # Fails Activation Energy Thermal3 A.F Failure Rate4 High Temperature Operating Life Early Failure Rate @125C 2007 Devices 0 N/A N/A 0 PPM High Temperature Operating Life1,2 Long Term Failure Rate 375,867 DHRs 0 0 .7 170 14 FITs Stress/Test 1 2 3 Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C. Chi-squared 60% estimations used to calculate the failure rate. Thermal Acceleration Factor is calculated from the Arrhenius equation ⎡E ⎡ 1 1 ⎤ ⎤ AF = exp ⎢ A ⎢ - ⎥ ⎥ ⎣ k ⎣ T 2 T1 ⎦ ⎦ where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. 4 Fit Rate calculation based on combined device hours from QTP# 010702 & 040901 Cypress Semiconductor PSoC™ Mixed-Signal Array family, S4AD-5CTI, Fab 2 Device: CY8C29xxxA 040901 V. 2.1 Page 7 of 12 March 2008 Reliability Test Data QTP #: Device Fab Lot # 010702 Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism STRESS: ACOUSTIC-MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 15 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 3.8V, Vcc Max CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 48 1005 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 48 1004 1 NON VISUAL CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 48 1005 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 3.8V, Vcc Max CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 80 120 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 500 120 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 80 120 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 500 120 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 80 120 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 500 120 0 STRESS: AGE BOND STRENGTH CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 15 0 TAIWN-T COMP 3 0 TAIWN-T 500 48 0 STRESS: DYNAMIC LATCH-UP TESTING, 11.5V CY2414ZC (7C841400A) 2101502 610106170/1/2 STRESS: LOW TEMPERATURE OPERATING LIFE, -30C, 4.3V CY2414ZC (7C841400A) 2101502 610106170/1/2 STRESS: ESD-CHARGE DEVICE MODEL, 500V CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 9 0 Cypress Semiconductor PSoC™ Mixed-Signal Array family, S4AD-5CTI, Fab 2 Device: CY8C29xxxA 040901 V. 2.1 Page 8 of 12 March 2008 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 010702 Assy Loc Duration Samp Rej Failure Mechanism STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,000V CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2103764 610106177 TAIWN-T COMP 10 0 STRESS: STATIC LATCH-UP TESTING, 125C, 10V, ±300mA CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 3 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 3 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 3 0 STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 3.63V, PRE COND 168 HR 85C/85%RH, MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 128 50 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 256 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 128 48 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 128 48 0 STRESS: HIGH TEMP STEADY STATE LIFE TEST, 150C, 3.63V CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 80 80 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 168 80 0 610106170/1/2 TAIWN-T COMP 45 0 STRESS: ENDURANCE TEST CY2414ZC (7C841400A) 2101502 STRESS: DATA RETENTION, PLASTIC, 150C CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 168 80 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 552 80 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 168 80 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 552 80 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 168 80 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 552 80 0 Cypress Semiconductor PSoC™ Mixed-Signal Array family, S4AD-5CTI, Fab 2 Device: CY8C29xxxA 040901 V. 2.1 Page 9 of 12 March 2008 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 010702 Assy Loc Duration Samp Rej STRESS: PRESSURE COOKER TEST, 121C, 100%RH, PRE COND 168 HR 85C/85%RH, MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 168 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 168 49 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 168 51 0 STRESS: TC COND. C -65C TO 150C, PRECONDITION 168 HRS 85C/85%RH, MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 300 50 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 500 50 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 1000 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 300 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 500 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 1000 50 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 300 50 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 500 50 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 1000 49 0 Failure Mechanism Cypress Semiconductor PSoC™ Mixed-Signal Array family, S4AD-5CTI, Fab 2 Device: CY8C29xxxA 040901 V. 2.1 Page 10 of 12 March 2008 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 040901 Assy Loc Duration Samp Rej STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 5.5V, Vcc Max CY8C29466 (8C29466A) 2415417 510405532 INDNS-O 96 1005 0 CY8C29466 (8C29466A) 2416473 510406227 INDNS-O 96 1002 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 125C, 5.5V, Vcc Max CY8C29466 (8C29466A) 2415417 510405532 INDNS-O 168 600 0 CY8C29466 (8C29466A) 2415417 510405532 INDNS-O 500 600 0 CY8C29466 (8C29466A) 2416473 510406227 INDNS-O 168 615 0 CY8C29466 (8C29466A) 2416473 510406227 INDNS-O 500 614 0 STRESS: DATA RETENTION, PLASTIC, 150C CY8C29466 (8C29466A) 2415417 510405532 INDNS-O 168 160 0 CY8C29466 (8C29466A) 2415417 510405532 INDNS-O 552 160 0 CY8C29466 (8C29466A) 2416473 510406227 INDNS-O 168 160 0 CY8C29466 (8C29466A) 24156473 510406227 INDNS-O 552 160 0 3 0 STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V CY8C29466 (8C29466A) 2415417 510405532 INDNS-O COMP STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, 2,200V CY8C29466 (8C29466A) 2415417 510405532 INDNS-O COMP 9 0 INDNS-O COMP 9 0 COMP 3 0 INDNS-O 128 50 0 INDNS-O 168 50 0 STRESS: ESD-CHARGE DEVICE MODEL, 500V CY8C29466 (8C29466A) 2415417 510405532 STRESS: STATIC LATCH-UP TESTING, 125C, 10V, ±300mA CY8C29466 (8C29466A) 2415417 510405532 INDNS-O STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 5.5V CY8C29466 (8C29466A) 2415417 510405532 STRESS: PRESSURE COOKER TEST, 121C, 100%RH CY8C29466 (8C29466A) 2415417 510405532 Failure Mechanism Cypress Semiconductor PSoC™ Mixed-Signal Array family, S4AD-5CTI, Fab 2 Device: CY8C29xxxA 040901 V. 2.1 Page 11 of 12 March 2008 Reliability Test Data QTP #: Device Fab Lot # 040901 Assy Lot # Assy Loc Duration Samp Rej STRESS: TC COND. C -65C TO 150C CY8C29466 (8C29466A) 2415417 510405532 INDNS-O 300 50 0 CY8C29466 (8C29466A) 2415417 510405532 INDNS-O 500 50 0 CY8C29466 (8C29466A) 2415417 510405532 INDNS-O 1000 50 0 CY8C29466 (8C29466A) 2416473 510406227 INDNS-O 300 50 0 CY8C29466 (8C29466A) 2416473 510406227 INDNS-O 500 50 0 CY8C29466 (8C29466A) 2416473 510406227 INDNS-O 1000 50 0 Failure Mechanism Cypress Semiconductor PSoC™ Mixed-Signal Array family, S4AD-5CTI, Fab 2 Device: CY8C29xxxA 040901 V. 2.1 Page 12 of 12 March 2008 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 073302 Assy Loc Duration Samp Rej Failure Mechanism STRESS: SORT YIELD CY8C29466 (8C29466A) 2727919 COMP COMPARABLE STRESS: DATA RETENTION, PLASTIC, 150C CY8C29466 (8C29466A) 2727919 610748117 PHIL-M 500 30 0 CY8C29466 (8C29466A) 2727919 610748117 PHIL-M 1000 30 0 CY8C29466 (8C29466A) 2727919 610748118 PHIL-M 500 25 0 CY8C29466 (8C29466A) 2727919 610748118 PHIL-M 1000 25 0 CY8C29466 (8C29466A) 2727919 610748119 PHIL-M 500 30 0 CY8C29466 (8C29466A) 2727919 610748119 PHIL-M 1000 30 0 CY8C29466 (8C29466A) 2727919 610748117 PHIL-M COMP 30 0 CY8C29466 (8C29466A) 2727919 610748118 PHIL-M COMP 30 0 CY8C29466 (8C29466A) 2727919 610748119 PHIL-M COMP 25 0 STRESS: ENDURANCE STRESS: ETEST YIELD CY8C29466 (8C29466A) 2727919 COMP COMPARABLE