STMICROELECTRONICS STW9N150

STW9N150
N-channel 1500V - 2.2Ω - 8A - TO-247
Very high voltage PowerMESH™ Power MOSFET
TARGET SPECIFICATION
General features
Type
VDSS
RDS(on)
ID
Pw
STW9N150
1500V
< 2.7Ω
8A
350W
■
100% avalanche tested
■
Avalanche ruggedness
■
Gate charge minimized
■
Very low intrinsic capacitances
■
High speed switching
■
Very low on-resistance
TO-247
Description
Using the well consolidated high voltage MESH
OVERLAY™ process, STMicroelectronics has
designed an advanced family of Power MOSFETs
with outstanding performances. The strengthened
layout coupled with the Company’s proprietary
edge termination structure, gives the lowest
RDS(on) per area, unrivalled gate charge and
switching characteristics.
Internal schematic diagram
Applications
■
Switching application
Order code
Part number
Marking
Package
Packaging
STW9N150
W9N150V
TO-247
Tube
May 2007
Rev 1
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
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www.st.com
9
Electrical ratings
1
STW9N150
Electrical ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage (VGS = 0)
1500
V
VGS
Gate- source voltage
± 30
V
ID
Drain current (continuous) at TC = 25°C
8
A
ID
Drain current (continuous) at TC = 100°C
5
A
Drain current (pulsed)
32
A
Total dissipation at TC = 25°C
350
W
Derating factor
0.37
W/°C
-55 to 150
°C
Value
Unit
Rthj-case Thermal resistance junction-case max
0.36
°C/W
Rthj-amb Thermal resistance junction-ambient max
62.5
°C/W
Max value
Unit
IDM
(1)
PTOT
Tj
Tstg
Operating junction temperature
Storage temperature
1. Pulse width limited by safe operating area
Table 2.
Symbol
Table 3.
Symbol
2/9
Thermal data
Parameter
Avalanche characteristics
Parameter
IAR
Avalanche current, repetitive or not-repetitive
(pulse width limited by Tj max)
Tbd
A
EAS
Single pulse avalanche energy
(starting Tj = 25°C, ID = IAR, VDD = 50V)
Tbd
mJ
STW9N150
2
Electrical characteristics
Electrical characteristics
(Tcase =25°C unless otherwise specified)
Table 4.
Symbol
V(BR)DSS
On /off states
Parameter
Drain-source
breakdown voltage
Test conditions
ID = 1mA, VGS = 0
IDSS
VDS = Max rating
Zero gate voltage
drain current (VGS = 0) VDS = Max rating, TC=125°C
IGSS
Gate-body leakage
current (VDS = 0)
Gate threshold voltage VDS = VGS, ID = 250µA
RDS(on
Static drain-source on
resistance
Symbol
Typ.
Max.
1500
3
VGS = 10V, ID = 1.3A
Unit
V
10
500
µA
µA
± 100
nA
4
5
V
2.2
2.7
Ω
Typ.
Max.
Unit
VGS = ± 30V
VGS(th)
Table 5.
Min.
Dynamic
Parameter
gfs (1)
Forward
transconductance
Ciss
Coss
Crss
Test conditions
Min.
VDS = 30V, ID = 2A
Tbd
S
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25 V, f = 1 MHz, VGS = 0
3600
280
35
pF
pF
pF
Rg
Gate input resistance
f=1MHz Gate DC Bias=0
Test signal level=20mV
open drain
2
Ω
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 600V, ID = 2.5A,
VGS = 10V
(see Figure 2)
90
Tbd
Tbd
nC
nC
nC
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
3/9
Electrical characteristics
STW9N150
Table 6.
Switching times
Symbol
Parameter
td(on)
tr
td(off)
tf
Table 7.
Symbol
ISD
ISDM
(1)
VSD (2)
trr
Qrr
IRRM
trr
Qrr
IRRM
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Test conditions
VDD = 750V, ID = 2A,
RG = 4.7Ω, VGS = 10V
(see Figure 1)
Typ.
Max Unit
Tbd
Tbd
Tbd
Tbd
ns
ns
ns
ns
Source drain diode
Parameter
Test conditions
Min. Typ. Max Unit
Source-drain current
Source-drain current (pulsed)
8
32
A
A
Tbd
V
Forward on voltage
ISD = 4A, VGS = 0
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 4A, di/dt = 100A/µs
VDD= 45V Tj = 25°C
(see Figure 3)
Tbd
Tbd
Tbd
ns
µC
A
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 4A, di/dt = 100A/µs
VDD= 45V Tj = 150°C
(see Figure 3)
Tbd
Tbd
Tbd
ns
µC
A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300µs, duty cycle 1.5%
4/9
Min.
STW9N150
Test circuits
3
Test circuits
Figure 1.
Switching times test circuit for
resistive load
Figure 3.
Test circuit for inductive load
Figure 4.
switching and diode recovery times
Unclamped Inductive load test
circuit
Figure 5.
Unclamped inductive waveform
Switching time waveform
Figure 2.
Figure 6.
Gate charge test circuit
5/9
Package mechanical data
4
STW9N150
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
6/9
STW9N150
Package mechanical data
TO-247 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
inch
MAX.
MIN.
TYP.
MAX.
A
4.85
5.15
0.19
0.20
A1
2.20
2.60
0.086
0.102
b
1.0
1.40
0.039
0.055
b1
2.0
2.40
0.079
0.094
0.134
b2
3.0
3.40
0.118
c
0.40
0.80
0.015
0.03
D
19.85
20.15
0.781
0.793
E
15.45
15.75
0.608
e
5.45
L
14.20
14.80
0.560
L1
3.70
4.30
0.14
L2
0.620
0.214
18.50
0.582
0.17
0.728
øP
3.55
3.65
0.140
0.143
øR
4.50
5.50
0.177
0.216
S
5.50
0.216
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Revision history
5
STW9N150
Revision history
Table 8.
8/9
Revision history
Date
Revision
24-May-2007
1
Changes
First release
STW9N150
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