NEC UPA1728

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µPA1728
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
PACKAGE DRAWING (Unit : mm)
The µPA1728 is N-Channel MOS Field Effect Transistor
designed for high current switching applications.
8
5
1, 2, 3
; Source
4
; Gate
5, 6, 7, 8 ; Drain
FEATURES
• Single chip type
• Low On-state Resistance
1.44
RDS(on)2 = 23 mΩ (TYP.) (VGS = 4.5 V, ID = 4.5 A)
4.4
0.8
+0.10
–0.05
RDS(on)3 = 24 mΩ (TYP.) (VGS = 4.0 V, ID = 4.5 A)
• Low Ciss : Ciss = 1700 pF (TYP.)
6.0 ±0.3
4
5.37 Max.
0.15
★
★
1
0.05 Min.
★
RDS(on)1 = 19 mΩ (TYP.) (VGS = 10 V, ID = 4.5 A)
1.8 Max.
★
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
1.27
0.40
0.5 ±0.2
0.10
0.78 Max.
+0.10
–0.05
0.12 M
ORDERING INFORMATION
PART NUMBER
PACKAGE
µPA1728
Power SOP8
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS
60
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
V
Drain Current (DC)
ID(DC)
±9
A
ID(pulse)
±36
A
PT
2.0
W
Drain Current (Pulse)
Note1
Total Power Dissipation (TA = 25 °C)
Note2
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Channel Temperature
Storage Temperature
Single Avalanche Current
150
°C
Tstg
–55 to + 150
°C
Note3
IAS
9
A
Note3
EAS
8.1
mJ
Single Avalanche Energy
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1 %
★
Tch
Gate
Protection
Diode
Source
2
2. Mounted on ceramic substrate of 1200 mm x 2.2 mm
3. Starting Tch = 25°C, RG = 25 Ω, TGS = 20 V →0 V
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
Exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G14321EJ1V0DS00 (1st edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
1999,2000
µPA1728
★ ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
Drain to Source On-state Resistance
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
RDS(on)1
VGS = 10 V, ID = 4.5 A
19
26
mΩ
RDS(on)2
VGS = 4.5 V, ID = 4.5 A
23
29
mΩ
RDS(on)3
VGS = 4.0 V, ID = 4.5 A
24
34
mΩ
VGS(off)
VDS = 10 V, ID = 1 mA
1.5
2.0
2.5
V
Forward Transfer Admittance
| yfs |
VDS = 10 V, ID = 4.5 A
6.0
12
Drain Leakage Current
IDSS
VDS = 60 V, VGS = 0 V
10
µA
Gate to Source Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
±10
µA
Input Capacitance
Ciss
VDS = 10 V
1700
pF
Output Capacitance
Coss
VGS = 0 V
270
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
130
pF
Turn-on Delay Time
td(on)
ID = 4.5 A
17
ns
VGS(on) = 10 V
69
ns
td(off)
VDD = 30 V
77
ns
tf
RG = 10 Ω
31
ns
Gate to Source Cut-off Voltage
Rise Time
tr
Turn-off Delay Time
Fall Time
S
Total Gate Charge
QG
ID = 9 A
31
nC
Gate to Source Charge
QGS
VDD = 48 V
4.4
nC
Gate to Drain Charge
QGD
VGS = 10 V
9.1
nC
VF(S-D)
IF = 9 A, VGS = 0 V
0.82
V
Reverse Recovery Time
trr
IF = 9 A, VGS = 0 V
41
ns
Reverse Recovery Charge
Qrr
di/dt = 100A/µs
76
nC
Body Diode Forward Voltage
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
D.U.T.
L
RL
PG.
50 Ω
VDD
VGS = 20 → 0 V
RG
PG.
VGS
VGS
Wave Form
0
90 %
ID
VGS
0
ID
Starting Tch
τ = 1 µs
Duty Cycle ≤ 1 %
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
2
IG = 2 mA
RL
50 Ω
VDD
10 %
0 10 %
Wave Form
τ
VDD
PG.
90 %
BVDSS
VDS
ID
90 %
VDD
ID
IAS
VGS(on)
10 %
Data Sheet G14321EJ1V0DS00
tr td(off)
td(on)
ton
tf
toff
µPA1728
[MEMO]
Data Sheet G14321EJ1V0DS00
3
µPA1728
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confirm that this is the latest version.
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consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
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M7 98. 8