AND8048/D SPICE Device Model NTHD5905T1 Dual P–Channel 1.8 V (G–S) MOSFET http://onsemi.com APPLICATION NOTE CHARACTERISTICS DESCRIPTION • • • • • • The attached SPICE Model describes typical electrical characteristics of the p–channel vertical DMOS. The sub–circuit model was extracted and optimized over a 25°C to 125°C temperature range under pulse conditions for 0 to –5 volts gate drives. Saturated output impedance model accuracy has been maximized for gate biases near threshold. A novel gate–to–drain feedback capacitor network is used to model gate charge characteristics while avoiding convergence problems of switched Cgd model. Model parameter values are optimized to provide a best fit to measure electrical data and are not intended as an exact physical description of a device. P–Channel Vertical DMOS Macro–Model (Sub–circuit) Level 3 MOS Applicable for both Linear and Switch Mode Applicable over a –55 to 125°C Temperature Range Models Gate Charge, Transient, and Diode Reverse Recovery Characteristics D 4 M R M G 3 DB 1 CGS 2 S Figure 1. Model Sub–circuit This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Semiconductor Components Industries, LLC, 2001 April, 2001 – Rev. 0 1 Publication Order Number: AND8048/D AND8048/D MODEL EVALUATION P–CHANNEL DEVICE (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Conditions Typical Unit Static VGS(th) VDS = VGS, ID = –250 A 0.83 V On–State Drain Current (Note 1.) ID(on) VDS –5.0 V, VGS = 4.5 V 36 A Drain–Source On–State Resistance (Note 1.) rDS(on) VGS = –4.5 V, ID = –3.0 A VGS = –2.5 V, ID = –2.5 A VGS = –1.8 V, ID = –1.0 A 0.080 0.110 0.142 gfs VDS = 5.0 V, ID = 3.0 A 7.6 S VSD IS = –0.9 A, VGS = 0.0 V –0.80 V Gate Threshold Voltage Forward Transconductance (Note 1.) Diode Forward Voltage (Note 1.) Dynamic (Note 2.) Total Gate Charge Qg Gate–Source Charge Qgs 35 VDS = –4.0 V, VGS = –4.5 V, ID = –3.0 A 0.5 Gate–Drain Charge Qgd 1.5 Turn–On Delay Time td(on) 13 Rise Time Turn–Off Delay Time tr VDD = –4.0 V, RL = 4.0 , ID –1.0 A, 19 td(off) VGEN = –4.5 V, RG = 6.0 24 Fall Time tf Source–Drain Reverse Recovery Time trr 12 IF = –0.9 A, di/dt = 100 A/s 1. Pulse test: pulse width 300 s, duty cycle 2%. 2. Guaranteed by design, not subject to production testing. http://onsemi.com 2 28 nC ns AND8048/D 10 10 VGS = 2.5 V ID, DRAIN CURRENT (A) 6 VGS = 2 V 4 2 –55°C 8 ID, DRAIN CURRENT (A) VGS = 3 V VGS = 3.5 V VGS = 5 V 8 125°C 6 4 25°C 2 VGS = 1.5 V 0 0 0 0.5 1 1.5 2 2.5 3 0 1 1.5 2.0 2.5 3 VDS, DRAIN–TO–SOURCE VOLTAGE (V) VGS, GATE–TO SOURCE (V) Figure 2. Drain Current vs. Drain–to–Source Voltage Figure 3. Drain Current vs. Gate–to–Source Voltage 1.0 SQRT (IDsat) 3.2 0.8 2.4 0.6 1.6 0.4 0.8 0.2 RDS(on) 0.0 0 1 2 3 0.30 RDS(on), ON–RESISTANCE (Ω) RDS(on), ON–RESISTANCE (Ω) 4.0 SQRT (IDsat) (A) 0.5 0.0 5 4 0.25 VGS = 1.8 V 0.20 0.15 VGS = 4.5 V 0.10 VGS = 4.5 V 0.05 0.00 0 2 VGS, GATE–TO SOURCE VOLTAGE (V) 4 6 8 10 ID, DRAIN CURRENT (A) Figure 4. Sqrt vs. Gate–to–Source Voltage Figure 5. On–Resistance vs. Drain Current 1000 5 4.0 VGS VDS (V) CAPACITANCE (pF) 600 400 4 VDS Ciss 2.4 3 1.6 2 0.8 2 Coss 200 Crss 0 0 0.0 0 2 4 6 8 0 1 2 3 4 VDS, DRAIN–TO–SOURCE VOLTAGE (V) Qg (nC) Figure 6. Capacitance vs. Drain–to–Source Voltage Figure 7. VDS vs. Qg http://onsemi.com 3 5 6 VGS (V) 3.2 800 AND8048/D H–SPICE .SUBCKT Si5905DC 4 1 2 M1 3 1 2 2 PMOS W = 183649u L = 0.50u M1 2 1 2 4 NMOS W = 183649u L = 1.05u R1 4 3 RTEMP 18E–3 CGS 1 2 540E–12 DBD 2 4 DBD ******************************************************************************************* .MODEL PMOS PMOS (LEVEL = 3 TOX = 1.7E–8 +RS = 45E–3 RD = 0 NSUB = 0.67E16 +KP = 4.7E–5 UO = 400 +VMAX = 0 XJ = 5E–7 KAPPA = 20E–3 +ETA = 1E–4 TPG = –1 +IS = 0 LD = 0 CAPOP = 5 +CGSO = 0 CGDO = 0 CGBO = 0 +TLEV = 1 BEX = –1.5 TCV = 1.5E–3 +NFS = 0.8E12 DELTA = 0.1) ******************************************************************************************* .MODEL NMOS NMOS (LEVEL = 3 TOX = 1.7E–8 +NSUB = 16E16 NSF = 10E11 TPG = –1) ******************************************************************************************* .MODEL DBD D (CJO = 200E–12 VJ = 0.38 M = 0.31 +RS = 0.6 FC = 0.5 IS = 1E–8 TT = 9E–8 N = 1 BV = 8.5) ******************************************************************************************* .MODEL RTEMP R (TC1 = 7.5E–3 TC2 = 5.5E–6) ******************************************************************************************* .ENDS http://onsemi.com 4 AND8048/D P–SPICE .SUBCKT Si5905DC 4 1 2 M1 3 1 2 2 PMOS W = 183649u L = 0.50u M1 2 1 2 4 NMOS W = 183649u L = 1.05u R1 4 3 RTEMP 18E–3 CGS 1 2 540E–12 DBD 2 4 DBD ******************************************************************************************* .MODEL PMOS PMOS (LEVEL = 3 TOX = 1.7E–8 +RS = 45E–3 RD = 0 NSUB = 0.67E16 +KP = 4.7E–5 UO = 400 +VMAX = 0 XJ = 5E–7 KAPPA = 20E–3 +ETA = 1E–4 TPG = –1 +IS = 0 LD = 0 CAPOP = 5 +CGSO = 0 CGDO = 0 CGBO = 0 +NFS = 0.8E12 DELTA = 0.1) ******************************************************************************************* .MODEL NMOS NMOS (LEVEL = 3 TOX = 1.7E–8 +NSUB = 16E16 NSF = 10E11 TPG = –1) ******************************************************************************************* .MODEL DBD D (CJO = 200E–12 VJ = 0.38 M = 0.31 +RS = 0.6 FC = 0.5 IS = 1E–8 TT = 9E–8 N = 1 BV = 8.5) ******************************************************************************************* .MODEL RTEMP R (TC1 = 7.5E–3 TC2 = 5.5E–6) ******************************************************************************************* .ENDS http://onsemi.com 5 AND8048/D IS–SPICE .SUBCKT Si5905DC 4 1 2 M1 3 1 2 2 PMOS W = 183649u L = 0.50u M1 2 1 2 4 NMOS W = 183649u L = 1.05u R1 4 3 18E–3 RTEMP CGS 1 2 540E–12 DBD 2 4 DBD ******************************************************************************************* .MODEL PMOS PMOS (LEVEL = 3 TOX = 1.7E–8 +RS = 45E–3 RD = 0 NSUB = 0.67E16 +KP = 4.7E–5 UO = 400 +VMAX = 0 XJ = 5E–7 KAPPA = 20E–3 +ETA = 1E–4 TPG = –1 +IS = 0 LD = 0 CAPOP = 5 +CGSO = 0 CGDO = 0 CGBO = 0 +NFS = 0.8E12 DELTA = 0.1) ******************************************************************************************* .MODEL NMOS NMOS (LEVEL = 3 TOX = 1.7E–8 +NSUB = 16E16 NSF = 10E11 TPG = –1) ******************************************************************************************* .MODEL DBD D (CJO = 200E–12 VJ = 0.38 M = 0.31 +RS = 0.6 FC = 0.5 IS = 1E–8 TT = 9E–8 N = 1 BV = 8.5) ******************************************************************************************* .MODEL RTEMP R (TC1 = 7.5E–3 TC2 = 5.5E–6) ******************************************************************************************* .ENDS http://onsemi.com 6 AND8048/D Notes http://onsemi.com 7 AND8048/D ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). 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