2SK1764 Silicon N Channel MOS FET REJ03G0970-0200 (Previous: ADE-208-1317) Rev.2.00 Sep 07, 2005 Application • Low frequency amplifier • High speed switching Features • • • • Low on-resistance High speed switching 4 V Gate drive device can be driven from 5 V source Suitable for switching regulator, DC-DC converter Outline RENESAS Package code: PLZZ0004CA-A (Package name: UPAK R ) 3 D 2 1 1. Gate 2. Drain 3. Source 4. Drain G 4 S Note: Marking is "KY". *UPAK is a trademark of Renesas Technology Corp. Rev.2.00 Sep 07, 2005 page 1 of 6 2SK1764 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Symbol VDSS Ratings 60 Unit V VGSS ID ±20 2 V A 4 2 A A ID(pulse) IDR Channel power dissipation Channel temperature *1 Pch*2 Tch 1 150 Storage temperature Tstg Notes: 1. PW ≤ 100 µs, duty cycle ≤ 10 % 2. Value on the alumina ceramic board (12.5 x 20 x 0.7 mm) –55 to +150 W °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Symbol V(BR)DSS Min 60 Typ — Max — Unit V Gate to source breakdown voltage Gate to source cutoff voltage V(BR)GSS VGS(off) ±20 1 — — — 2 V V IG = ±100 µA, VDS = 0 VDS = 10 V, ID = 1 mA Drain to source cutoff current Gate to source cutoff current IDSS IGSS — — — — 10 ±5 µA µA VDS = 50 V, VGS = 0 VGS = ±15 V, VDS = 0 Static drain to source on state resistance Static drain to source on state resistance RDS(on)1 — 0.3 0.45 Ω VGS = 10 V, ID = 1 A* RDS(on)2 — 0.4 0.60 Ω VGS = 4 V, ID = 1 A* Forward transfer admittance Input capacitance |yfs| Ciss 0.9 — 1.7 140 — — S pF Output capacitance Reverse transfer capacitance Coss Crss — — 75 20 — — pF pF VDS = 10 V, ID = 1 A* VDS = 10 V, VGS = 0, f = 1 MHz ton toff — — 18 80 — — ns ns Turn on time Turn off time Note: 3. Pulse Test Rev.2.00 Sep 07, 2005 page 2 of 6 Test Conditions ID = 10 mA, VGS = 0 3 3 3 3 VDS = 10 V, ID = 1 A* , RL = 30 Ω 2SK1764 Maximum Channel Power Dissipation Curve Safe Operation Area 10 Drain Current Ambient Temperature Drain Current ID (A) 3.5 V 2 3V 1 VGS = 2.5 V 2 4 6 8 10 3 30 100 VDS (V) VDS = 10 V Pulse Test 4 3 2 1 –25°C TC= 25°C 75°C 0 10 1 2 3 4 5 Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage Static Drain to Source On State Resistance vs. Drain Current 1.0 Pulse Test 0.8 2A 0.6 0.4 1A ID = 0.5 A 0.2 0 1.0 5 2 4 6 8 Gate to Source Voltage VGS (V) Rev.2.00 Sep 07, 2005 page 3 of 6 10 Static Drain to Source on State Resistance RDS (on) (Ω) Drain Current ID (A) 3 0.3 Typical Transfer Characteristics 4.5 V Pulse Test 5V 7V 4V 4 0 Drain to Source Saturation Voltage VDS (on) (V) 10 V n Drain to Source Voltage Ta (°C) Typical Output Characteristics 5 io Ta = 25°C 0.01 0.1 200 at t) 150 er ho 0.1 op s (1 100 s 0.3 C s 50 D ) in on n io s S( at a i R D r pe re y O is a d b th ite lim m 1.0 0.03 0 m 0.4 1 0.8 10 1.2 3 = ID (A) 1.6 PW Channel Power Dissipation Pch** (W) (** on the almina ceramic board) Main Characteristics 5 Pulse Test 2 VGS = 4 V 1.0 0.5 10 V 0.2 0.1 0.05 0.05 0.1 0.2 0.5 1.0 2 Drain Current ID (A) 5 Static Drain to Source on State Resistance vs. Temperature 1.0 Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance yfs (S) Static Drain to Source on State Resistance RDS (on) (Ω) 2SK1764 Pulse Test ID = 2 A 0.8 1A 0.5 A VGS = 4 V 0.6 0.4 2 A 0.5 A 1A VGS = 10 V 0.2 0 –40 0 40 80 120 160 0.2 0.1 0.05 0.05 0.1 0.2 1.0 0.5 5 2 Typical Capacitance vs. Drain to Source Voltage VGS = 0 f = 1 MHz Capacitance C (pF) 300 100 50 20 Ciss 100 Coss 30 Crss 10 3 1 0.1 0.2 0.5 1.0 2 0 5 10 20 30 40 50 Reverse Drain Current IDR (A) Drain to Source Voltage VDS (V) Dynamic Input Characteristics Switching Characteristics 100 100 20 80 16 25 V 10 V 12 VDS VDD = 50 V VGS 20 ID = 1.5 A 25 V 10 V 2 8 4 6 8 Gate Charge Qg (nc) Rev.2.00 Sep 07, 2005 page 4 of 6 4 0 10 td (off) 50 Switching Time t (ns) VDD = 50 V Gate to Source Voltage VGS (V) Reverse Recovery Time trr (ns) 0.5 1000 10 0.05 Drain to Source Voltage VDS (V) 75°C Body to Drain Diode Reverse Recovery Time 200 0 1.0 Drain Current ID (A) di/dt = 50 A/µs, Ta = 25°C VGS = 0 Pulse Test 500 40 2 VDS = 10 V –25°C Pulse Test T = 25°C C Case Temperature TC (°C) 1000 60 5 tf VGS = 10 V VDD = 30 V PW = 2 µs, duty < 1 % • 20 • tr 10 5 td (on) 2 1 0.05 0.1 0.2 0.5 1.0 2 Drain Current ID (A) 5 2SK1764 Reverse Drain Current vs. Source to Drain Voltage Reverse Drain Current IDR (A) 2.0 Pulse Test 1.6 1.2 10 V 15 V 5V 0.8 VGS = 0, –5 V 0.4 0 0.4 0.8 1.2 1.6 2.0 Source to Drain Voltage VSD (V) Rev.2.00 Sep 07, 2005 page 5 of 6 2SK1764 Package Dimensions RENESAS Code Package Name MASS[Typ.] PLZZ0004CA-A UPAK / UPAKV 0.050g 1.5 1.5 3.0 1.5 ± 0.1 0.44 Max 2.5 ± 0.1 4.25 Max (1.5) 0.44 Max (0.2) 0.53 Max 0.48 Max 0.8 Min φ1 0.4 4.5 ± 0.1 1.8 Max Unit: mm (2.5) SC-62 (0.4) JEITA Package Code Ordering Information Part Name 2SK1764KYTL-E 2SK1764KYTR-E Quantity 3000 pcs 3000 pcs Shipping Container Taping, φ178 mm Reel Taping, φ178 mm Reel Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.2.00 Sep 07, 2005 page 6 of 6 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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