2SJ386 Silicon P Channel MOS FET REJ03G0861-0200 (Previous: ADE-208-1195) Rev.2.00 Sep 07, 2005 Description High speed power switching Features • • • • • Low on-resistance High speed switching Low drive current 4 V gate drive device can be driven from 5 V source Suitable for Switching regulator, DC-DC converter Outline RENESAS Package code: PRSS0003DC-A (Package name: TO-92 Mod) D 1. Source 2. Drain 3. Gate G 32 Rev.2.00 Sep 07, 2005 page 1 of 5 1 S 2SJ386 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Symbol VDSS Value –30 Unit V VGSS ID ±20 –3 V A –5 –3 A A ID (pulse) IDR Note 1 Channel dissipation Channel temperature Pch Tch 0.9 150 W °C Storage temperature Note: 1. PW ≤ 10 µs, duty cycle ≤ 1% Tstg –55 to +150 °C Electrical Characteristics (Ta = 25°C) Item Symbol Min Typ Max Unit V (BR) DSS V (BR) GSS –30 ±20 — — — — V V ID = –10 mA, VGS = 0 IG = ±100 µA, VDS = 0 IGSS IDSS — — — — ±10 –10 µA µA VGS = ±16 V, VDS = 0 VDS = –24 V, VGS = 0 Gate to source cutoff voltage Static drain to source on state resistance VGS (off) RDS (on) –1.0 — — 0.3 –2.5 0.4 V Ω ID = –1 mA, VDS = –10 V Note 2 ID = –2 A, VGS = –10 V Forward transfer admittance RDS (on) |yfs| — 1.0 0.55 1.7 0.8 — Ω S ID = –2 A, VGS = –4 V Note 2 ID = –1 A, VDS = –10 V Input capacitance Output capacitance Ciss Coss — — 177 120 — — pF pF Reverse transfer capacitance Turn-on delay time Crss td (on) — — 59 8 — — pF ns VDS = –10 V VGS = 0 f = 1 MHz Rise time Turn-off delay time tr td (off) — — 28 45 — — ns ns tf — 60 — ns Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Zero gate voltage drain current Fall time Note: 2. Pulse test Rev.2.00 Sep 07, 2005 page 2 of 5 Test Conditions Note 2 ID = –2 A VGS = –10 V RL = 15 Ω 2SJ386 Main Characteristics Maximum Safe Operation Area Power vs. Temperature Derating –10 ID (A) Drain Current Channel Dissipation 0.4 0 0 50 100 150 Ambient Temperature O pe ra tio n Operation in this area is limited by RDS (on) –0.1 –0.03 Ta (°C) Ta = 25°C 1 shot pulse –1.6 –30 –100 VDS (V) VDS = –10 V Pulse Test Ta = 25°C Pulse Test –4 25°C Tc = –25°C –3 Drain Current –2.5 V –0.8 –0.4 VGS = –2 V 0 –2 –4 –6 –8 –5 Ta = 25°C Pulse Test –4 –3 –2 ID = –5 A –3 A –1 A 0 0 –4 –8 –12 Gate to Source Voltage Rev.2.00 Sep 07, 2005 page 3 of 5 –1 –16 –20 VGS (V) 0 –1 –2 –3 –4 Gate to Source Voltage VDS (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage –1 75°C –2 0 –10 –5 VGS (V) Static Drain to Source on State Resistance vs. Drain Current Drain to Source on State Resistance RDS (on) (Ω) Drain Current –10 –5 –3 V Drain to Source Voltage Drain to Source Saturation Voltage VDS (on) (V) –3 Typical Transfer Characteristics –1.2 0 –1 Drain to Source Voltage ID (A) ID (A) –5 V –4 V –3.5 V m s DC –0.3 Typical Output Characteristics –2.0 10 –1 –0.01 –0.1 –0.3 200 = s 0.8 –3 m 1.2 100 µs PW 1 Pch (W) 1.6 10 Pulse Test 5 2 1 VGS = –4 V 0.5 –10 V 0.2 0.1 –0.1 –0.2 –0.5 –1 Drain Current –2 –5 ID (A) –10 2SJ386 1.0 ID = –3 A 0.8 –1 A 0.6 ID = –5 A 0.4 –3 A 0.2 –1 A –10 V 0 –40 0 40 80 120 Ambient Temperature 160 VDS = –10 V Pulse Test 5 Tc = –25°C 2 25°C 1 75°C 0.5 0.2 0.1 –0.1 –0.2 Ta (°C) VDS (V) Coss 50 Crss 20 10 Drain to Source Voltage Capacitance C (pF) 500 100 VGS = 0 f = 1 MHz 0 –10 –20 –30 –40 –50 0 –4 –20 –8 VDS –30 –12 VDD = –30 V –20 V –10 V VGS –40 –50 0 4 8 Gate Charge 12 16 –16 –20 20 Qg (nc) Reverse Drain Current vs. Source to Drain Voltage 200 –5 Reverse Drain Current IDR (A) Switching Time t (ns) 0 VDD = –10 V –20 V –30 V –10 Switching Characteristics 50 –10 –5 ID = –3 A Drain to Source Voltage VDS (V) 100 –2 Dynamic Input Characteristics 1000 Ciss –1 Drain Current ID (A) Typical Capacitance vs. Drain to Source Voltage 200 –0.5 tf td(off) 20 tr td(on) 10 5 VGS = –10 V, VDD = –30 V PW = 2 µs, duty ≤ 1 % 2 –0.05 –0.1 –0.2 –0.5 Drain Current Rev.2.00 Sep 07, 2005 page 4 of 5 –1 –2 ID (A) Pulse Test –4 –10 V –3 –5 V –2 VGS = 0 –1 0 –5 –1.2 –1.6 Source to Drain Voltage VSD 0 –0.4 –0.8 –2.0 (V) VGS (V) VGS = –4 V 10 Gate to Source Voltage Pulse Test Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance RDS (on) (Ω) Static Drain to Source on State Resistance vs. Temperature 2SJ386 Package Dimensions JEITA Package Code RENESAS Code Package Name MASS[Typ.] SC-51 PRSS0003DC-A TO-92 Mod / TO-92 ModV 0.35g 4.8 ± 0.4 Unit: mm 2.3 Max 0.65 ± 0.1 0.75 Max 0.7 0.60 Max 0.55 Max 10.1 Min 8.0 ± 0.5 3.8 ± 0.4 0.5 Max 1.27 2.54 Ordering Information Part Name Quantity Shipping Container 2SJ386TZ-E 2500 pcs Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.2.00 Sep 07, 2005 page 5 of 5 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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