RENESAS 2SK2980

2SK2980
Silicon N Channel MOS FET
High Speed Power Switching
REJ03G1061-0400
(Previous: ADE-208-571B)
Rev.4.00
Sep 07, 2005
Features
• Low on-resistance
RDS(on) = 0.2 Ω typ. (VGS = 4 V, ID = 500 mA)
• 2.5 V gate drive devices.
• Small package (MPAK)
Outline
RENESAS Package code: PLSP0003ZB-A
(Package name: MPAK)
D
3
1
G
1. Source
2. Gate
3. Drain
2
S
Note:
Marking is “ZZ–”
Rev.4.00 Sep 07, 2005 page 1 of 6
2SK2980
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Symbol
VDSS
VGSS
Ratings
30
+12
–10
1.0
4
0.8
150
–55 to +150
Drain current
ID
Drain peak current
ID(pulse)Note1
Channel dissipation
Pch Note2
Channel temperature
Tch
Storage temperature
Tstg
Notes: 1. PW ≤ 10µs, duty cycle ≤ 1 %
2. Value at when using alumina ceramic board (12.5 x 20 x 0.7 mm)
Unit
V
V
V
A
A
W
°C
°C
Electrical Characteristics
(Ta = 25°C)
Item
Drain to source breakdown voltage
Gate to source breakdown voltage
Symbol
V(BR)DSS
V(BR)GSS
Min
30
+12
–10
Typ
—
—
—
Max
—
—
—
Unit
V
V
V
Zero gate voltage drain current
Gate to source leak current
Gate to source cutoff voltage
IDSS
IGSS
VGS(off)
Static drain to source on state
resistance
RDS(on)
—
—
0.5
—
—
—
—
0.2
1.0
±5.0
1.5
0.28
µA
µA
V
Ω
VDS = 30 V, VGS = 0
VGS = ±8 V, VDS = 0
ID = 10 µA, VDS = 5 V
ID = 500 mA, VGS = 4 V Note3
Static drain to source on state
resistance
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Note: 3. Pulse test
RDS(on)
—
0.3
0.5
Ω
ID = 500 mA, VGS = 2.5 V Note3
|yfs|
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
1.2
—
—
—
—
—
—
—
2.0
155
75
35
12
30
35
30
—
—
—
—
—
—
—
—
S
pF
pF
pF
ns
ns
ns
ns
ID = 500 mA, VDS = 10 V Note3
Rev.4.00 Sep 07, 2005 page 2 of 6
Test Conditions
ID = 100 µA, VGS = 0
IG = +100 µA, VDS = 0
IG = –100 µA, VDS = 0
VDS = 10 V, VGS = 0,
f = 1 MHz
VGS = 4 V, ID = 500 mA,
RL = 20 Ω
2SK2980
Main Characteristics
Maximum Safe Operation Area
Power vs. Temperature Derating
100
Test condition :
When using alumina ceramic board
(12.5 x 20 x 0.7 mm)
1.2
0.8
0.4
0
50
100
150
30
Drain Current ID (A)
Channel Dissipation Pch (W)
1.6
200
10 µs 100 µs
3
1
m
s
=
1
(1 0 m
DC
0.3
sh s
Op
ot
)
Operation
in
e
0.1
ra
tio
this area is
n
limited by RDS(on)
0.03
Ta = 25°C
0.01
3
0.1 0.3
1
10 30
PW
1
Drain to Source Voltage VDS (V)
Typical Output Characteristics
Typical Transfer Characteristics
1.0
4V
2.5 V
Drain Current ID (A)
Pulse Test
0.8
2V
0.6
1.8 V
0.4
0.2
0.8
25°C
75°C
0.6
Tc = –25°C
0.4
0.2
VDS = 10 V
Pulse Test
VGS = 1.5 V
2
4
6
8
1
2
3
4
Drain to Source Voltage VDS (V)
Gate to Source Voltage VGS (V)
Drain to Source Saturation Voltage
vs. Gate to Source Voltage
Static Drain to Source on State
Resistance vs. Drain Current
0.5
Pulse Test
0.4
0.3
0.2
ID = 1 A
0.5 A
0.1
0.2 A
0
0
10
2
4
6
8
10
Gate to Source Voltage VGS (V)
Rev.4.00 Sep 07, 2005 page 3 of 6
Static Drain to Source on State Resistance
RDS (on) (Ω)
Drain to Source Saturation Voltage
VDS (on) (V)
0
100
Ambient Temperature Ta (°C)
1.0
Drain Current ID (A)
10
5
2
Pulse Test
1
0.5
VGS = 2.5 V
0.2
4V
0.1
0.05
0.1
0.2
0.5
1
2
Drain Current ID (A)
5
Static Drain to Source on State Resistance
vs. Temperature
0.5
ID = 0.1 A, 0.2 A, 0.5 A
0.4
VGS = 2.5 V
0.3
0.1 A, 0.2 A, 0.5 A
4V
0.1
Pulse Test
0
40
80
Case Temperature
120
Tc
160
2
Tc = –25°C
1
25°C
0.5
75°C
0.2
0.1
0.05
0.01 0.02
(°C)
Capacitance C (pF)
Drain to Source Voltage VDS (V)
VGS = 0
f = 1 MHz
Coss
100
Ciss
50
Crss
20
10
5
0
10
20
30
40
50
16
30
10
Reverse Drain Current IDR (A)
Switching Time t (ns)
tr
td(on)
10
5
VGS = 4 V, VDD = 10 V
PW = 2 µs, duty < 1 %
0.2
0.5
1
Drain Current
Rev.4.00 Sep 07, 2005 page 4 of 6
2
ID (A)
4
VDD = 20 V
10 V
5V
2
4
6
8
0
10
Qg (nc)
Reverse Drain Current vs.
Source to Drain Voltage
tf
1
0.1
8
VGS
Gate Charge
100
2
12
V DD = 5 V
10 V
20 V
VDS
20
(V)
200
20
20
40
Switching Characteristics
td(off)
1
0.5
ID = 1 A
0
50
Drain to Source Voltage VDS
50
0.2
Dynamic Input Characteristics
1000
200
0.05 0.1
Drain Current ID (A)
Typical Capacitance vs.
Drain to Source Voltage
500
VDS = 10 V
Pulse Test
5
10
1.0
0.8
0.6
VGS = 0
5V
0.4
0.2
Pulse Test
0
0.4
0.8
1.2
Source to Drain Voltage
1.6
2.0
VSD (V)
VGS (V)
0
–40
5
Gate to Source Voltage
0.2
Forward Transfer Admittance vs.
Drain Current
Forward Transfer Admittance |yfs| (S)
Static Drain to Source on State Resistance
RDS(on) (Ω)
2SK2980
2SK2980
Switching Time Test Circuit
Waveform
90%
Vout
Monitor
Vin Monitor
D.U.T.
RL
Vin
Vout
Vin
4V
50 Ω
VDD
= 10 V
10%
10%
90%
td(on)
Rev.4.00 Sep 07, 2005 page 5 of 6
10%
tr
90%
td(off)
tf
2SK2980
Package Dimensions
JEITA Package Code
RENESAS Code
Package Name
MPAK(T) / MPAK(T)V,
MPAK / MPAKV
PLSP0003ZB-A
SC-59A
D
MASS[Typ.]
0.011g
A
Q
e
E
HE
L
A
c
LP
L1
Reference
Symbol
A3
A
x M S
b
A
e
A2
A
e1
A1
S
b
b1
c1
I1
c
b2
A-A Section
Pattern of terminal position areas
A
A1
A2
A3
b
b1
c
c1
D
E
e
HE
L
L1
LP
x
b2
e1
I1
Q
Dimension in Millimeters
Min
1.0
0
1.0
0.35
0.1
2.7
1.35
2.2
0.35
0.15
0.25
Nom
1.1
0.25
0.42
0.4
0.13
0.11
1.5
0.95
2.8
Max
1.3
0.1
1.2
0.5
0.15
3.1
1.65
3.0
0.75
0.55
0.65
0.05
0.55
1.95
1.05
0.3
Ordering Information
Part Name
2SK2980ZZ-TL-E
2SK2980ZZ-TR-E
Quantity
3000 pcs
3000 pcs
Shipping Container
Taping
Taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
Rev.4.00 Sep 07, 2005 page 6 of 6
Sales Strategic Planning Div.
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Colophon .3.0