2SJ317 Silicon P Channel MOS FET REJ03G0857-0200 (Previous: ADE-208-1191) Rev.2.00 Sep 07, 2005 Description High speed power switching Low voltage operation Features • Very low on-resistance • High speed switching • Suitable for camera or VTR motor drive circuit, power switch, solenoid drive and etc. Outline RENESAS Package code: PLZZ0004CA-A (Package name: UPAK R ) D 3 2 1 1. Gate 2. Drain 3. Source 4. Drain G 4 S Note: Marking is “NY”. *UPAK is a trademark of Renesas Technology Corp. Rev.2.00 Sep 07, 2005 page 1 of 6 2SJ317 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Symbol VDSS Value –12 Unit V VGSS ID –7 ±2 V A ±4 2 A A 1 150 W °C –55 to +150 °C ID (pulse) IDR Note 1 Note 2 Channel dissipation Channel temperature Pch Tch Storage temperature Tstg Notes: 1. PW ≤ 100 µs, duty cycle ≤ 10% 2. Value on the alumina ceramic board (12.5 × 20 × 0.7 mm) Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Symbol V (BR) DSS Min –12 Typ — Max — Unit V Gate to source breakdown voltage Gate to source leak current V (BR) GSS IGSS ±7 — — — — ±5 V µA IG = ±10 µA, VDS = 0 VGS = ±6.5 V, VDS = 0 IDSS VGS (off) — –0.4 — — –1 –1.4 µA V VDS = –8 V, VGS = 0 ID = –100 µA, VDS = –5 V RDS (on) 1 RDS (on) 2 — — 0.4 0.28 0.7 0.35 Ω Ω ID = –0.5 A, VGS = –2.2 V Note 3 ID = –1 A, VGS = –4 V Forward transfer admittance Input capacitance |yfs| Ciss 1.0 — 2.3 63 — — S pF Output capacitance Reverse transfer capacitance Coss Crss — — 180 23 — — pF pF ID = –1 A, VDS = –5 V VDS = –5 V VGS = 0 f = 1 MHz Turn-on delay time Turn-off delay time td (on) td (off) — — 500 2860 — — ns ns ID = –0.2 A Vin = –4 V, RL = 51 Ω Zero gate voltage drain current Gate to source cutoff voltage Static drain to source on state resistance Note: 3. Pulse test Rev.2.00 Sep 07, 2005 page 2 of 6 Test Conditions ID = –1 mA, VGS = 0 Note 3 Note 3 2SJ317 Main Characteristics Maximum Safe Operation Area Power vs. Temperature Derating –10 ID (A) PW = 1 ms (1 shot) 1.0 0 50 100 150 –0.3 –0.1 –0.03 Ta = 25°C –0.01 –0.1 –0.3 –1 200 Ambient Temperature Ta (°C) –10 –4 V –3 V VDS (V) –2.5 V –2 V Tc = –25°C ID (A) Pulse Test –4 –3 –4 75°C 25°C –3 –2 –1.5 V –1 –2 –1 VDS = –5 V Pulse Test VGS = –1 V 0 –2 –4 –6 –8 Drain to Source Voltage 0 –10 10 Tc = –25°C 5 2 25°C 1 75°C 0.5 VDS = –5 V Pulse Test 0.2 –0.1 –0.2 –0.5 –1 –2 Drain Current ID (A) Rev.2.00 Sep 07, 2005 page 3 of 6 –5 –10 –1 –2 –3 –4 –5 VGS (V) Drain to Source on State Resistance vs. Drain Current Drain to Source on State Resistance RDS (on) (Ω) 20 0 Gate to Source Voltage VDS (V) Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) –100 Typical Foward Transfer Characteristics Drain Current –5 V 0 –30 –5 –5 ID (A) –3 Drain to Source Voltage Typical Output Characteristics Drain Current Operation in this area is limited by RDS (on) ) °C 25 0 –1 c= (T 0.5 –3 n tio ra pe O Drain Current 1.5 DC Channel Dissipation Pch (W) (on the alumina ceramic board) 2.0 10 Pulse Test 5 2 1 0.5 –3 V VGS = –2 V –4 V 0.2 0.1 –0.1 –0.2 –0.5 –1 Drain Current –2 ID (A) –5 –10 Drain to Source Saturation Voltage vs. Gate to Source Voltage Static Drain to Source on State Resistance vs. Temperature Static Drain to Source on State Resistance RDS (on) (Ω) Drain to Source Saturation Voltage VDS (on) (V) 2SJ317 –0.5 Pulse Test –0.4 ID = –1 A –0.3 –0.2 –0.5 A –0.1 A –0.1 –0.2 A 0 0 –1 –2 –3 Gate to Source Voltage –4 –5 1.0 Pulse Test 0.8 ID = –2 A 0.6 VGS = –2.5 V 0.2 0 –25 0 25 50 75 Case Temperature 100 Tc (°C) Switching Time vs. Drain Current 2000 tf 1000 Switching Time t (ns) Reverse Recovery Time trr (ns) –2 A –1 A, 0.5 A –4 V VGS (V) 2000 500 200 100 50 di / dt = 10 A / µs VGS = 0 20 –0.1 –0.2 –0.5 –1 –2 Reverse Drain Current –5 1000 50 –0.05 –0.1 –0.2 –10 –10 –4 –2 –5 VDS 0 0 4 Gate Charge Rev.2.00 Sep 07, 2005 page 4 of 6 6 8 Qg (nc) –1 –2 –5 ID (A) 10 VGS (V) 1000 VGS = 0 f = 1 MHz 500 Capacitance C (pF) –6 Gate to Source Voltage –8 VGS 2 –0.5 Typical Capacitance vs. Drain to Source Voltage –10 0 td(on) Drain Current VDD = –10 V ID = –2 A –20 Pulse test –15 tr VGS = –4 V 200 VDD = –10 V PW = 5 µs Duty cycle ≤ 1 % 100 IDR (A) –25 td(off) 500 Dynamic Input Characteristics VDS (V) –0.5 A 0.4 Reverse Recovery Time vs. Recovery Time Drain to Source Voltage –1 A Coss 200 100 Ciss 50 Crss 20 10 –0.1 –0.2 –0.5 –1 –2 –5 –10 Drain to Source Voltage VDS (V) 2SJ317 Reverse Drain Current vs. Source to Drain Voltage Reverse Drain Current IDR (A) –4 Pulse Test VGS = –4 V –3 –2.5 V –2 –1 VGS = 0 0 0 –0.5 –1.0 Source to Drain Voltage Rev.2.00 Sep 07, 2005 page 5 of 6 –1.5 VSD –2.0 (V) 2SJ317 Package Dimensions RENESAS Code Package Name MASS[Typ.] PLZZ0004CA-A UPAK / UPAKV 0.050g 1.5 1.5 3.0 1.5 ± 0.1 0.44 Max 2.5 ± 0.1 4.25 Max (1.5) 0.44 Max (0.2) 0.53 Max 0.48 Max 0.8 Min φ1 0.4 4.5 ± 0.1 1.8 Max Unit: mm (2.5) SC-62 (0.4) JEITA Package Code Ordering Information Part Name 2SJ317NYTL-E 2SJ317NYTR-E Quantity 1000 pcs 1000 pcs Shipping Container Taping Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.2.00 Sep 07, 2005 page 6 of 6 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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