SONY CXD2303AQ

CXD2303AQ
8-bit 3-channel 50 MSPS Video A/D Converter with clamp function
Description
The CXD2303AQ is an 8-bit 3-channel CMOS A/D
converter for video with synchronizing digital clamp
function. The adoption of 2 step-parallel method
achieves low power consumption and a maximum
conversion rates of 50 MSPS.
Features
• Resolution : 8 bit±1/2 LSB (DL)
• Maximum sampling frequency : 50 MSPS
• Low power consumption : 400 mW (at 50 MSPS
Typ.) (Reference current excluded)
• Synchronizing digital clamp function
• Clamp ON/OFF function
• Reference voltage self-bias circuit
• Input CMOS/TTL compatible
• 3-state TTL compatible output
• Single 5 V power supply or dual 5 V/3.3 V power
supplies
• Low input capacitance 15 pF
• Reference impedance : 370 Ω (Typ.)
• Different digital output multiplex format:
– 4 : 4 : 4 format
– 4 : 2 : 2 format
– 4 : 1 : 1 format
Applications
Wide range of applications that require high-speed
A/D conversion such as monitor, TV and VCR.
Structure
Silicon gate CMOS IC
80 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
AVDD, DVDD
7
V
• Input voltage
Vin
Digital output pins
DVDD+0.5 to DVSS–0.5 V
Other pins
AVDD+0.5 to AVSS–0.5 V
• Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage
AVDD, AVSS
4.75 to 5.25
V
DVDD, DVSS
3.0 to 5.5
V
| DVSS–AVSS |
0 to 100
mV
• Reference input voltage
VARB, VBRB, VCRB
0 or more
V
VART, VBRT, VCRT
2.7 or less
V
• Analog input
AIN, BIN, CIN 1.7 Vp-p or more
• Clock pulse width
Tpw1, Tpw0
9 ns (min.) to 1.1 µs (max.)
• Operating ambient temperature
Topr
–20 to +85
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E98220A89
CXD2303AQ
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
DVDD
DVDD
DVDD
DVDD
DVSS
DVSS
DVSS
Block Diagram
30
35
41
42
62
68
22
23
1
2
11
12
71
72
DVSS
13
A0 (LSB)
20
A7 (MSB)
44
XAOE
3
B0 (LSB)
10
B7 (MSB)
45
XBOE
73
C0 (LSB)
80
C7 (MSB)
46
XCOE
ARTS 32
8
ART 31
A-ch
8-bit ADC
AIN 28
ARB
26
Digital
Clamp
Circuit
9
ARBS 25
9-bit
DAC
AIO 29
BRTS 33
8
BRT 34
BIN 37
BRB
Data
Selector
+
Latch
B-ch
8-bit ADC
39
Digital
Clamp
Circuit
9
BRBS 40
9-bit
DAC
BIO 36
CRTS 70
69
8
C-ch
8-bit ADC
CIN 66
AVSS
38
Clamp Control
60
61
65
52
58
53
51
54
57
59
43
—2—
21
TGR
47
CTL0
49
CTL2
50
SY
Decoder
TEST
27
TEST
AVSS
REF3
24
SEL
AVSS
9-bit
DAC
CLP
67
CLE
CIO
Digital
Clamp
Circuit
9
CLK
63
AVSS
CRBS
AVSS
64
AVSS
CRB
REF0
CRT
AVDD
TEST
XAOE
XCOE
XBOE
CTL1
CTL0
SY
CTL2
CLK
SEL
CLP
REF0
REF1
REF3
CLE
TEST
AVSS
AVSS
AVDD
CRBS
CRB
REF2
C7 80
8
7
6
5
4
3
2
1
DVDD
C6 79
B0
DVDD
C5 78
B2
B1
C4 77
B4
B3
C3 76
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
B6
C2 75
B5
C1 74
B7
C0 73
DVSS
DVSS 72
DVSS
DVSS
A1
40 BRBS
25 ARBS
26 ARB
27 AVSS
28 AIN
29 AIO
30 AVDD
31 ART
32 ARTS
33 BRTS
34 BRT
35 AVDD
A0
71
A3
CRTS 70
A2
36 BIO
A5
37 BIN
A4
CRT 69
A7
AVDD 68
A6
38 AVSS
TGR
39 BRB
DVDD
CIN 66
AVSS
—3—
DVDD
CIO 67
AVSS 65
AVDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
CXD2303AQ
Pin Configuration
CXD2303AQ
Pin Description
Pin No.
Symbol
I/O
1, 2, 22, 23
DVDD
—
13 to 20
3 to 10
73 to 80
A0 to A7
B0 to B7
C0 to C7
Equivalent circuit
Description
Digital power supply.
+5 V or +3.3 V
DVDD
Digital output.
A0 (LSB) to A7 (MSB)
B0 (LSB) to B7 (MSB)
C0 (LSB) to C7 (MSB)
O
Trigger output.
21
TGR
See the Tables and Timing Chart
II described in the Output Format
section.
O
DVSS
11, 12, 71, 72
24, 27, 38,
60, 61, 65
25
40
63
26
39
64
31
34
69
32
33
70
DVSS
—
Digital ground.
AVSS
—
Analog ground.
ARBS
BRBS
CRBS
ARB
BRB
CRB
ART
BRT
CRT
ARTS
BRTS
CRTS
Shorting these pins to AVSS
generates voltage of about 0.5 V at
the ARB, BRB and CRB pins.
AVDD
—
32
33
—
26
70
39
RT
31
—
Reference voltage (bottom).
64
RREF
34
25
RB
69
40
63
—
AVSS
Reference voltage (top).
Shorting these pins to AVDD
generates voltage of about 2.5 V at
the ART, BRT and CRT pins.
AVDD
28
37
66
AIN
BIN
CIN
28
I
37
Analog input.
66
AVSS
—4—
CXD2303AQ
Pin No.
Symbol
I/O
Equivalent circuit
Description
AVDD
29
36
67
AIO
BIO
CIO
29
O
about 200Ω
36
67
Analog output.
The digital clamp circuit comprises
a D/A converter whose outputs are
available on these pins.
AVSS
30, 35, 41,
42, 62, 68
AVDD
Analog +5 V power supply.
43
59
TEST
I
44
45
46
XAOE
XBOE
XCOE
I
47
48
49
CTL0
CTL1
CTL2
I
50
SY
I
AVDD
AVSS
—5—
Normally open.
Pull-down resistors are
incorporated.
Output enable input.
When these pins are Low, data is
output from the digital output pins.
When these pins are High, the
digital output pins are high
impedance.
The A, B and C channels can be
controlled separately.
Also, these pins are not
synchronized with the clock signal.
Pull-down resistors are
incorporated.
Determines the digital output
mode. See the Mode Tables and
Timing Charts.
Pull-down resistors are
incorporated.
Controls the digital output mode
switching timing. The mode is
switched by detecting the transition
point where this pin changes from
Low to High. See the Mode
Tables and Timing Charts for
details.
A pull-down resistor is
incorporated.
CXD2303AQ
Pin No.
51
Symbol
SEL
I/O
Equivalent circuit
Controls the CLP signal polarity.
When this pin is Low, CLP is High
active.
When this pin is High, CLP is Low
active.
This pin has a built-in pull-down
resistor.
I
52
CLK
I
53
CLP
I
AVDD
54
55
56
57
58
REF0
REF1
REF2
REF3
CLE
I
Description
AVSS
Clock input.
A pull-down resistor is
incorporated.
Clamp pulse input.
The polarity can be set to either
High or Low by setting SEL.
This pin has a built-in pull-down
resistor.
Determines the clamp circuit
reference data.
See the Mode Tables for the set
data.
These pins are not synchronized
with the clock input signal.
Pull-down resistors are
incorporated.
Clamp enable.
When this pin is Low, the clamp
circuit does not operate.
When this pin is High, the clamp
circuit operates.
A pull-down resistor is
incorporated.
I
—6—
CXD2303AQ
Digital output
The following table shows the relationship between analog input voltage and digital output code.
Input signal
voltage
VART, VBRT, VCRT
:
:
:
:
VARB, VBRB, VCRB
Digital output code
MSB
LSB
1 1 1 1 1 1 1 1
:
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
:
0 0 0 0 0 0 0 0
Step
0
:
127
128
:
255
Timing Chart I
tr
4ns
tf
4ns
3V
90%
Clock
input
1.3V
10%
0V
3V
Digital
input
2.2V
0.8V
0V
tH
Digital
output
tS
0.7VDD
0.3VDD
tpLH,
tpHL
Timing Chart I-1.
tr=4.5ns
XAOE
XBOE
XCOE
tf=4.5ns
3V
90%
input
1.3V
10%
tpLZ
0V
tpZL
VOH
Output 1
1.3V
10%
VOL (≠DVSS)
tpHZ
tpZH
VOH (≠DVDD)
90%
Output 2
1.3V
VOL
Timing Chart I-2.
—7—
Digital
output
Analog
input
Clock
input
1.3V
N–5
N
tsd
Tpw1 Tpw0
N–4
N+1
N–3
4.5CLK
N+2
N–2
N+3
N–1
N+4
N+1
N+6
Timing Chart I-3
N
N+5
N+2
N+7
N+3
N+8
N+5
N+10
N+6
N+11
: Analog signal sampling point
N+4
N+9
CXD2303AQ
—8—
CXD2303AQ
Electrical Characteristics
Analog characteristics
Item
(Fc=50 MSPS, AVDD=5 V, DVDD=3 to 5.5 V, VRB=0.5 V, VRT=2.5 V, Ta=25 °C)
Conditions
Symbol
Min.
Typ.
Max.
Unit
50
MSPS
AVDD=4.75 to 5.25 V
Conversion rate
Fc
Analog input band width
BW
Differential non-linearity error
Integral non-linearity error
ED
EL
EOT
EOB
DG
DP
tsd
Offset voltage (∗1)
Differential gain error
Differential phase error
Sampling delay
Clamp offset voltage
EOC
Ta=–20 to +85 °C
VIN=0.5 to 2.5 V
FIN=1 kHz triangular wave
Envelop
–1 dB
RIN=33 Ω
–3 dB
0.5
60
100
±0.3
±0.7
End point
Potential difference to ART, BRT, CRT
Potential difference to ARB, BRB, CRB
–50
0
Ref. Data=
“00010000”
Spurious free dynamic
range
Cross talk
SFDR
CT
mV
%
deg
ns
LSB
Ref. Data=
“10000000”
±1
0.5
SNR
LSB
±1
Full-scale input ratio (∗2)
Signal-to-noise ratio
±0.5
±1.5
–10
40
3
1.5
3
NTSC 40 IRE mod ramp,
Fc=14.3 MSPS
VIN=DC
CIN=10 µF
tpcw=2.75 µs
FC=14.3 MHz
FCLP=15.75 kHz
MHz
FIN=150 kHz
FIN=500 kHz
FIN=1 MHz
FIN=3 MHz
FIN=10 MHz
FIN=20 MHz
FIN=150 kHz
FIN=500 kHz
FIN=1 MHz
FIN=3 MHz
FIN=10 MHz
FIN=20 MHz
FIN=1 MHz sin wave
43
42
42
41
38
35
59
59
55
49
44
41
52
%
dB
dB
dB
(∗1) The offset voltage EOB is a potential difference between ARB, BRB, CRB and a point of position where the
voltage drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to
“00000001”. EOT is a potential difference between ART, BRT, CRT and a potential of point where the
voltage rises equivalent to 1/2 LSB of the voltage when the output data changes from “11111111” to
“11111110”.
(∗2) Full-scale input ratio =
(2 V+EOT–EOB) of each channel
Average of (2 V+EOT–EOB) of each channel
—9—
–1
×100 (%)
CXD2303AQ
DC characteristics
Item
Analog
Digital
Supply current
Analog
Digital
Reference current
Reference resistance
(RT to RB)
(Fc=50 MSPS, AVDD=5 V, DVDD=5 V or 3.3 V, VRB=0.5 V, VRT=2.5 V, Ta=25 °C)
Symbol
IAD+IDD
IAD
IDD
IAD+IDD
IAD
IDD
IREF
RREF
CAI2
CDIN
CAO
CDO
VIH
Digital input voltage
VIL
Digital input current
For every channel
260
370
480
0.50
0.54
0.58
XOE=0 V
RIN
CAI1
Output capacitance
4.1
IOH
VRT1–VRB1
Min.
DVDD=3.3 V
IIH
IIL
Self-bias
Input capacitance
NTSC ramp
DVDD=5 V
wave input
DVDD=3.3 V
CLE=Low
For every channel
Typ.
80
70
5
70
60
5
5.4
Shorts AV SS and ARBS, BRBS,
CRBS.
Shorts AV DD and ARTS, BRTS,
CRTS.
Fc=50 MHz
AIN, BIN, CIN
Fc=35 MHz
Fc=20 MHz
AIN, BIN, CIN,
VIN=1.5 V+0.07 Vrms
ARTS, ART, ARB, ABFS,
BRTS, BRT, BRB, BRBS,
CRTS, CRT, CRB, CRBS
Digital input pin
AIO, BIO, CIO
Digital output pin
AVDD=4.75 to 5.25 V
DVDD=3 to 5.5 V
Ta=–20 to +75 °C
VI=0 V to AVDD
Ta=–20 to +75 °C
VRB1
Analog input resistance
Conditions
DVDD=5 V
NTSC ramp
wave input
CLE=High
FCLP=15.75 kHz
Max.
100
90
10
90
80
10
7.7
Unit
Ω
mA
mA
V
1.80
1.92
2.04
13
16
30
kΩ
15
9
9
11
11
pF
pF
2.2
V
0.8
–40
240
µA
–2
VOH=DVDD–0.8 V
DVDD=5 V
IOL
Ta=–20 to 75 °C
VOL=0.4 V
IOH
XOE=0 V
VOH=DVDD–0.8 V
Digital output current
4
mA
–1.2
DVDD=3.3 V
IOL
IOZH
Ta=–20 to 75 °C
VOL=0.4 V
XOE=3 V
VOH=DVDD
–40
DVDD=3 to 5.5 V
IOZL
Ta=–20 to 75 °C
2.4
VOL=0 V
—10—
40
µA
CXD2303AQ
DC Characteristic (Continue)
Item
Symbol
VOH
Conditions
XOE=0 V
IOH=–2 mA
DVDD=5 V
Ta=–20 to 75 °C IOL=4 mA
VOL
Digital output voltage
VOH
XOE=0 V
IOH=–1.2 mA
DVDD=3.3 V
Ta=–20 to 75 °C IOL=2.4 mA
VOL
Timing
Min.
DVDD
–0.8
Typ.
Max.
Unit
0.4
V
DVDD
–0.8
0.4
(Fc=50 MSPS, AVDD=5 V, DVDD=5 V or 3.3 V, VRB=0.5 V, VRT=2.5 V, Ta=25 °C)
Item
Setup time
Hold time
Symbol
tpLH
tpHL
tpLH
tpHL
tpZH
tpZL
tpZH
tpZL
tpHZ
tpLZ
tpHZ
tpLZ
tS
tH
Pulse width
tH
Output data delay
Tri-state output
enable time
Tri-state output
disable time
Min.
Conditions
DVDD=5 V
CL=15 pF
XOE=0 V
4.5
DVDD=3.3 V
3.8
DVDD=5 V
RL=1 kΩ
CL=15 pF
XOE=3 V → 0 V DVDD=3.3 V
4.2
RL=1 kΩ
DVDD=5 V
CL=15 pF
XOE=0 V → 3 V DVDD=3.3 V
3.6
2.9
Max.
CLP
SY
ns
13.8
11.3
ns
12.8
9.5
ns
10.5
ns
ns
Cycle
Electrical Characteristics Measurement Circuit
Output data delay measurement circuit
Tri-state output measurement circuit
Measurement point
Measurement
point
To output pin
DVDD
RL
CL
To output pin
CL
Note) CL includes capacitance of probes.
—11—
Unit
11.0
3.5
4.5
2
1
CTL0 to 2, CLP, SY
CLK conversion
3.5
Typ.
8.5
7.4
10.0
6.7
7.1
8.0
8.4
7.2
6.8
6.3
6.8
6.0
RL
CXD2303AQ
Integral non-linearity error
Differential non-linearity error
Offset voltage
Analog input resistance measurement circuit
measurement
circuit
+V
+5V
2.5V
S2
AVDD, DVDD
S1 : ON IF A<B
S2 : ON IF B>A
ART, BRT, CRT
S1
A
AIN, BIN, CIN
–V
ARB, BRB, CRB
8
AIN
A
BIN
DUT
CXD2303AQ B
CIN
8
8
8
C
A<B
A>B
COMPARATOR
A8
B8
to
to
A1
B1
A0
B0
“0”
V
8
CLK
0.5V
BUFFER
AVSS, DVSS
“1”
DVM
8
CLK (50MHZ)
000···00
TO
111···10
CONTROLLER
Differential gain error
Differential phase error
measurement circuit
CX20202A-1
8
AIN
NTSC
SIGNAL
SOURCE
AMP
IRE
100
S.G.
(CW)
40 IRE
MODULATION
A
BIN
8
DUT
CXD2303AQ B
CIN
8
8
TTL
↓
ECL
8
C
VECTOR
SCOPE
620
CLK
2.5V
D.G
D.P.
–5.2V
BURST
0
–40
10-bit
D/A
0.5V
SYNC
FC
620
TTL
↓
ECL
–5.2V
Digital output current measurement circuit
+4.75V
+4.75V
AVDD, DVDD
2.5V
AVDD, DVDD
2.5V
ART, BRT, CRT
AIN, BIN, CIN
0.5V
ARB, BRB, CRB
AIN, BIN, CIN
IOL
Data
out
ART, BRT, CRT
A
0.5V
CLK
ARB, BRB, CRB
IOH
Data
out
A
CLK
VOL
OE
VOL
OE
AVSS, DVSS
AVSS, DVSS
—12—
CXD2303AQ
Cross talk measurement circuit
CXD2303AQ
SG
AIN
sine wave
An
AMP
8
FFT
Bn
BIN, CIN
8
Cn
SG
8
CLK
Note : This diagram shows the case where the channel A is measured.
The same as for measuring the channels B and C.
Description of Operation
1. Output Format
The CXD2303AQ can select six different types of output formats through a combination of the CTL0, CTL1
and CTL2 inputs as shown in the table below. Output is synchronized to the SY input signal transition from
Low to High.
Table 1. Setting values and output formats
Setting
CTL2 CTL1 CTL0
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
Mode
Output
Format
0
1
2
3
4
5
6
7
4:4:4
4 : 2 : 2 (8 fs)
4 : 2 : 2 (D2)
4 : 2 : 2 (Special)
4:1:1
4 : 1 : 1 (Special)
Simple boundary scan 1
Simple boundary scan 2
Note that when the SY input is open or Low level, the output format is mode #0 (4 : 4 : 4).
However, when the SY input signal temporarily goes to Low level for the mode switching, the mode
changes as shown in Timing Chart II. When digital data is being output in the mode n output format, if the
SY input signal changes from High level to Low level, the digital data continues to be output in the mode n
output format for the following two clocks. The output format for the digital data output from the third to fifth
clocks is not established, so its use is prohibited. If the SY input signal remains Low level, the digital data
is output in the mode #0 output format from the sixth clock. After the SY input signal changes from Low
level to High level, the digital data is output in the mode m output format from the sixth clock. At this time,
the data output at the sixth clock is the data A/D converted from the analog input signal that was sampled
at the falling edge of the clock input signal immediately after the SY input signal changes from Low level to
High level.
The output format control input signals CTL2, CTL1 and CTL0 are fetched only in sync with the rising edge
of the clock input signal after the SY input signal has risen.
—13—
1.3V
Digital
output
CTL2 to CTL0
SY
Clock
input
N–10
N–5
Mode n
N–9
2CLK
Mode n
N–4
N–8
N–3
5CLK
N–2
—14—
N
N–4
N+1
Timing Chart II
Prohibited
N–1
N–3
5CLK
N+2
Mode #0
N–2
Mode m
N+3
N–1
N+4
N
N+5
Mode m
N+1
N+6
N+2
CXD2303AQ
CXD2303AQ
Mode #0
4:4:4
Bit
A73
Sampling timing (∗)
ADC channel
ADC channel
A
B
C
Output
A7
A6
A5
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
C7
C6
C5
C4
C3
C2
C1
C0
TGR
Data
A70
A60
A50
A40
A30
A20
A10
A00
B70
B60
B50
B40
B30
B20
B10
B00
C70
C60
C50
C40
C30
C20
C10
C00
Low
A71
A61
A51
A41
A31
A21
A11
A01
B71
B61
B51
B41
B31
B21
B11
B01
C71
C61
C51
C41
C31
C21
C11
C01
A72
A62
A52
A42
A32
A22
A12
A02
B72
B62
B52
B42
B32
B22
B12
B02
C72
C62
C52
C42
C32
C22
C12
C02
Note (∗) : See Timing Chart II.
—15—
A73
A63
A53
A43
A33
A23
A13
A03
B73
B63
B53
B43
B33
B23
B13
B03
C73
C63
C53
C43
C33
C23
C13
C03
A74
A64
A54
A44
A34
A24
A14
A04
B74
B64
B54
B44
B34
B24
B14
B04
C74
C64
C54
C44
C34
C24
C14
C04
A75
A65
A55
A45
A35
A25
A15
A05
B75
B65
B55
B45
B35
B25
B15
B05
C75
C65
C55
C45
C35
C25
C15
C05
A76
A66
A56
A46
A36
A26
A16
A06
B76
B66
B56
B46
B36
B26
B16
B06
C76
C66
C56
C46
C36
C26
C16
C06
A77
A67
A57
A47
A37
A27
A17
A07
B77
B67
B57
B47
B37
B27
B17
B07
C77
C67
C57
C47
C37
C27
C17
C07
CXD2303AQ
Mode #1
4 : 2 : 2 (8 fs)
Bit
A73
Sampling timing (∗)
ADC channel
ADC channel
A
B
C
Output
A7
A6
A5
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
C7
C6
C5
C4
C3
C2
C1
C0
TGR
Data
A70
A60
A50
A40
A30
A20
A10
A00
B70
B60
B50
B40
B30
B20
B10
B00
B70
B60
B50
B40
B30
B20
B10
B00
High
A70
A60
A50
A40
A30
A20
A10
A00
B70
B60
B50
B40
B30
B20
B10
B00
A70
A60
A50
A40
A30
A20
A10
A00
Low
A72
A62
A52
A42
A32
A22
A12
A02
C70
C60
C50
C40
C30
C20
C10
C00
C70
C60
C50
C40
C30
C20
C10
C00
Note (∗) : See Timing Chart II.
—16—
A72
A62
A52
A42
A32
A22
A12
A02
C70
C60
C50
C40
C30
C20
C10
C00
A72
A62
A52
A42
A32
A22
A12
A02
A74
A64
A54
A44
A34
A24
A14
A04
B74
B64
B54
B44
B34
B24
B14
B04
B74
B64
B54
B44
B34
B24
B14
B04
High
A74
A64
A54
A44
A34
A24
A14
A04
B74
B64
B54
B44
B34
B24
B14
B04
A74
A64
A54
A44
A34
A24
A14
A04
Low
A76
A66
A56
A46
A36
A26
A16
A06
C74
C64
C54
C44
C34
C24
C14
C04
C74
C64
C54
C44
C34
C24
C14
C04
A76
A66
A56
A46
A36
A26
A16
A06
C74
C64
C54
C44
C34
C24
C14
C04
A76
A66
A56
A46
A36
A26
A16
A06
CXD2303AQ
Mode #2
4 : 2 : 2 (D2)
Bit
A73
Sampling timing (∗)
ADC channel
ADC channel
A
B
C
Output
A7
A6
A5
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
C7
C6
C5
C4
C3
C2
C1
C0
TGR
Data
A70
A60
A50
A40
A30
A20
A10
A00
B70
B60
B50
B40
B30
B20
B10
B00
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
High
A71
A61
A51
A41
A31
A21
A11
A01
C70
C60
C50
C40
C30
C20
C10
C00
A72
A62
A52
A42
A32
A22
A12
A02
B72
B62
B52
B42
B32
B22
B12
B02
A73
A63
A53
A43
A33
A23
A13
A03
C72
C62
C52
C42
C32
C22
C12
C02
A74
A64
A54
A44
A34
A24
A14
A04
B74
B64
B54
B44
B34
B24
B14
B04
A75
A65
A55
A45
A35
A25
A15
A05
C74
C64
C54
C44
C34
C24
C14
C04
A76
A66
A56
A46
A36
A26
A16
A06
B76
B66
B56
B46
B36
B26
B16
B06
A77
A67
A57
A47
A37
A27
A17
A07
C76
C66
C56
C46
C36
C26
C16
C06
Low
High
Low
High
Low
High
Low
HiZ : High impedance
Note (∗) : See Timing Chart II.
—17—
CXD2303AQ
Mode #3
4 : 2 : 2 (Special)
Bit
A73
Sampling timing (∗)
ADC channel
ADC channel
A
B
C
Output
A7
A6
A5
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
C7
C6
C5
C4
C3
C2
C1
C0
TGR
Data
A70
A60
A50
A40
A30
A20
A10
A00
B70
B60
B50
B40
B30
B20
B10
B00
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
High
A71
A61
A51
A41
A31
A21
A11
A01
C71
C61
C51
C41
C31
C21
C11
C01
A72
A62
A52
A42
A32
A22
A12
A02
B72
B62
B52
B42
B32
B22
B12
B02
A73
A63
A53
A43
A33
A23
A13
A03
C73
C63
C53
C43
C33
C23
C13
C03
A74
A64
A54
A44
A34
A24
A14
A04
B74
B64
B54
B44
B34
B24
B14
B04
A75
A65
A55
A45
A35
A25
A15
A05
C75
C65
C55
C45
C35
C25
C15
C05
A76
A66
A56
A46
A36
A26
A16
A06
B76
B66
B56
B46
B36
B26
B16
B06
A77
A67
A57
A47
A37
A27
A17
A07
C77
C67
C57
C47
C37
C27
C17
C07
Low
High
Low
High
Low
High
Low
HiZ : High impedance
Note (∗) : See Timing Chart II.
—18—
CXD2303AQ
Mode #4
4:1:1
Bit
A73
Sampling timing (∗)
ADC channel
ADC channel
A
B
C
Output
A7
A6
A5
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
C7
C6
C5
C4
C3
C2
C1
C0
TGR
Data
A70
A60
A50
A40
A30
A20
A10
A00
B70
B60
C70
C60
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
High
A71
A61
A51
A41
A31
A21
A11
A01
B50
B40
C50
C40
A72
A62
A52
A42
A32
A22
A12
A02
B30
B20
C30
C20
A73
A63
A53
A43
A33
A23
A13
A03
B10
B00
C10
C00
Low
HiZ : High impedance
Note (∗) : See Timing Chart II.
—19—
A74
A64
A54
A44
A34
A24
A14
A04
B74
B64
C74
C64
A75
A65
A55
A45
A35
A25
A15
A05
B54
B44
C54
C44
High
Low
A76
A66
A56
A46
A36
A26
A16
A06
B34
B24
C34
C24
A77
A67
A57
A47
A37
A27
A17
A07
B14
B04
C14
C04
CXD2303AQ
Mode #5
4 : 1 : 1 (Special)
Bit
A73
Sampling timing (∗)
ADC channel
ADC channel
A
B
C
Output
A7
A6
A5
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
C7
C6
C5
C4
C3
C2
C1
C0
TGR
Data
A70
A60
A50
A40
A30
A20
A10
A00
B30
B20
B10
B00
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
High
A71
A61
A51
A41
A31
A21
A11
A01
B70
B60
B50
B40
A72
A62
A52
A42
A32
A22
A12
A02
C32
C22
C12
C02
A73
A63
A53
A43
A33
A23
A13
A03
C72
C62
C52
C42
Low
HiZ : High impedance
Note (∗) : See Timing Chart II.
—20—
A74
A64
A54
A44
A34
A24
A14
A04
B34
B24
B14
B04
A75
A65
A55
A45
A35
A25
A15
A05
B74
B64
B54
B44
High
Low
A76
A66
A56
A46
A36
A26
A16
A06
C36
C26
C16
C06
A77
A67
A57
A47
A37
A27
A17
A07
C76
C66
C56
C46
CXD2303AQ
Mode #6, 7 simple boundary scan 1 and 2
The CXD2303AQ has a simple boundary scan function.
Table 2. Simple boundary scan
Bits
A7
A6
A5
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
C7
C6
C5
C4
C3
C2
C1
C0
Output data
MODE #6
MODE #7
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
Note : CLK and SY must be set.
2. Clamp Function
The following two points should be noted when using the digital clamp circuit.
-The clamp pulse must be supplied externally.
-The clamp circuit is not designed for V cycle clamping.
16 different reference levels can be selected for the digital clamp circuit through a combination of the REF0,
REF1, REF2 and REF3 inputs as shown in the table below. Note that the REF0, REF1, REF2 and REF3
input signals are fetched asynchronously with the clock input signal.
Table 3. Setting values and reference levels
Setting
REF3
REF2
REF1
REF0
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Reference level
Mode
Channel A
Channels B and C
Decimal
Binary
Decimal
Binary
0
16
00010000
128
10000000
1
32
00100000
128
10000000
2
48
00110000
128
10000000
3
64
01000000
128
10000000
4
1
00000001
1
00000001
5
16
00010000
16
00010000
6
32
00100000
32
00100000
7
48
00110000
48
00110000
8
239
11101111
127
01111111
9
223
11011111
127
01111111
A
207
11001111
127
01111111
B
191
10111111
127
01111111
C
254
11111110
254
11111110
D
239
11101111
239
11101111
E
223
11011111
223
11011111
F
207
11001111
207
11001111
—21—
CXD2303AQ
The digital clamp circuit operates in the way the average value of the A/D-converted analog input signal data
sampled during the 32 clock cycles after the clamp pulse is input and the reference data set by REF0 to REF3
are compared, and the result difference becomes smaller (See Timing Chart III). Therefore, take notice that
when there is the fixed noise and others during the 32 cycles of the clock signal, the digital clamp circuit deals
with the noise portion as the signal and it comes to the stable state still including the error. Photos 1 and 2
show the clamp circuit responses for the Application Circuit 1.
Photo 2 shows that inputting the clamp pulse during the vertical hold has no effect on the input signal.
2CLK (min.)
CLP
CLK
AAAAAAAA
AAAAAAAA
AAAAAAAA
32CLK
Noise
Input
This input level is desired to be clamped.
Timing III (When SEL=low)
Photo 1. Response waveform of clamp circuit
(When FCLK=50 MSPS, clamp pulse is NTSC SYNC
and reference data is 128)
Photo 2. Response waveform of clamp circuit
(FCLK=50 MSPS, clamp pulse is NTSC SYNC and
reference data is 128)
Upper: Analog input pin waveform
(H: 5 ms/div., V: 500 mV/div.)
Lower: Analog input signal waveform
(H: 5 ms/div., V: 2 V/div.)
Upper: Analog input pin waveform
(H: 200 µs/div., V: 5 V/div.)
Lower: Vertical hold pulse
(H: 200 µs/div., V: 500 mV/div.)
—22—
CXD2303AQ
RBS
RB
Reference
Supply
RTS
RT
Lower
Sampling
Comparator
(4bits)
Lower
Encoder
(4bits)
Upper
Data
Latch
Analog
in
Data0
(LSB)
Data1
Data2
Data3
Lower
Sampling
Comparator
(4bits)
Lower
Encoder
(4bits)
Upper
Sampling
Comparator
(4bits)
Upper
Encoder
(4bits)
Data4
External
clock
Clock
Generator
Fig. 1. 8-bit ADC block diagram
—23—
Upper
Data
Latch
Data5
Data6
Data7
(MSB)
CXD2303AQ
Vi (1)
Vi (2)
Vi (3)
Vi (4)
Analog input
External clock
Upper comparators block
(1)
(2)
S (1)
Data0 to Data7
(4)
S (3)
H (1)
C (3)
C (1)
C (0)
RV (3)
S (3)
H (3)
C (3)
LD (1)
S (2)
H (2)
LD (–1)
Data (–2)
C (4)
MD (3)
RV (2)
LD (–1)
H (0)
S (4)
MD (2)
RV (1)
S (1)
Lower data A
Lower data B
C (2)
MD (1)
RV (0)
Lower reference voltage
Lower comparators B block
S (2)
MD (0)
Upper data
Lower comparators A block
C (1)
(3)
C (2)
LD (0)
Data (–1)
S (4)
H (4)
LD (2)
Data (0)
Data (1)
Timing Chart IV
3. 8-bit ADC Operation (See Fig.1 and Timing Chart IV)
1) The CXD2303AQ includes 3 channels of the 8-bit A/D converter. This converter has the 2-step parallel
system, composed of a 4-bit upper comparator and two 4-bit lower comparator blocks. The reference
voltage that is equal to the voltage between RT-RB/16 is constantly applied to the upper 4-bit comparator
block. Voltage corresponded to the upper data is fed to the lower 4-bit comparator block through the
reference supply . RTS and RBS pins serve for the self- generation of RT (Reference voltage top) and RB
(Reference voltage bottom), and they are also used as the sense pins as shown in the Application Circuit 3.
—24—
CXD2303AQ
2) This IC uses an offset cancel type comparator that operates synchronously with an external clock. It
features the following operating modes which are respectively indicated on the Timing Chart IV with S, H, C
symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode.
3) The operation of respective parts is as indicated in the Timing Chart IV. For instance the input voltage Vi
(1) is sampled at the falling edge of the external clock (1) by means of the upper comparator bock and the
lower comparator A block.
The upper comparator block establishes comparison data MD (1) at the rising edge of the external clock
(2). Simultaneously the reference supply generates the lower reference voltage RV (1) corresponded to the
upper results. The lower comparator A block establishes comparison data LD (1) at the rising edge of the
external clock (3). MD (1) and LD (1) are combined and output as Out (1) at the rising edge of the external
clock (4). Accordingly, there is a 2.5 clock delay from the analog input sampling point to the A/D converter
digital data output.
Note that there is a 4.5 clock delay from the analog input sampling point to the digital data output because
the output data selector circuit is located at the stage after the A/D converter circuit. (See the item 5 of
Notes on Operation)
Notes on Operation
1. Power supply and ground
To reduce the effects of noise, separate the analog and digital systems around the device. Bypass both the
digital and analog power supply pins to the respective grounds using ceramic capacitors of about 0.1 µF set
as close to the pin as possible.
2. Analog input
Compared with flash type A/D converters, the input capacitance of the analog input is rather small.
However, driving must be performed with an amplifier featuring sufficient bands and drive capability. When
driving with an amplifier of low output impedance, parasitic oscillation may occur. This can be prevented by
inserting resistance of about 33 Ω in series between the amplifier output and A/D input. When the input
signals of Pins 28, 37 and 66 are monitored, the kickback noise of the clock can be found. However, this
has no effect on the A/D conversion characteristics.
3. Clock input
The clock line wiring should be as short as possible and should be separated from other circuits to avoid
any interference with other signals.
4. Reference input
Voltages ART to ARB, BRT to BRB and CRT to CRB supports dynamic range of the analog input. Stable
characteristics can be obtained by bypassing these pins to GND using capacitors of about 0.1 µF. The selfbias function that generates VRT=about 2.5 V and VRB=about 0.6 V is activated by shorting ARTS, BRTS
and CRTS to AVDD and ARBS, BRBS and CRBS to AVSS, respectively.
5. Timing
Analog input is sampled at the falling edge of CLK and output as digital data synchronized with a delay of
4.5 clocks at its rising edge (see Timing Chart I-3 ). The delay from the clock rising edge to the data output
is about 9 ns (DVDD=5 V).
6. Output enable pins
Pins 13 to 20 (A0 to A7) are in the output mode by leaving XAOE open or connecting it to DVSS, and these
pins are in the high impedance mode by connecting XAOE to DVDD. Pins 3 to 10 (B0 to B7) have the same
relationship with XBOE, and Pins 73 to 80 (C0 to C7) with XCOE, respectively.
—25—
VDD (Digital)
REF2
18 19
20 21
22 23
24
41
76
77
78
79
80
C3
C4
C5
C6
C7
0.1µ
GND (Digital)
10 11
9
8
7
6
5
4
3
0.1µ
0.01µ
33
0.01µ 0.1µ
GND (Analog)
25
26
27
28
29
30
31
32
33
0.1µ
0.01µ 0.1µ
0.01µ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
75
B0
C2
B1
C1
B2
74
B3
73
B4
33
B5
72
B6
34
B7
71
A0
35
A1
70
36
16 17
43 42
69
14 15
45 44
37
12 13
47 46
68
A2
C0
10µ
REF1
38
2
CLP
67
1
SEL
39
49 48
A3
0.01µ
SY
51 50
A4
0.1µ
CLK
53 52
A5
33
REF0
55 54
A6
C-ch
input
REF3
57 56
CTL2
66
59 58
CTL1
40
61 60
CTL0
65
64 63 62
0.1µ
A7
—26—
TGR
10µ
0.01µ
10µ
+5V (Analog)
Application Circuit
1. When clamp and self-bias are used
10µ
10µ
A-ch
input
B-ch
input
CXD2303AQ
VDD (Digital)
78
79
80
C4
C5
C6
C7
0.1µ
GND (Digital)
10 11
9
8
7
6
5
4
3
20 21
22 23
24
0.1µ
0.01µ
33
0.01µ 0.1µ
GND (Analog)
25
26
27
28
29
30
31
32
33
0.1µ
0.01µ 0.1µ
0.01µ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
77
10µ
76
B0
C3
B1
75
B2
C2
B3
74
B4
C1
B5
73
B6
C0
B7
33
A0
72
A1
34
A2
71
A3
35
A4
70
36
18 19
41
37
16 17
43 42
69
14 15
45 44
68
12 13
47 46
38
2
49 48
67
1
51 50
A5
0.01µ
CLK
53 52
A6
0.1µ
55 54
A7
—27—
TGR
C-ch 33
input
57 56
SY
39
59 58
CTL2
66
61 60
CTL1
40
64 63 62
0.1µ
CTL0
65
0.01µ
10µ
+5V (Analog)
2. When self-bias is used, and clamp is not used
A-ch
input
B-ch
input
CXD2303AQ
VDD (Digital)
1
2
12 13
14 15
16 17
18 19
47 46
20 21
45 44
22 23
43 42
24
41
37
38
77
78
79
80
C3
C4
C5
C6
C7
0.1µ
GND (Digital)
10 11
9
8
7
6
5
4
3
0.1µ
0.01µ
0.01µ
GND (Analog)
25
26
27
28
29
30
31
32
0.01µ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
76
C2
10µ
75
C1
B0
74
B1
73
B2
C0
B3
33
B4
72
B5
34
B6
71
B7
35
A0
70
A1
36
A2
69
68
67
A3
CRT
49 48
A4
0.01µ
51 50
A5
0.1µ
CLK
53 52
CTL2
39
55 54
SY
66
57 56
A6
C-ch 33
input
59 58
CTL1
40
61 60
0.1µ
CTL0
65
64 63 62
10µ
A7
—28—
TGR
CRB
0.01µ
+5V (Analog)
3. When clamp and self-bias are not used
33
0.1µ
0.1µ
33
0.01µ
0.1µ
A-ch
input
B-ch
input
ARB
ART
BRT
BRB
CXD2303AQ
CXD2303AQ
Example of Representative Characteristics
Supply voltage vs. Supply current
FC=50MHz
NTSC ramp wave input
AVDD=DVDD=5V
CLE=Low
75
70
Supply current [mA]
Supply current [mA]
Ambient temperature vs. Supply current
65
–40
–20
0
25
50
90
80
FC=50MHz
NTSC ramp wave input
AVDD=DVDD
CLE=High
Ta=25°C
70
75 85
4.75
5
5.25
Ambient temperature [°C]
Supply voltage [V]
Sampling frequency vs. Supply current
Input frequency vs. Supply current
50
20
30
40
50
85
FC=50MHz
Sine wave 1.6Vp-p
AVDD=DVDD=5V
Ta=25°C
CLE=Low
70
0.01
0.1
1
10
Sampling frequency [MSPS]
Input frequency [MHz]
Ambient temperature vs. Maximum conversion rate
Supply voltage vs.
Maximum conversion rate
Maximum conversion rate [MSPS]
Maximum conversion rate [MSPS]
10
Sampling delay [ns]
Supply current [mA]
NTSC ramp wave input
AVDD=DVDD=5V
Ta=25°C
FIN=1kHz, triangular wave input
AVDD=DVDD=5V
70
65
60
–20
0
25
50
75
65
NTSC ramp wave input
AVDD=DVDD
63
4.75
5
5.25
Supply voltage [V]
Ambient temperature vs. Sampling delay
Analog input band
FC=10MHz
AVDD=DVDD=5V
4
FC=50MHz
Sine wave 1Vp-p input
AVDD=DVDD=5V
Ta=25°C
0
3
2
25
67
Ambient temperature [°C]
Output level [dB]
Supply current [mA]
100
80
–1
–3
–40
–20
0
25
50
0.1
75 85
Ambient temperature [°C]
1
10
100
Analog input frequency [MHz]
—29—
CXD2303AQ
6
40
5
FC=50MHz
AVDD=DVDD=5V
VIN=2Vp-p
Ta=25°C
60
SFDR [dB]
SNR [dB]
7
Analog input frequency vs. SFDR
FC=50MHz
AVDD=DVDD=5V
VIN=2Vp-p
Ta=25°C
50
8
30
50
40
0.1
1
10
0.1
Analog input frequency [MHz]
12
10
tpLH
8
tpHL
6
12
tpLH
10
–20
0
25
50
tpHL
75 85
–40
–20
Ambient temperature [°C]
Output data delay [ns]
8
tpHL
6
75 85
12
15
20
Fc=10MHz
AVDD=5V
DVDD=3.3V
Ta=25°C
tpLH
10
8
6
10
50
Load capacitance vs. Output data delay
tpHL
0
25
5
10
15
20
25
Load capacitance [pF]
Load capacitance [pF]
DVDD supply voltage vs. Output data delay
Analog input voltage vs. Input current
Analog input current IAI [mA]
Output data delay [ns]
tpLH
10
5
25
14
Fc=10MHz
AVDD=DVDD=5V
Ta=25°C
0
0
Ambient temperature [°C]
Load capacitance vs. Output data delay
12
Fc=10MHz
AVDD=5V
DVDD=3.3V
CL=15pF
8
6
–40
10
Ambient temperature vs. Output data delay
Output data delay [ns]
Output data delay [ns]
Fc=10MHz
AVDD=DVDD=5V
CL=15pF
1
Analog input frequency [MHz]
Ambient temperature vs. Output data delay
Output data delay [ns]
Effective bit [bit]
Analog input frequency vs. SNR, effective bit
FC=10MHz
AVDD=5V
CL=15pF
Ta=25°C
12
10
8
6
3
3.5
4
4.5
5
80
FC=50MHz
AVDD=DVDD=5V
VRT=2.5V
VRB=0.5V
Ta=25°C
0
–80
0.5
5.5
DVDD supply voltage [V]
1.5
Analog input voltage VIN [V]
—30—
2.5
CXD2303AQ
Input frequency vs. Cross talk
FC=50MHz
AVDD=DVDD=5V
VIN=1.6Vp-p
Ta=25°C
Cross talk CT [dB]
50
40
30
0.1
1
10
24
Input frequency FIN [MHz]
—31—
CXD2303AQ
CXD2303Q Evaluation Board
Evaluation boards are available for the CMOS converter CXD2303AQ.
Block Diagram
External Clamp
clock
pulse
Buffers
Digital
Circuit
Mount
Portion
Characteristics
• Resolution
• Maximum conversion rate
• Supply voltage
CXD2303AQ
Digit SW
Min.
Analog Input
Interface
Analog
input
Analog
Circuit
Mount
Portion
8 bits
50 MHz
±5.0 V (Single +5 V power supply possible at self-bias use)
Supply voltage
Item
+5 V
–5 V
GND –5V
Analog
Circuit
Mount
Portion
Data Latch
CXD1178Q
3ch 8-bit DAC
Digital
Circuit
Mount
Portion
Analog
output
+5V
Typ.
Max.
185
20
Unit
mA
Clock input
Either 1 or 2 should be used.
1. TTL
Pulse width
TCW1 9 ns (min.)
TCW0 9 ns (min.)
2. Sine wave
—32—
CXD2303AQ
(RL = 200 Ω)
Analog Output (CXD1178Q)
Item
Analog output
Full-scale
output ratio (∗)
∗
Min.
1.8
Typ.
2.0
Max.
2.2
Unit
V
0
1.5
3
%
Full-scale voltage of each channel
Average of the full-scale voltage of each channel
Full-scale output ratio =
Output Format (CXD2303AQ)
The table shows the output format of AD converter.
Analog input
voltage
VART, VBRT, VCRT
:
:
:
:
VARB, VBRB, VCRB
Digital output code
MSB
LSB
1 1 1 1 1 1 1 1
:
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
:
0 0 0 0 0 0 0 0
Step
0
:
127
128
:
255
Timing Chart
Analog input
External clock
tPW1
AD clock
tPW0
1.3V
tPD (AD)
AD output
tPD
Latch output
DA input
tH
tS
DA clock
1.3V
tPD (DA)
100%
DA output
50%
0%
—33—
–1 × 100 [%]
CXD2303AQ
Item
External clock (∗)
Clock High time
Clock Low time
Data delay (AD)
Data delay (latch)
Setup time
Hold time
Propagation delay time (DA)
Symbol
TPW1
TPW0
tPD (AD)
tDD
tS
th
tPD (DA)
Min.
1
9
9
4.5
5
10
Typ.
Max.
1100
1100
11.0
9.5
10
10
Unit
V
ns
ns
ns
ns
ns
ns
ns
∗ In the case of a sine wave, the effects of jitter increase as the input voltage decreases.
List of Parts
Resistor
R20
R21
R30A, B, C
R31A, B, C
R32A, B, C
R33A, B, C
R34A, B, C
R35A, B, C
R50
R51
R52
R53
VR20
VR21
VR30A, B, V
VR31A, B, V
VR50
75 Ω
75 Ω
510 Ω
510 Ω
510 Ω
100 kΩ
75 Ω
33 kΩ
3.3 kΩ
200 Ω
200 Ω
200 Ω
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
Transistor
Q30A, B, C
Q31A, B, C
Q32A, B, C
2SC2785
2SC2785
2SC2785
IC
IC1
IC2
IC3
IC4
IC5
IC6
CXD2303AQ
74F821
74F574
74F574
74F04
CXD1178Q
Capacitor
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C20
C21
C22
C30A, B, C
C31A, B, C
C30A, B, C
C50
C51
C52
C53
Others
Connector
DIP SW
—34—
0.1 µF
0.1 µF
10 µF
0.1 µF
0.1 µF
10 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
47 µF
47 µF
0.1 µF
0.1 µF
0.1 µF
47 µF
0.1 µF
470 µF
10 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
BNC-LR-PC-3 (Hirose Electric Co.,Ltd.)
C52
R53 R52 R51
200 200 200
75
R20
C51
C53
VR20
2k
75
R21
37
38
39
40
41
42
43
44
45
46
47
48
R50
3.3k
C50
VR50
1k
VR21
2k
7
14
[IC5]74F04
1 2 3 4 5 6 7 8 9 10 11 12
[IC6]
CXD1178Q
(3ch 8-bit DAC)
24
23
22
21
20
19
18
17
16
15
14
13
C22
4
3
2
36 35 34 33 32 31 30 29 28 27 26 25
47µ
C21
1
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
BB7
BB6
BB5
BB4
Note : Unless otherwise specified, all capacitor values are 0.1.
Aout
Bout
Cout
Clamp
Pulse
Input
8
6
C40A
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
TGB
BB0
BB1
BB2
BB3
BB4
BB5
BB6
BB7
C40B
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
C40C
22
23
13
1
21
20
19
18
17
16
15
14
19
18
17
16
15
14
13
12
20
10
19
18
17
16
15
14
13
12
20
10
3
2
12
24
4
5
6
7
8
9
10
11
2
3
4
5
6
7
8
9
11
1
2
3
4
5
6
7
8
9
11
1
A0
A1
A2
A3
A4
A5
A6
A7
TGR
B0
B1
B2
B3
B4
B5
B6
B7
C0
C1
C2
C3
C4
C5
C6
C7
C3
10µ
CLP
CLK
C2
C1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
analog
+5V
J15
J8
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
A0
A1
A2
A3
A4
A5
A6
A7
TGR
B0
B1
B2
B3
B4
B5
B6
B7
[IC1]
CXD2303AQ
(3ch 8-bit ADC)
SEL
SY
CTL2
CTL1
CTL0
XCOE
XBOE
XAOE
J1
10bit
digit
SW
C4
C5
C7
J3
C8
J4
C9
C10
J6
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
C6
10µ
CLE
REF3
REF2
REF1
REF0
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
ARB
5
AIN
J2
digital
+5V
ART
10
C15
47µ
CRT
12
C7
C6
C5
C4
C3
C2
C1
C0
J11,12
[IC4]74F574
[IC3]74F574
[IC2]74F821
+5V
+5V
GND
+5V
–5V
BRT
CIN
BRB
0.1µ
C20
J10
J9
C13
C14
47µ
BIN
J5
External
Clock
Input
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
BB0
BB1
BB2
BB3
J13
—35—
1 2 3 4 5 6 7 8 9 0
CLE
REF3
REF2
REF1
REF0
SEL
SY
CTL2
CTL1
CTL0
XCOE
XBOE
XAOE
C11
C16
C17
J14
J7
CRB
C12
AIN
R32B
510
VR31B
2k
BRT
Adjust
R34C
75
R34A
75
R35A C31A
33
10µ
R32A
510
VR31A
2k
ART
Adjust
R34B
75
R35B C31B
33
10µ
Q31A
ARB
ART
BIN
R32C
510
VR31C
2k
R35C C31C
10µ
33
Q31B
BRB
BRT
CIN
CRB
CRT
Q31C
CRT
Adjust
TP30B
R33A
100k
VR30A
2k
R30A
510
Video Signal
IN A-ch
TP30A
C30A
470µ
Q32A
R31A
510
Q30A
ARB
Adjust
C30B
470µ
R33B
100k
Q32B
R31B
510
VR30B
2k
R30B
510
Video Signal
IN B-ch
BRB
Adjust
Q30B
VR30C
2k
R30C
510
Video Signal
IN C-ch
TP30C
C30C
470µ
R33C
100k
Q32C
R31C
510
Q30C
CRB
Adjust
CXD2303AQ
CXD2303AQ
Adjustment
1. Vref adjustment (VR30, VR31)
Adjustment of A/D converter reference voltage. ARB, BRB and CRB are adjusted though VR30A, VR30B
and VR30C, respectively, and ART, ARB and CRT through VR31A, VR31B and VR31C. When self-bias is
used, there is no need for adjustment. Reference voltage is set through self-bias delivery.
2. DAC output full-scale adjustment (VR50)
Full-scale voltage of D/A converter output is adjusted to about 2 V at the PCB shipment.
3. Clamp pulse and clock signal DC voltage adjustment (VR20, VR21)
The clamp pulse and the clock signal DC voltages are adjusted.
4. DIP switches
All DIP switches other than CLE are set of OFF when the PCB is shipped from the factory. Only CLE is set
to ON.
Notes on Operation
1. Reference voltage
When ARTS, BRTS and CRTS are connected to AVDD and at the same time ARBS, BRBS and CRBS are
connected to AVSS, the self-bias function causes the ART, BRT and CRT voltage to become about 2.5 V,
and the ARB, BRB, and CRB voltage to become about 0.5 V. On the evaluation board, either self-bias or
the external reference voltage can be selected depending on the junction method of the jumper line. When
shipped from the factory, the reference voltage is set to self-bias. To select the external reference voltage,
adjust the dynamic range (VRT–VRB) to 1.7 Vp-p or more.
2. Clock input
The clock signal should be supplied externally.
3. The three latch ICs (74F574, 74F821) are not absolutely necessary for the evaluation of the ADC and DAC.
That is, operation is performed normally if the ADC output data is directly input to the DAC input. However,
as the ADC output data is hardly ever D/A converted without executing digital signal processing, it was
mounted on the main board to indicate an example layout of digital signal processing IC. Use the latch IC
output when the ADC output data is used.
4. When clamp is not used
Turning CLE to Low will set the clamp function OFF. In this case, the DC element is cut off by means of
C31A, C31B and C31C on the main board and DC voltage on the ADC side of C31A, C31B and C31C
turns to about (VART+VARB) /2, (VBRT+VBRB) /2, and (VCRT+VCRB) 2. To transfer DC elements of input
signals, short C31A, C31B and C31C. At that time, it is necessary to bias input signals, but keeping R34A,
R34B and R34C open, Q32A, Q32B, Q32C can also be used as buffer. Use the open space for the bias circuit.
5. Clamp pulse latch
The latch is incorporated in the CLP pin of the CXD2303AQ.
6. Peripheral through hole
There is a group of through holes on the analog input, output and logic. They are to be used when
mounting additional circuits to the evaluation board. Use when necessary.
The connector hole on the DAC part is used to mount the test chassis mount jack.
—36—
CXD2303AQ
Package Outline
Unit : mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
17.9 ± 0.4
+ 0.4
14.0 – 0.1
40
A
+ 0.2
0.1 – 0.05
25
1
24
0.8
0.2
M
+ 0.15
0.35 – 0.1
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP080-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.6g
JEDEC CODE
—37—
0.8 ± 0.2
80