Data Sheet

74LVC594A-Q100
8-bit shift register with output register
Rev. 1 — 15 November 2013
Product data sheet
1. General description
The 74LVC594A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register. Separate clock and reset inputs are provided on both shift and storage registers.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The shift register has a serial input (DS) and a serial output (Q7S) for cascading
purposes. Data is shifted on the positive-going transitions of the SHCP input. The data in
the shift register is transferred to the storage register on a positive-going transition of the
STCP input. If both clocks are connected together, the shift register is always one clock
pulse ahead of the storage register. A LOW level on one of the two register reset pins
(SHR and STR) clears the corresponding register.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 5 V tolerant inputs/outputs for interfacing with 5 V logic
 Wide supply voltage range from 1.2 V to 3.6 V
 CMOS low-power consumption
 Direct interface with TTL levels
 Balanced propagation delays
 All inputs have Schmitt-trigger action
 Complies with JEDEC standard:
 JESD8-7A (1.65 V to 1.95 V)
 JESD8-5A (2.3 V to 2.7 V)
 JESD8-C/JESD36 (2.7 V to 3.6 V)
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
3. Applications
 Serial-to-parallel data conversion
 Remote control holding register
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC594AD-Q100
40 C to +125 C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74LVC594APW-Q100
40 C to +125 C
TSSOP16
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
SOT403-1
74LVC594ABQ-Q100
40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal
enhanced very thin quad flat package; no
leads; 16 terminals; body 2.5  3.5  0.85 mm
SOT763-1
5. Functional diagram
6+&3 67&3
'6
Fig 1.
74LVC594A_Q100
Product data sheet
4
4
Logic symbol
46
6+5
675
4
4
4
4
4
4
'6
6+&3
6+5
67$*(6+,)75(*,67(5
67&3
675
%,76725$*(5(*,67(5
4 4 4 4 4 4 4 4
PEF
Fig 2.
46
PEF
Functional diagram
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Rev. 1 — 15 November 2013
© NXP B.V. 2013. All rights reserved.
2 of 20
74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
67$*(672
67$*(
'6
'
'
4
67$*(
4
'
46
4
))6+
))6+
&3
&3
5
5
6+&3
6+5
'
'
4
))67
4
))67
&3
&3
5
5
67&3
675
4
Fig 3.
4 4 4 4 4 4
4
PEF
Logic diagram
6+&3
'6
67&3
6+5
675
4
4
4
4
46
PEF
Fig 4.
Timing diagram
74LVC594A_Q100
Product data sheet
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Rev. 1 — 15 November 2013
© NXP B.V. 2013. All rights reserved.
3 of 20
74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
6. Pinning information
6.1 Pinning
4
WHUPLQDO
LQGH[DUHD
/9&$4
'6
4
4
4
675
4
'6
4
67&3
4
675
4
6+&3
4
67&3
4
6+5
4
6+&3
4
6+5
*1'
46
4
4
4
46
9&&
*1'
4
DDD
7UDQVSDUHQWWRSYLHZ
DDD
Fig 5.
9&&
/9&$4
Pin configuration SO16 and TSSOP16
Fig 6.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
15, 1, 2, 3, 4, 5, 6, 7
parallel data output
GND
8
ground (0 V)
Q7S
9
serial data output
SHR
10
shift register reset (active LOW)
SHCP
11
shift register clock input
STCP
12
storage register clock input
STR
13
storage register reset (active LOW)
DS
14
serial data input
VCC
16
supply voltage
74LVC594A_Q100
Product data sheet
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Rev. 1 — 15 November 2013
© NXP B.V. 2013. All rights reserved.
4 of 20
74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
7. Functional description
Function table[1]
Table 3.
Input
Output
Function
SHCP STCP SHR
STR
DS
Q7S
Qn
X
X
X
L
NC
X
L
a LOW-state on SHR only affects the shift register
X
X
X
L
X
NC
L
a LOW-state on STR only affects the storage register
X

L
H
X
L
L
empty shift register loaded into storage register

X
H
X
H
Q6S
NC
logic HIGH level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X

H
H
X
NC
QnS
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages


H
H
X
Q6S
QnS
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
[1]
H = HIGH voltage state;
L = LOW voltage state;
 = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
output voltage
VO
Conditions
VI < 0 V
[1]
Min
Max
Unit
0.5
+6.5
V
50
-
mA
0.5
+6.5
V
-
50
mA
3-state
[1]
0.5
6.5
V
output HIGH or LOW state
[1]
0.5
VCC + 0.5
V
-
50
mA
VO > VCC or VO < 0 V
IO
output current
VO = 0 V to VCC
ICC
supply current
-
100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
-
500
mW
Tamb = 40 C to +125 C
[2]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
74LVC594A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 November 2013
© NXP B.V. 2013. All rights reserved.
5 of 20
74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
VCC
supply voltage
VI
input voltage
VO
output voltage
Min
Typ
Max
Unit
1.65
-
3.6
V
functional
1.2
-
-
V
0
-
5.5
V
3-state
0
-
5.5
V
output HIGH or LOW state
0
-
VCC
V
40
-
+125
C
-
-
20
ns/V
-
-
10
ns/V
Tamb
ambient temperature
t/V
input transition rise and fall rate VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 3.6 V
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Min
VIH
VIL
VOH
VOL
II
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output
voltage
LOW-level
output
voltage
VCC = 1.2 V
Product data sheet
40 C to +125 C
Max
Min
Max
Unit
1.08
-
-
1.08
-
V
0.65  VCC
-
-
0.65  VCC
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
0.12
V
VCC = 1.65 V to 1.95 V
VCC = 1.2 V
-
-
0.12
-
VCC = 1.65 V to 1.95 V
-
-
0.35  VCC
-
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC  0.2
-
-
VCC  0.3
-
V
IO = 4 mA; VCC = 1.65 V
1.2
-
-
1.05
-
V
IO = 8 mA; VCC = 2.3 V
1.8
-
-
1.65
-
V
IO = 12 mA; VCC = 2.7 V
2.2
-
-
2.05
-
V
IO = 18 mA; VCC = 3.0 V
2.4
-
-
2.25
-
V
IO = 24 mA; VCC = 3.0 V
2.2
-
-
2.0
-
V
IO = 100 A;
VCC = 1.65 V to 3.6 V
-
-
0.2
-
0.3
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
-
0.65
V
IO = 8 mA; VCC = 2.3 V
-
-
0.6
-
0.8
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
-
0.6
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
-
0.8
V
-
0.1
5
-
20
A
0.35  VCC V
VI = VIH or VIL
IO = 100 A;
VCC = 1.65 V to 3.6 V
VI = VIH or VIL
input leakage VCC = 3.6 V; VI = 5.5 V or GND
current
74LVC594A_Q100
Typ[1]
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Rev. 1 — 15 November 2013
© NXP B.V. 2013. All rights reserved.
6 of 20
74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
40 C to +125 C
Min
Typ[1]
Max
Min
Max
Unit
IOFF
power-off
leakage
current
VCC = 0 V; VI or VO = 5.5 V
-
0.1
10
-
20
A
ICC
supply
current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
0.1
10
-
40
A
ICC
additional
supply
current
per input pin;
VCC = 1.65 V to 3.6 V;
VI = VCC  0.6 V; IO = 0 A
-
5
500
-
5000
A
CI
input
capacitance
VCC = 0 V to 3.6 V;
VI = GND to VCC
-
5.0
-
-
-
pF
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.
Symbol Parameter
tpd
40 C to +85 C
Conditions
propagation delay SHCP to Q7S; see Figure 7
Max
Min
Unit
Max
-
17.5
-
-
-
ns
VCC = 1.65 V to 1.95 V
2.0
5.2
15.8
2.0
18.2
ns
VCC = 2.3 V to 2.7 V
1.5
3.2
8.1
1.5
9.3
ns
VCC = 2.7 V
1.5
3.5
7.6
1.5
8.7
ns
1.5
3.1
6.7
1.5
7.7
ns
-
19.3
-
-
-
ns
2.0
7.6
15.8
2.0
18.2
ns
VCC = 2.3 V to 2.7 V
1.5
4.8
8.1
1.5
9.3
ns
VCC = 2.7 V
1.5
5.2
7.6
1.5
8.7
ns
VCC = 3.0 V to 3.6 V
1.2
4.5
6.7
1.2
7.7
ns
VCC = 3.0 V to 3.6 V
STCP to Qn; see Figure 8
VCC = 1.2 V
VCC = 1.65 V to 1.95 V
Product data sheet
40 C to +125 C
[2]
VCC = 1.2 V
74LVC594A_Q100
Min
Typ[1]
[2]
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Rev. 1 — 15 November 2013
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7 of 20
74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.
Symbol Parameter
tPHL
40 C to +85 C
Conditions
HIGH to LOW
SHR to Q7S; see Figure 11
propagation delay
VCC = 1.2 V
Min
Typ[1]
40 C to +125 C
Max
Min
Unit
Max
-
12.0
-
-
-
ns
VCC = 1.65 V to 1.95 V
2.0
5.0
15.8
2.0
18.2
ns
VCC = 2.3 V to 2.7 V
1.5
3.8
8.1
1.5
9.3
ns
VCC = 2.7 V
1.2
3.9
7.6
1.2
8.7
ns
VCC = 3.0 V to 3.6 V
1.2
3.3
6.7
1.2
7.7
ns
-
20.0
-
-
-
ns
2.0
7.7
15.8
2.0
18.2
ns
VCC = 2.3 V to 2.7 V
1.5
5.0
8.1
1.5
9.3
ns
VCC = 2.7 V
1.2
5.3
7.6
1.2
8.7
ns
VCC = 3.0 V to 3.6 V
1.2
4.4
6.7
1.2
7.7
ns
VCC = 1.65 V to 1.95 V
6.0
2.5
-
7.0
-
ns
VCC = 2.3 V to 2.7 V
5.0
2.0
-
5.5
-
ns
VCC = 2.7 V
4.5
1.5
-
5.0
-
ns
VCC = 3.0 V to 3.6 V
4.0
1.5
-
4.5
-
ns
6.0
2.5
-
5.5
-
ns
STR to Qn; see Figure 12
VCC = 1.2 V
VCC = 1.65 V to 1.95 V
tW
pulse width
SHCP, STCP HIGH or LOW;
see Figure 7 and Figure 8
SHR, STR LOW; see
Figure 11 and Figure 12
VCC = 1.65 V to 1.95 V
tsu
set-up time
VCC = 2.3 V to 2.7 V
4.0
2.0
-
4.5
-
ns
VCC = 2.7 V
2.5
1.5
-
3.0
-
ns
VCC = 3.0 V to 3.6 V
2.5
1.5
-
3.0
-
ns
DS to SHCP; see Figure 9
VCC = 1.65 V to 1.95 V
5.0
1.0
-
5.5
-
ns
VCC = 2.3 V to 2.7 V
4.0
0.8
-
4.5
-
ns
VCC = 2.7 V
2.0
0.6
-
2.5
-
ns
VCC = 3.0 V to 3.6 V
2.0
0.6
-
2.5
-
ns
VCC = 1.65 V to 1.95 V
8.0
3.5
-
8.5
-
ns
VCC = 2.3 V to 2.7 V
5.0
2.1
-
5.5
-
ns
VCC = 2.7 V
4.0
1.8
-
4.5
-
ns
VCC = 3.0 V to 3.6 V
4.0
1.7
-
4.5
-
ns
VCC = 1.65 V to 1.95 V
8.0
3.5
-
8.5
-
ns
VCC = 2.3 V to 2.7 V
5.0
2.1
-
5.5
-
ns
VCC = 2.7 V
4.0
1.8
-
4.5
-
ns
VCC = 3.0 V to 3.6 V
4.0
1.7
-
4.5
-
ns
SHR to STCP; see Figure 10
SHCP to STCP; see Figure 8
74LVC594A_Q100
Product data sheet
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Rev. 1 — 15 November 2013
© NXP B.V. 2013. All rights reserved.
8 of 20
74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.
Symbol Parameter
40 C to +85 C
Conditions
Min
th
hold time
recovery time
trec
maximum
frequency
fmax
Typ[1]
40 C to +125 C
Max
Min
Unit
Max
DS to SHCP; see Figure 9
VCC = 1.65 V to 1.95 V
1.5
0.2
-
2.0
-
ns
VCC = 2.3 V to 2.7 V
1.5
0.1
-
2.0
-
ns
VCC = 2.7 V
+1.5
0.1
-
+2.0
-
ns
VCC = 3.0 V to 3.6 V
+1.0
0.2
-
+1.5
-
ns
VCC = 1.65 V to 1.95 V
+5.0
2.7
-
+5.5
-
ns
VCC = 2.3 V to 2.7 V
+4.0
1.5
-
+4.5
-
ns
VCC = 2.7 V
+2.0
1.0
-
+2.5
-
ns
VCC = 3.0 V to 3.6 V
+2.0
1.0
-
+2.5
-
ns
SHR to SHCP, STR to STCP;
see Figure 11 and Figure 12
SHCP or STCP; see Figure 7
and Figure 8
VCC = 1.65 V to 1.95 V
80
130
-
70
-
MHz
VCC = 2.3 V to 2.7 V
100
140
-
90
-
MHz
VCC = 2.7 V
110
150
-
100
-
MHz
130
180
-
115
-
MHz
-
-
1.0
-
1.5
ns
VCC = 1.65 V to 1.95 V
-
50
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
45
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
44
-
-
-
pF
VCC = 3.0 V to 3.6 V
tsk(o)
output skew time
VCC = 3.0 V to 3.6 V
[3]
CPD
power dissipation
capacitance
VI = GND to VCC
[4]
[1]
Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2]
tpd is the same as tPLH and tPHL.
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
74LVC594A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 November 2013
© NXP B.V. 2013. All rights reserved.
9 of 20
74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
12. Waveforms
1/fmax
VI
SHCP input
VM
GND
tW
t PHL
t PLH
VOH
VM
Q 7S output
VOL
mna557
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 7.
The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and
maximum shift clock frequency
VI
SHCP input
VM
GND
1/fmax
t su
VI
STCP input
VM
GND
tW
t PHL
t PLH
VOH
VM
Q n output
VOL
mna558
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 8.
The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width
and the shift clock to storage clock set-up time
74LVC594A_Q100
Product data sheet
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Rev. 1 — 15 November 2013
© NXP B.V. 2013. All rights reserved.
10 of 20
74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
VI
VM
SHCP input
GND
t su
t su
th
th
VI
VM
DS input
GND
VOH
VM
Q 7S output
VOL
mna560
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 9.
The data set-up and hold times for the serial data input (DS)
6+5LQSXW
90
WVX
67&3LQSXW
4QRXWSXWV
90
90
PEF
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 10. The shift reset (SHR) to storage clock (STCP) set-up times
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74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
6+5LQSXW
90
W:
WUHF
90
6+&3LQSXW
W3+/
90
46RXWSXW
PEF
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 11. The shift reset (SHR) pulse width, the shift reset to serial data output (Q7S) propagation delays and the
shift reset to shift clock (SHCP) recovery time
675LQSXW
90
W:
WUHF
90
67&3LQSXW
W3+/
4QRXWSXWV
90
PEF
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 12. The storage reset (STR) pulse width, the storage reset to parallel data output (Qn) propagation delays and
the storage reset to storage clock (STCP) recovery time
Table 8.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VCC < 2.7 V
0.5  VCC
0.5  VCC
VCC  2.7 V
1.5 V
1.5 V
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Product data sheet
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8-bit shift register with output register
W:
9,
QHJDWLYH
SXOVH
90
90
9
WI
WU
WU
WI
9,
SRVLWLYH
SXOVH
90
90
9
W:
9(;7
9&&
*
9,
5/
92
'87
57
5/
&/
DDH
Test data is given in Table 9. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
Input
Load
VEXT
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
VCC
 2 ns
30 pF
1 k
open
2  VCC
GND
1.65 V to 1.95 V
VCC
 2 ns
30 pF
1 k
open
2  VCC
GND
2.3 V to 2.7 V
VCC
 2 ns
30 pF
500 
open
2  VCC
GND
2.7 V
2.7 V
 2.5 ns
50 pF
500 
open
2  VCC
GND
3.0 V to 3.6 V
2.7 V
 2.5 ns
50 pF
500 
open
2  VCC
GND
1.2 V
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Product data sheet
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8-bit shift register with output register
13. Package outline
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74LVC594A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 November 2013
© NXP B.V. 2013. All rights reserved.
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74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
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Fig 15. Package outline SOT403-1 (TSSOP16)
74LVC594A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 November 2013
© NXP B.V. 2013. All rights reserved.
15 of 20
74LVC594A-Q100
NXP Semiconductors
8-bit shift register with output register
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Fig 16. Package outline SOT763-1 (DHVQFN16)
74LVC594A_Q100
Product data sheet
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Rev. 1 — 15 November 2013
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8-bit shift register with output register
14. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC594A_Q100 v.1
20131115
Product data sheet
-
-
74LVC594A_Q100
Product data sheet
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NXP Semiconductors
8-bit shift register with output register
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC594A_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 November 2013
© NXP B.V. 2013. All rights reserved.
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8-bit shift register with output register
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Product data sheet
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Rev. 1 — 15 November 2013
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8-bit shift register with output register
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 15 November 2013
Document identifier: 74LVC594A_Q100